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1 | /* |
2 | * ARM Ltd. Juno Platform | |
3 | * | |
4 | * Copyright (c) 2015 ARM Ltd. | |
5 | * | |
6 | * This file is licensed under a dual GPLv2 or BSD license. | |
7 | */ | |
8 | ||
9 | /dts-v1/; | |
10 | ||
11 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
12 | ||
13 | / { | |
14 | model = "ARM Juno development board (r1)"; | |
15 | compatible = "arm,juno-r1", "arm,juno", "arm,vexpress"; | |
16 | interrupt-parent = <&gic>; | |
17 | #address-cells = <2>; | |
18 | #size-cells = <2>; | |
19 | ||
20 | aliases { | |
21 | serial0 = &soc_uart0; | |
22 | }; | |
23 | ||
24 | chosen { | |
25 | stdout-path = "serial0:115200n8"; | |
26 | }; | |
27 | ||
28 | psci { | |
29 | compatible = "arm,psci-0.2"; | |
30 | method = "smc"; | |
31 | }; | |
32 | ||
33 | cpus { | |
34 | #address-cells = <2>; | |
35 | #size-cells = <0>; | |
36 | ||
37 | A57_0: cpu@0 { | |
38 | compatible = "arm,cortex-a57","arm,armv8"; | |
39 | reg = <0x0 0x0>; | |
40 | device_type = "cpu"; | |
41 | enable-method = "psci"; | |
42 | next-level-cache = <&A57_L2>; | |
43 | }; | |
44 | ||
45 | A57_1: cpu@1 { | |
46 | compatible = "arm,cortex-a57","arm,armv8"; | |
47 | reg = <0x0 0x1>; | |
48 | device_type = "cpu"; | |
49 | enable-method = "psci"; | |
50 | next-level-cache = <&A57_L2>; | |
51 | }; | |
52 | ||
53 | A53_0: cpu@100 { | |
54 | compatible = "arm,cortex-a53","arm,armv8"; | |
55 | reg = <0x0 0x100>; | |
56 | device_type = "cpu"; | |
57 | enable-method = "psci"; | |
58 | next-level-cache = <&A53_L2>; | |
59 | }; | |
60 | ||
61 | A53_1: cpu@101 { | |
62 | compatible = "arm,cortex-a53","arm,armv8"; | |
63 | reg = <0x0 0x101>; | |
64 | device_type = "cpu"; | |
65 | enable-method = "psci"; | |
66 | next-level-cache = <&A53_L2>; | |
67 | }; | |
68 | ||
69 | A53_2: cpu@102 { | |
70 | compatible = "arm,cortex-a53","arm,armv8"; | |
71 | reg = <0x0 0x102>; | |
72 | device_type = "cpu"; | |
73 | enable-method = "psci"; | |
74 | next-level-cache = <&A53_L2>; | |
75 | }; | |
76 | ||
77 | A53_3: cpu@103 { | |
78 | compatible = "arm,cortex-a53","arm,armv8"; | |
79 | reg = <0x0 0x103>; | |
80 | device_type = "cpu"; | |
81 | enable-method = "psci"; | |
82 | next-level-cache = <&A53_L2>; | |
83 | }; | |
84 | ||
85 | A57_L2: l2-cache0 { | |
86 | compatible = "cache"; | |
87 | }; | |
88 | ||
89 | A53_L2: l2-cache1 { | |
90 | compatible = "cache"; | |
91 | }; | |
92 | }; | |
93 | ||
94 | pmu { | |
95 | compatible = "arm,armv8-pmuv3"; | |
96 | interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>, | |
97 | <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>, | |
98 | <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, | |
99 | <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, | |
100 | <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, | |
101 | <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
102 | interrupt-affinity = <&A57_0>, | |
103 | <&A57_1>, | |
104 | <&A53_0>, | |
105 | <&A53_1>, | |
106 | <&A53_2>, | |
107 | <&A53_3>; | |
108 | }; | |
109 | ||
110 | #include "juno-base.dtsi" | |
111 | ||
112 | }; | |
113 | ||
114 | &memtimer { | |
115 | status = "okay"; | |
116 | }; |