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Commit | Line | Data |
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90556ca1 PM |
1 | /* |
2 | * ARM Ltd. Fast Models | |
3 | * | |
4 | * Versatile Express (VE) system model | |
5 | * Motherboard component | |
6 | * | |
7 | * VEMotherBoard.lisa | |
8 | */ | |
9 | ||
10 | motherboard { | |
11 | arm,v2m-memory-map = "rs1"; | |
12 | compatible = "arm,vexpress,v2m-p1", "simple-bus"; | |
13 | #address-cells = <2>; /* SMB chipselect number and offset */ | |
14 | #size-cells = <1>; | |
15 | #interrupt-cells = <1>; | |
16 | ranges; | |
17 | ||
18 | flash@0,00000000 { | |
19 | compatible = "arm,vexpress-flash", "cfi-flash"; | |
20 | reg = <0 0x00000000 0x04000000>, | |
21 | <4 0x00000000 0x04000000>; | |
22 | bank-width = <4>; | |
23 | }; | |
24 | ||
e2b6b35e | 25 | v2m_video_ram: vram@2,00000000 { |
90556ca1 PM |
26 | compatible = "arm,vexpress-vram"; |
27 | reg = <2 0x00000000 0x00800000>; | |
28 | }; | |
29 | ||
30 | ethernet@2,02000000 { | |
31 | compatible = "smsc,lan91c111"; | |
32 | reg = <2 0x02000000 0x10000>; | |
33 | interrupts = <15>; | |
34 | }; | |
35 | ||
36 | v2m_clk24mhz: clk24mhz { | |
37 | compatible = "fixed-clock"; | |
38 | #clock-cells = <0>; | |
39 | clock-frequency = <24000000>; | |
40 | clock-output-names = "v2m:clk24mhz"; | |
41 | }; | |
42 | ||
43 | v2m_refclk1mhz: refclk1mhz { | |
44 | compatible = "fixed-clock"; | |
45 | #clock-cells = <0>; | |
46 | clock-frequency = <1000000>; | |
47 | clock-output-names = "v2m:refclk1mhz"; | |
48 | }; | |
49 | ||
50 | v2m_refclk32khz: refclk32khz { | |
51 | compatible = "fixed-clock"; | |
52 | #clock-cells = <0>; | |
53 | clock-frequency = <32768>; | |
54 | clock-output-names = "v2m:refclk32khz"; | |
55 | }; | |
56 | ||
57 | iofpga@3,00000000 { | |
2ef7d5f3 | 58 | compatible = "simple-bus"; |
90556ca1 PM |
59 | #address-cells = <1>; |
60 | #size-cells = <1>; | |
61 | ranges = <0 3 0 0x200000>; | |
62 | ||
63 | v2m_sysreg: sysreg@010000 { | |
64 | compatible = "arm,vexpress-sysreg"; | |
65 | reg = <0x010000 0x1000>; | |
66 | gpio-controller; | |
67 | #gpio-cells = <2>; | |
68 | }; | |
69 | ||
70 | v2m_sysctl: sysctl@020000 { | |
71 | compatible = "arm,sp810", "arm,primecell"; | |
72 | reg = <0x020000 0x1000>; | |
73 | clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; | |
74 | clock-names = "refclk", "timclk", "apb_pclk"; | |
75 | #clock-cells = <1>; | |
76 | clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; | |
341a670a SB |
77 | assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>; |
78 | assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>; | |
90556ca1 PM |
79 | }; |
80 | ||
81 | aaci@040000 { | |
82 | compatible = "arm,pl041", "arm,primecell"; | |
83 | reg = <0x040000 0x1000>; | |
84 | interrupts = <11>; | |
85 | clocks = <&v2m_clk24mhz>; | |
86 | clock-names = "apb_pclk"; | |
87 | }; | |
88 | ||
89 | mmci@050000 { | |
90 | compatible = "arm,pl180", "arm,primecell"; | |
91 | reg = <0x050000 0x1000>; | |
92 | interrupts = <9 10>; | |
93 | cd-gpios = <&v2m_sysreg 0 0>; | |
94 | wp-gpios = <&v2m_sysreg 1 0>; | |
95 | max-frequency = <12000000>; | |
96 | vmmc-supply = <&v2m_fixed_3v3>; | |
97 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; | |
98 | clock-names = "mclk", "apb_pclk"; | |
99 | }; | |
100 | ||
101 | kmi@060000 { | |
102 | compatible = "arm,pl050", "arm,primecell"; | |
103 | reg = <0x060000 0x1000>; | |
104 | interrupts = <12>; | |
105 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; | |
106 | clock-names = "KMIREFCLK", "apb_pclk"; | |
107 | }; | |
108 | ||
109 | kmi@070000 { | |
110 | compatible = "arm,pl050", "arm,primecell"; | |
111 | reg = <0x070000 0x1000>; | |
112 | interrupts = <13>; | |
113 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; | |
114 | clock-names = "KMIREFCLK", "apb_pclk"; | |
115 | }; | |
116 | ||
117 | v2m_serial0: uart@090000 { | |
118 | compatible = "arm,pl011", "arm,primecell"; | |
119 | reg = <0x090000 0x1000>; | |
120 | interrupts = <5>; | |
121 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; | |
122 | clock-names = "uartclk", "apb_pclk"; | |
123 | }; | |
124 | ||
125 | v2m_serial1: uart@0a0000 { | |
126 | compatible = "arm,pl011", "arm,primecell"; | |
127 | reg = <0x0a0000 0x1000>; | |
128 | interrupts = <6>; | |
129 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; | |
130 | clock-names = "uartclk", "apb_pclk"; | |
131 | }; | |
132 | ||
133 | v2m_serial2: uart@0b0000 { | |
134 | compatible = "arm,pl011", "arm,primecell"; | |
135 | reg = <0x0b0000 0x1000>; | |
136 | interrupts = <7>; | |
137 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; | |
138 | clock-names = "uartclk", "apb_pclk"; | |
139 | }; | |
140 | ||
141 | v2m_serial3: uart@0c0000 { | |
142 | compatible = "arm,pl011", "arm,primecell"; | |
143 | reg = <0x0c0000 0x1000>; | |
144 | interrupts = <8>; | |
145 | clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; | |
146 | clock-names = "uartclk", "apb_pclk"; | |
147 | }; | |
148 | ||
149 | wdt@0f0000 { | |
150 | compatible = "arm,sp805", "arm,primecell"; | |
151 | reg = <0x0f0000 0x1000>; | |
152 | interrupts = <0>; | |
153 | clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; | |
154 | clock-names = "wdogclk", "apb_pclk"; | |
155 | }; | |
156 | ||
157 | v2m_timer01: timer@110000 { | |
158 | compatible = "arm,sp804", "arm,primecell"; | |
159 | reg = <0x110000 0x1000>; | |
160 | interrupts = <2>; | |
161 | clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; | |
162 | clock-names = "timclken1", "timclken2", "apb_pclk"; | |
163 | }; | |
164 | ||
165 | v2m_timer23: timer@120000 { | |
166 | compatible = "arm,sp804", "arm,primecell"; | |
167 | reg = <0x120000 0x1000>; | |
168 | interrupts = <3>; | |
169 | clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; | |
170 | clock-names = "timclken1", "timclken2", "apb_pclk"; | |
171 | }; | |
172 | ||
173 | rtc@170000 { | |
174 | compatible = "arm,pl031", "arm,primecell"; | |
175 | reg = <0x170000 0x1000>; | |
176 | interrupts = <4>; | |
177 | clocks = <&v2m_clk24mhz>; | |
178 | clock-names = "apb_pclk"; | |
179 | }; | |
180 | ||
181 | clcd@1f0000 { | |
182 | compatible = "arm,pl111", "arm,primecell"; | |
183 | reg = <0x1f0000 0x1000>; | |
e2b6b35e | 184 | interrupt-names = "combined"; |
90556ca1 PM |
185 | interrupts = <14>; |
186 | clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; | |
187 | clock-names = "clcdclk", "apb_pclk"; | |
e2b6b35e CM |
188 | arm,pl11x,framebuffer = <0x18000000 0x00180000>; |
189 | memory-region = <&v2m_video_ram>; | |
190 | max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */ | |
191 | ||
192 | port { | |
193 | v2m_clcd_pads: endpoint { | |
194 | remote-endpoint = <&v2m_clcd_panel>; | |
195 | arm,pl11x,tft-r0g0b0-pads = <0 8 16>; | |
196 | }; | |
197 | }; | |
198 | ||
199 | panel { | |
200 | compatible = "panel-dpi"; | |
201 | ||
202 | port { | |
203 | v2m_clcd_panel: endpoint { | |
204 | remote-endpoint = <&v2m_clcd_pads>; | |
205 | }; | |
206 | }; | |
207 | ||
208 | panel-timing { | |
209 | clock-frequency = <63500127>; | |
210 | hactive = <1024>; | |
211 | hback-porch = <152>; | |
212 | hfront-porch = <48>; | |
213 | hsync-len = <104>; | |
214 | vactive = <768>; | |
215 | vback-porch = <23>; | |
216 | vfront-porch = <3>; | |
217 | vsync-len = <4>; | |
218 | }; | |
219 | }; | |
90556ca1 | 220 | }; |
1bb2cbb6 | 221 | |
207b6e6b | 222 | virtio-block@0130000 { |
1bb2cbb6 MH |
223 | compatible = "virtio,mmio"; |
224 | reg = <0x130000 0x200>; | |
225 | interrupts = <42>; | |
226 | }; | |
90556ca1 PM |
227 | }; |
228 | ||
6d6acd14 | 229 | v2m_fixed_3v3: v2m-3v3 { |
90556ca1 PM |
230 | compatible = "regulator-fixed"; |
231 | regulator-name = "3V3"; | |
232 | regulator-min-microvolt = <3300000>; | |
233 | regulator-max-microvolt = <3300000>; | |
234 | regulator-always-on; | |
235 | }; | |
236 | ||
237 | mcc { | |
3b9334ac | 238 | compatible = "arm,vexpress,config-bus"; |
90556ca1 PM |
239 | arm,vexpress,config-bridge = <&v2m_sysreg>; |
240 | ||
6d6acd14 | 241 | v2m_oscclk1: oscclk1 { |
90556ca1 PM |
242 | /* CLCD clock */ |
243 | compatible = "arm,vexpress-osc"; | |
244 | arm,vexpress-sysreg,func = <1 1>; | |
245 | freq-range = <23750000 63500000>; | |
246 | #clock-cells = <0>; | |
247 | clock-output-names = "v2m:oscclk1"; | |
248 | }; | |
249 | ||
6d6acd14 | 250 | reset { |
90556ca1 PM |
251 | compatible = "arm,vexpress-reset"; |
252 | arm,vexpress-sysreg,func = <5 0>; | |
253 | }; | |
254 | ||
6d6acd14 | 255 | muxfpga { |
90556ca1 PM |
256 | compatible = "arm,vexpress-muxfpga"; |
257 | arm,vexpress-sysreg,func = <7 0>; | |
258 | }; | |
259 | ||
6d6acd14 | 260 | shutdown { |
90556ca1 PM |
261 | compatible = "arm,vexpress-shutdown"; |
262 | arm,vexpress-sysreg,func = <8 0>; | |
263 | }; | |
264 | ||
6d6acd14 | 265 | reboot { |
90556ca1 PM |
266 | compatible = "arm,vexpress-reboot"; |
267 | arm,vexpress-sysreg,func = <9 0>; | |
268 | }; | |
269 | ||
6d6acd14 | 270 | dvimode { |
90556ca1 PM |
271 | compatible = "arm,vexpress-dvimode"; |
272 | arm,vexpress-sysreg,func = <11 0>; | |
273 | }; | |
274 | }; | |
275 | }; |