[mirror_ubuntu-eoan-kernel.git] / arch / arm64 / boot / dts / broadcom / ns2.dtsi

/*
 *  BSD LICENSE
 *
 *  Copyright (c) 2015 Broadcom.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/bcm-ns2.h>

/ {
	compatible = "brcm,ns2";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		A57_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0 0>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER0_L2>;
		};

		A57_1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0 1>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER0_L2>;
		};

		A57_2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0 2>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER0_L2>;
		};

		A57_3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0 3>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER0_L2>;
		};

		CLUSTER0_L2: l2-cache@000 {
			compatible = "cache";
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
			      IRQ_TYPE_EDGE_RISING)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
			      IRQ_TYPE_EDGE_RISING)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
			      IRQ_TYPE_EDGE_RISING)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
			      IRQ_TYPE_EDGE_RISING)>;
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&A57_0>,
				     <&A57_1>,
				     <&A57_2>,
				     <&A57_3>;
	};

	pcie0: pcie@20020000 {
		compatible = "brcm,iproc-pcie";
		reg = <0 0x20020000 0 0x1000>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &gic GIC_SPI 281 IRQ_TYPE_NONE>;

		linux,pci-domain = <0>;

		bus-range = <0x00 0xff>;

		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;

		brcm,pcie-ob;
		brcm,pcie-ob-oarr-size;
		brcm,pcie-ob-axi-offset = <0x00000000>;
		brcm,pcie-ob-window-size = <256>;

		status = "disabled";

		msi-parent = <&msi0>;
		msi0: msi@20020000 {
			compatible = "brcm,iproc-msi";
			msi-controller;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 277 IRQ_TYPE_NONE>,
				     <GIC_SPI 278 IRQ_TYPE_NONE>,
				     <GIC_SPI 279 IRQ_TYPE_NONE>,
				     <GIC_SPI 280 IRQ_TYPE_NONE>;
			brcm,num-eq-region = <1>;
			brcm,num-msi-msg-region = <1>;
		};
	};

	pcie4: pcie@50020000 {
		compatible = "brcm,iproc-pcie";
		reg = <0 0x50020000 0 0x1000>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &gic GIC_SPI 305 IRQ_TYPE_NONE>;

		linux,pci-domain = <4>;

		bus-range = <0x00 0xff>;

		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;

		brcm,pcie-ob;
		brcm,pcie-ob-oarr-size;
		brcm,pcie-ob-axi-offset = <0x30000000>;
		brcm,pcie-ob-window-size = <256>;

		status = "disabled";

		msi-parent = <&msi4>;
		msi4: msi@50020000 {
			compatible = "brcm,iproc-msi";
			msi-controller;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 301 IRQ_TYPE_NONE>,
				     <GIC_SPI 302 IRQ_TYPE_NONE>,
				     <GIC_SPI 303 IRQ_TYPE_NONE>,
				     <GIC_SPI 304 IRQ_TYPE_NONE>;
		};
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;

		#include "ns2-clock.dtsi"

		dma0: dma@61360000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x61360000 0x1000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			#dma-channels = <8>;
			#dma-requests = <32>;
			clocks = <&iprocslow>;
			clock-names = "apb_pclk";
		};

		smmu: mmu@64000000 {
			compatible = "arm,mmu-500";
			reg = <0x64000000 0x40000>;
			#global-interrupts = <2>;
			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
			mmu-masters;
		};

		gic: interrupt-controller@65210000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x65210000 0x1000>,
			      <0x65220000 0x1000>,
			      <0x65240000 0x2000>,
			      <0x65260000 0x1000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
				      IRQ_TYPE_LEVEL_HIGH)>;
		};

		timer0: timer@66030000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x66030000 0x1000>;
			interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&iprocslow>,
				 <&iprocslow>,
				 <&iprocslow>;
			clock-names = "timer1", "timer2", "apb_pclk";
		};

		timer1: timer@66040000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x66040000 0x1000>;
			interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&iprocslow>,
				 <&iprocslow>,
				 <&iprocslow>;
			clock-names = "timer1", "timer2", "apb_pclk";
		};

		timer2: timer@66050000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x66050000 0x1000>;
			interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&iprocslow>,
				 <&iprocslow>,
				 <&iprocslow>;
			clock-names = "timer1", "timer2", "apb_pclk";
		};

		timer3: timer@66060000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x66060000 0x1000>;
			interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&iprocslow>,
				 <&iprocslow>,
				 <&iprocslow>;
			clock-names = "timer1", "timer2", "apb_pclk";
		};

		i2c0: i2c@66080000 {
			compatible = "brcm,iproc-i2c";
			reg = <0x66080000 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 394 IRQ_TYPE_NONE>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		wdt0: watchdog@66090000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x66090000 0x1000>;
			interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&iprocslow>, <&iprocslow>;
			clock-names = "wdogclk", "apb_pclk";
		};

		i2c1: i2c@660b0000 {
			compatible = "brcm,iproc-i2c";
			reg = <0x660b0000 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 395 IRQ_TYPE_NONE>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		uart3: serial@66130000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x66130000 0x100>;
			interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&osc>;
			status = "disabled";
		};

		ssp0: ssp@66180000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x66180000 0x1000>;
			interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&iprocslow>, <&iprocslow>;
			clock-names = "spiclk", "apb_pclk";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		ssp1: ssp@66190000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x66190000 0x1000>;
			interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&iprocslow>, <&iprocslow>;
			clock-names = "spiclk", "apb_pclk";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		hwrng: hwrng@66220000 {
			compatible = "brcm,iproc-rng200";
			reg = <0x66220000 0x28>;
		};

		sdio0: sdhci@66420000 {
			compatible = "brcm,sdhci-iproc-cygnus";
			reg = <0x66420000 0x100>;
			interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
			bus-width = <8>;
			clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
			status = "disabled";
		};

		sdio1: sdhci@66430000 {
			compatible = "brcm,sdhci-iproc-cygnus";
			reg = <0x66430000 0x100>;
			interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
			bus-width = <8>;
			clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
			status = "disabled";
		};

		nand: nand@66460000 {
			compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
			reg = <0x66460000 0x600>,
			      <0x67015408 0x600>,
			      <0x66460f00 0x20>;
			reg-names = "nand", "iproc-idm", "iproc-ext";
			interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;
			#size-cells = <0>;

			brcm,nand-has-wp;
		};
	};
};
Commit	Line	Data
6aad8bf9 RJ	1	/*
	2	* BSD LICENSE
	3	*
59a5bede	4	* Copyright (c) 2015 Broadcom. All rights reserved.
6aad8bf9 RJ	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions
	8	* are met:
	9	*
	10	* * Redistributions of source code must retain the above copyright
	11	* notice, this list of conditions and the following disclaimer.
	12	* * Redistributions in binary form must reproduce the above copyright
	13	* notice, this list of conditions and the following disclaimer in
	14	* the documentation and/or other materials provided with the
	15	* distribution.
	16	* * Neither the name of Broadcom Corporation nor the names of its
	17	* contributors may be used to endorse or promote products derived
	18	* from this software without specific prior written permission.
	19	*
	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	21	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	22	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	23	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	24	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	25	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	26	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	27	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	28	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	29	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	30	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	31	*/
	32
	33	#include <dt-bindings/interrupt-controller/arm-gic.h>
d8bd64c1	34	#include <dt-bindings/clock/bcm-ns2.h>
6aad8bf9	35
6aad8bf9 RJ	36	/ {
	37	compatible = "brcm,ns2";
	38	interrupt-parent = <&gic>;
	39	#address-cells = <2>;
	40	#size-cells = <2>;
	41
	42	cpus {
	43	#address-cells = <2>;
	44	#size-cells = <0>;
	45
5b31d875	46	A57_0: cpu@0 {
6aad8bf9 RJ	47	device_type = "cpu";
	48	compatible = "arm,cortex-a57", "arm,armv8";
	49	reg = <0 0>;
a9abb475	50	enable-method = "psci";
33a93aa4	51	next-level-cache = <&CLUSTER0_L2>;
6aad8bf9 RJ	52	};
6aad8bf9 RJ	53
5b31d875	54	A57_1: cpu@1 {
6aad8bf9 RJ	55	device_type = "cpu";
	56	compatible = "arm,cortex-a57", "arm,armv8";
	57	reg = <0 1>;
a9abb475	58	enable-method = "psci";
33a93aa4	59	next-level-cache = <&CLUSTER0_L2>;
6aad8bf9 RJ	60	};
6aad8bf9 RJ	61
5b31d875	62	A57_2: cpu@2 {
6aad8bf9 RJ	63	device_type = "cpu";
	64	compatible = "arm,cortex-a57", "arm,armv8";
	65	reg = <0 2>;
a9abb475	66	enable-method = "psci";
33a93aa4	67	next-level-cache = <&CLUSTER0_L2>;
6aad8bf9 RJ	68	};
6aad8bf9 RJ	69
5b31d875	70	A57_3: cpu@3 {
6aad8bf9 RJ	71	device_type = "cpu";
	72	compatible = "arm,cortex-a57", "arm,armv8";
	73	reg = <0 3>;
a9abb475	74	enable-method = "psci";
33a93aa4 AP	75	next-level-cache = <&CLUSTER0_L2>;
	76	};
	77
	78	CLUSTER0_L2: l2-cache@000 {
	79	compatible = "cache";
6aad8bf9 RJ	80	};
	81	};
	82
a9abb475 LS	83	psci {
	84	compatible = "arm,psci-1.0";
	85	method = "smc";
	86	};
	87
6aad8bf9 RJ	88	timer {
	89	compatible = "arm,armv8-timer";
	90	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) \|
	91	IRQ_TYPE_EDGE_RISING)>,
	92	<GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) \|
	93	IRQ_TYPE_EDGE_RISING)>,
	94	<GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) \|
	95	IRQ_TYPE_EDGE_RISING)>,
	96	<GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) \|
	97	IRQ_TYPE_EDGE_RISING)>;
	98	};
	99
5b31d875 AP	100	pmu {
	101	compatible = "arm,armv8-pmuv3";
	102	interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
	103	<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
	104	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	105	<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
	106	interrupt-affinity = <&A57_0>,
	107	<&A57_1>,
	108	<&A57_2>,
	109	<&A57_3>;
	110	};
	111
fd5e5dd5 RJ	112	pcie0: pcie@20020000 {
	113	compatible = "brcm,iproc-pcie";
	114	reg = <0 0x20020000 0 0x1000>;
	115
	116	#interrupt-cells = <1>;
	117	interrupt-map-mask = <0 0 0 0>;
	118	interrupt-map = <0 0 0 0 &gic GIC_SPI 281 IRQ_TYPE_NONE>;
	119
	120	linux,pci-domain = <0>;
	121
	122	bus-range = <0x00 0xff>;
	123
	124	#address-cells = <3>;
	125	#size-cells = <2>;
	126	device_type = "pci";
	127	ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
	128
	129	brcm,pcie-ob;
	130	brcm,pcie-ob-oarr-size;
	131	brcm,pcie-ob-axi-offset = <0x00000000>;
	132	brcm,pcie-ob-window-size = <256>;
	133
	134	status = "disabled";
	135
	136	msi-parent = <&msi0>;
	137	msi0: msi@20020000 {
	138	compatible = "brcm,iproc-msi";
	139	msi-controller;
	140	interrupt-parent = <&gic>;
	141	interrupts = <GIC_SPI 277 IRQ_TYPE_NONE>,
	142	<GIC_SPI 278 IRQ_TYPE_NONE>,
	143	<GIC_SPI 279 IRQ_TYPE_NONE>,
	144	<GIC_SPI 280 IRQ_TYPE_NONE>;
	145	brcm,num-eq-region = <1>;
	146	brcm,num-msi-msg-region = <1>;
	147	};
	148	};
	149
	150	pcie4: pcie@50020000 {
	151	compatible = "brcm,iproc-pcie";
	152	reg = <0 0x50020000 0 0x1000>;
	153
	154	#interrupt-cells = <1>;
	155	interrupt-map-mask = <0 0 0 0>;
	156	interrupt-map = <0 0 0 0 &gic GIC_SPI 305 IRQ_TYPE_NONE>;
	157
	158	linux,pci-domain = <4>;
	159
	160	bus-range = <0x00 0xff>;
	161
	162	#address-cells = <3>;
	163	#size-cells = <2>;
	164	device_type = "pci";
	165	ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
	166
	167	brcm,pcie-ob;
	168	brcm,pcie-ob-oarr-size;
	169	brcm,pcie-ob-axi-offset = <0x30000000>;
	170	brcm,pcie-ob-window-size = <256>;
	171
	172	status = "disabled";
	173
	174	msi-parent = <&msi4>;
	175	msi4: msi@50020000 {
176	compatible = "brcm,iproc-msi";
177	msi-controller;
178	interrupt-parent = <&gic>;
179	interrupts = <GIC_SPI 301 IRQ_TYPE_NONE>,
180	<GIC_SPI 302 IRQ_TYPE_NONE>,
181	<GIC_SPI 303 IRQ_TYPE_NONE>,
182	<GIC_SPI 304 IRQ_TYPE_NONE>;
183	};
184	};
185
6aad8bf9 RJ	186	soc: soc {
	187	compatible = "simple-bus";
	188	#address-cells = <1>;
	189	#size-cells = <1>;
	190	ranges = <0 0 0 0xffffffff>;
	191
59a5bede AP	192	#include "ns2-clock.dtsi"
59a5bede AP	193
538fb37c AP	194	dma0: dma@61360000 {
	195	compatible = "arm,pl330", "arm,primecell";
	196	reg = <0x61360000 0x1000>;
	197	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	198	<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
	199	<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	200	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
	201	<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	202	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
	203	<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
	204	<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
	205	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
	206	#dma-cells = <1>;
	207	#dma-channels = <8>;
	208	#dma-requests = <32>;
	209	clocks = <&iprocslow>;
	210	clock-names = "apb_pclk";
	211	};
	212
6ec5f3c5 AP	213	smmu: mmu@64000000 {
	214	compatible = "arm,mmu-500";
	215	reg = <0x64000000 0x40000>;
	216	#global-interrupts = <2>;
	217	interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
	218	<GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
	219	<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
	220	<GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
	221	<GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
	222	<GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
	223	<GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
	224	<GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
	225	<GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
	226	<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
	227	<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
	228	<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
	229	<GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
	230	<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
	231	<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
	232	<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
	233	<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
	234	<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
	235	<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
	236	<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
	237	<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
	238	<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
	239	<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
	240	<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
	241	<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
	242	<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
	243	<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
	244	<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
	245	<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
	246	<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
	247	<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
	248	<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
	249	<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
	250	<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
	251	mmu-masters;
	252	};
	253
6aad8bf9 RJ	254	gic: interrupt-controller@65210000 {
	255	compatible = "arm,gic-400";
	256	#interrupt-cells = <3>;
	257	interrupt-controller;
	258	reg = <0x65210000 0x1000>,
	259	<0x65220000 0x1000>,
	260	<0x65240000 0x2000>,
	261	<0x65260000 0x1000>;
b2f9cd48 AP	262	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) \|
b2f9cd48 AP	263	IRQ_TYPE_LEVEL_HIGH)>;
6aad8bf9 RJ	264	};
6aad8bf9 RJ	265
e99df8fd AP	266	timer0: timer@66030000 {
	267	compatible = "arm,sp804", "arm,primecell";
	268	reg = <0x66030000 0x1000>;
	269	interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
	270	clocks = <&iprocslow>,
	271	<&iprocslow>,
	272	<&iprocslow>;
	273	clock-names = "timer1", "timer2", "apb_pclk";
	274	};
	275
	276	timer1: timer@66040000 {
	277	compatible = "arm,sp804", "arm,primecell";
	278	reg = <0x66040000 0x1000>;
	279	interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
	280	clocks = <&iprocslow>,
	281	<&iprocslow>,
	282	<&iprocslow>;
	283	clock-names = "timer1", "timer2", "apb_pclk";
	284	};
	285
	286	timer2: timer@66050000 {
	287	compatible = "arm,sp804", "arm,primecell";
	288	reg = <0x66050000 0x1000>;
	289	interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
	290	clocks = <&iprocslow>,
	291	<&iprocslow>,
	292	<&iprocslow>;
	293	clock-names = "timer1", "timer2", "apb_pclk";
	294	};
	295
	296	timer3: timer@66060000 {
	297	compatible = "arm,sp804", "arm,primecell";
	298	reg = <0x66060000 0x1000>;
	299	interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
	300	clocks = <&iprocslow>,
	301	<&iprocslow>,
	302	<&iprocslow>;
	303	clock-names = "timer1", "timer2", "apb_pclk";
	304	};
	305
7ac674e8 RJ	306	i2c0: i2c@66080000 {
	307	compatible = "brcm,iproc-i2c";
	308	reg = <0x66080000 0x100>;
	309	#address-cells = <1>;
	310	#size-cells = <0>;
	311	interrupts = <GIC_SPI 394 IRQ_TYPE_NONE>;
	312	clock-frequency = <100000>;
	313	status = "disabled";
	314	};
	315
6e79e7cf AP	316	wdt0: watchdog@66090000 {
	317	compatible = "arm,sp805", "arm,primecell";
	318	reg = <0x66090000 0x1000>;
	319	interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
	320	clocks = <&iprocslow>, <&iprocslow>;
	321	clock-names = "wdogclk", "apb_pclk";
	322	};
	323
7ac674e8 RJ	324	i2c1: i2c@660b0000 {
	325	compatible = "brcm,iproc-i2c";
	326	reg = <0x660b0000 0x100>;
	327	#address-cells = <1>;
	328	#size-cells = <0>;
	329	interrupts = <GIC_SPI 395 IRQ_TYPE_NONE>;
	330	clock-frequency = <100000>;
	331	status = "disabled";
	332	};
	333
6aad8bf9 RJ	334	uart3: serial@66130000 {
	335	compatible = "snps,dw-apb-uart";
	336	reg = <0x66130000 0x100>;
	337	interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
	338	reg-shift = <2>;
	339	reg-io-width = <4>;
d8bd64c1	340	clocks = <&osc>;
6aad8bf9 RJ	341	status = "disabled";
6aad8bf9 RJ	342	};
e8a6e265	343
d69dbd9f AP	344	ssp0: ssp@66180000 {
	345	compatible = "arm,pl022", "arm,primecell";
	346	reg = <0x66180000 0x1000>;
	347	interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
	348	clocks = <&iprocslow>, <&iprocslow>;
	349	clock-names = "spiclk", "apb_pclk";
	350	#address-cells = <1>;
	351	#size-cells = <0>;
	352	status = "disabled";
	353	};
	354
	355	ssp1: ssp@66190000 {
	356	compatible = "arm,pl022", "arm,primecell";
	357	reg = <0x66190000 0x1000>;
	358	interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
	359	clocks = <&iprocslow>, <&iprocslow>;
	360	clock-names = "spiclk", "apb_pclk";
	361	#address-cells = <1>;
	362	#size-cells = <0>;
	363	status = "disabled";
	364	};
	365
e8a6e265 AP	366	hwrng: hwrng@66220000 {
	367	compatible = "brcm,iproc-rng200";
	368	reg = <0x66220000 0x28>;
	369	};
c6fe9a2e	370
efc87767 AP	371	sdio0: sdhci@66420000 {
	372	compatible = "brcm,sdhci-iproc-cygnus";
	373	reg = <0x66420000 0x100>;
	374	interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
	375	bus-width = <8>;
	376	clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
	377	status = "disabled";
	378	};
	379
	380	sdio1: sdhci@66430000 {
	381	compatible = "brcm,sdhci-iproc-cygnus";
	382	reg = <0x66430000 0x100>;
	383	interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
	384	bus-width = <8>;
	385	clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
	386	status = "disabled";
	387	};
	388
c6fe9a2e AP	389	nand: nand@66460000 {
	390	compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
	391	reg = <0x66460000 0x600>,
	392	<0x67015408 0x600>,
	393	<0x66460f00 0x20>;
	394	reg-names = "nand", "iproc-idm", "iproc-ext";
	395	interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
	396
	397	#address-cells = <1>;
	398	#size-cells = <0>;
	399
	400	brcm,nand-has-wp;
	401	};
6aad8bf9 RJ	402	};
6aad8bf9 RJ	403	};