[mirror_ubuntu-eoan-kernel.git] / arch / arm64 / boot / dts / broadcom / ns2.dtsi

/*
 *  BSD LICENSE
 *
 *  Copyright (c) 2015 Broadcom.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/bcm-ns2.h>

/ {
	compatible = "brcm,ns2";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		A57_0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0 0>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER0_L2>;
		};

		A57_1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0 1>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER0_L2>;
		};

		A57_2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0 2>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER0_L2>;
		};

		A57_3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0 3>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER0_L2>;
		};

		CLUSTER0_L2: l2-cache@000 {
			compatible = "cache";
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) |
			      IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) |
			      IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) |
			      IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) |
			      IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&A57_0>,
				     <&A57_1>,
				     <&A57_2>,
				     <&A57_3>;
	};

	pcie0: pcie@20020000 {
		compatible = "brcm,iproc-pcie";
		reg = <0 0x20020000 0 0x1000>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &gic GIC_SPI 281 IRQ_TYPE_NONE>;

		linux,pci-domain = <0>;

		bus-range = <0x00 0xff>;

		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;

		brcm,pcie-ob;
		brcm,pcie-ob-oarr-size;
		brcm,pcie-ob-axi-offset = <0x00000000>;
		brcm,pcie-ob-window-size = <256>;

		status = "disabled";

		msi-parent = <&msi0>;
		msi0: msi@20020000 {
			compatible = "brcm,iproc-msi";
			msi-controller;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 277 IRQ_TYPE_NONE>,
				     <GIC_SPI 278 IRQ_TYPE_NONE>,
				     <GIC_SPI 279 IRQ_TYPE_NONE>,
				     <GIC_SPI 280 IRQ_TYPE_NONE>;
			brcm,num-eq-region = <1>;
			brcm,num-msi-msg-region = <1>;
		};
	};

	pcie4: pcie@50020000 {
		compatible = "brcm,iproc-pcie";
		reg = <0 0x50020000 0 0x1000>;

		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0>;
		interrupt-map = <0 0 0 0 &gic GIC_SPI 305 IRQ_TYPE_NONE>;

		linux,pci-domain = <4>;

		bus-range = <0x00 0xff>;

		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;

		brcm,pcie-ob;
		brcm,pcie-ob-oarr-size;
		brcm,pcie-ob-axi-offset = <0x30000000>;
		brcm,pcie-ob-window-size = <256>;

		status = "disabled";

		msi-parent = <&msi4>;
		msi4: msi@50020000 {
			compatible = "brcm,iproc-msi";
			msi-controller;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 301 IRQ_TYPE_NONE>,
				     <GIC_SPI 302 IRQ_TYPE_NONE>,
				     <GIC_SPI 303 IRQ_TYPE_NONE>,
				     <GIC_SPI 304 IRQ_TYPE_NONE>;
		};
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;

		#include "ns2-clock.dtsi"

		pdc0: iproc-pdc0@612c0000 {
			compatible = "brcm,iproc-pdc-mbox";
			reg = <0x612c0000 0x445>;  /* PDC FS0 regs */
			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
			#mbox-cells = <1>;
			brcm,rx-status-len = <32>;
			brcm,use-bcm-hdr;
		};

		pdc1: iproc-pdc1@612e0000 {
			compatible = "brcm,iproc-pdc-mbox";
			reg = <0x612e0000 0x445>;  /* PDC FS1 regs */
			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
			#mbox-cells = <1>;
			brcm,rx-status-len = <32>;
			brcm,use-bcm-hdr;
		};

		pdc2: iproc-pdc2@61300000 {
			compatible = "brcm,iproc-pdc-mbox";
			reg = <0x61300000 0x445>;  /* PDC FS2 regs */
			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
			#mbox-cells = <1>;
			brcm,rx-status-len = <32>;
			brcm,use-bcm-hdr;
		};

		pdc3: iproc-pdc3@61320000 {
			compatible = "brcm,iproc-pdc-mbox";
			reg = <0x61320000 0x445>;  /* PDC FS3 regs */
			interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
			#mbox-cells = <1>;
			brcm,rx-status-len = <32>;
			brcm,use-bcm-hdr;
		};

		dma0: dma@61360000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x61360000 0x1000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			#dma-channels = <8>;
			#dma-requests = <32>;
			clocks = <&iprocslow>;
			clock-names = "apb_pclk";
		};

		smmu: mmu@64000000 {
			compatible = "arm,mmu-500";
			reg = <0x64000000 0x40000>;
			#global-interrupts = <2>;
			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
			#iommu-cells = <1>;
		};

		pinctrl: pinctrl@6501d130 {
			compatible = "brcm,ns2-pinmux";
			reg = <0x6501d130 0x08>,
			      <0x660a0028 0x04>,
			      <0x660009b0 0x40>;
		};

		gpio_aon: gpio@65024800 {
			compatible = "brcm,iproc-gpio";
			reg = <0x65024800 0x50>,
			      <0x65024008 0x18>;
			ngpios = <6>;
			#gpio-cells = <2>;
			gpio-controller;
		};

		gic: interrupt-controller@65210000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x65210000 0x1000>,
			      <0x65220000 0x1000>,
			      <0x65240000 0x2000>,
			      <0x65260000 0x1000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
				      IRQ_TYPE_LEVEL_HIGH)>;
		};

		cci@65590000 {
			compatible = "arm,cci-400";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x65590000 0x1000>;
			ranges = <0 0x65590000 0x10000>;

			pmu@9000 {
				compatible = "arm,cci-400-pmu,r1",
					     "arm,cci-400-pmu";
				reg = <0x9000 0x4000>;
				interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		pwm: pwm@66010000 {
			compatible = "brcm,iproc-pwm";
			reg = <0x66010000 0x28>;
			clocks = <&osc>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		mdio_mux_iproc: mdio-mux@6602023c {
			compatible = "brcm,mdio-mux-iproc";
			reg = <0x6602023c 0x14>;
			#address-cells = <1>;
			#size-cells = <0>;

			mdio@0 {
				reg = <0x0>;
				#address-cells = <1>;
				#size-cells = <0>;

				pci_phy0: pci-phy@0 {
					compatible = "brcm,ns2-pcie-phy";
					reg = <0x0>;
					#phy-cells = <0>;
					status = "disabled";
				};
			};

			mdio@7 {
				reg = <0x7>;
				#address-cells = <1>;
				#size-cells = <0>;

				pci_phy1: pci-phy@0 {
					compatible = "brcm,ns2-pcie-phy";
					reg = <0x0>;
					#phy-cells = <0>;
					status = "disabled";
				};
			};

			mdio@10 {
				reg = <0x10>;
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		timer0: timer@66030000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x66030000 0x1000>;
			interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&iprocslow>,
				 <&iprocslow>,
				 <&iprocslow>;
			clock-names = "timer1", "timer2", "apb_pclk";
		};

		timer1: timer@66040000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x66040000 0x1000>;
			interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&iprocslow>,
				 <&iprocslow>,
				 <&iprocslow>;
			clock-names = "timer1", "timer2", "apb_pclk";
		};

		timer2: timer@66050000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x66050000 0x1000>;
			interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&iprocslow>,
				 <&iprocslow>,
				 <&iprocslow>;
			clock-names = "timer1", "timer2", "apb_pclk";
		};

		timer3: timer@66060000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x66060000 0x1000>;
			interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&iprocslow>,
				 <&iprocslow>,
				 <&iprocslow>;
			clock-names = "timer1", "timer2", "apb_pclk";
		};

		i2c0: i2c@66080000 {
			compatible = "brcm,iproc-i2c";
			reg = <0x66080000 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 394 IRQ_TYPE_NONE>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		wdt0: watchdog@66090000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x66090000 0x1000>;
			interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&iprocslow>, <&iprocslow>;
			clock-names = "wdogclk", "apb_pclk";
		};

		gpio_g: gpio@660a0000 {
			compatible = "brcm,iproc-gpio";
			reg = <0x660a0000 0x50>;
			ngpios = <32>;
			#gpio-cells = <2>;
			gpio-controller;
			interrupt-controller;
			interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
		};

		i2c1: i2c@660b0000 {
			compatible = "brcm,iproc-i2c";
			reg = <0x660b0000 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 395 IRQ_TYPE_NONE>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		uart0: serial@66100000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x66100000 0x100>;
			interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&iprocslow>;
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		uart1: serial@66110000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x66110000 0x100>;
			interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&iprocslow>;
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		uart2: serial@66120000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x66120000 0x100>;
			interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&iprocslow>;
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		uart3: serial@66130000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x66130000 0x100>;
			interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&osc>;
			status = "disabled";
		};

		ssp0: ssp@66180000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x66180000 0x1000>;
			interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&iprocslow>, <&iprocslow>;
			clock-names = "spiclk", "apb_pclk";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		ssp1: ssp@66190000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x66190000 0x1000>;
			interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&iprocslow>, <&iprocslow>;
			clock-names = "spiclk", "apb_pclk";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		hwrng: hwrng@66220000 {
			compatible = "brcm,iproc-rng200";
			reg = <0x66220000 0x28>;
		};

		sata_phy: sata_phy@663f0100 {
			compatible = "brcm,iproc-ns2-sata-phy";
			reg = <0x663f0100 0x1f00>,
			      <0x663f004c 0x10>;
			reg-names = "phy", "phy-ctrl";
			#address-cells = <1>;
			#size-cells = <0>;

			sata_phy0: sata-phy@0 {
				reg = <0>;
				#phy-cells = <0>;
				status = "disabled";
			};

			sata_phy1: sata-phy@1 {
				reg = <1>;
				#phy-cells = <0>;
				status = "disabled";
			};
		};

		sata: ahci@663f2000 {
			compatible = "brcm,iproc-ahci", "generic-ahci";
			reg = <0x663f2000 0x1000>;
			reg-names = "ahci";
			interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			sata0: sata-port@0 {
				reg = <0>;
				phys = <&sata_phy0>;
				phy-names = "sata-phy";
			};

			sata1: sata-port@1 {
				reg = <1>;
				phys = <&sata_phy1>;
				phy-names = "sata-phy";
			};
		};

		sdio0: sdhci@66420000 {
			compatible = "brcm,sdhci-iproc-cygnus";
			reg = <0x66420000 0x100>;
			interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
			bus-width = <8>;
			clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
			status = "disabled";
		};

		sdio1: sdhci@66430000 {
			compatible = "brcm,sdhci-iproc-cygnus";
			reg = <0x66430000 0x100>;
			interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
			bus-width = <8>;
			clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
			status = "disabled";
		};

		nand: nand@66460000 {
			compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
			reg = <0x66460000 0x600>,
			      <0x67015408 0x600>,
			      <0x66460f00 0x20>;
			reg-names = "nand", "iproc-idm", "iproc-ext";
			interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;
			#size-cells = <0>;

			brcm,nand-has-wp;
		};

		qspi: spi@66470200 {
			compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi";
			reg = <0x66470200 0x184>,
				<0x66470000 0x124>,
				<0x67017408 0x004>,
				<0x664703a0 0x01c>;
			reg-names = "mspi", "bspi", "intr_regs",
				"intr_status_reg";
			interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "spi_l1_intr";
			clocks = <&iprocmed>;
			clock-names = "iprocmed";
			num-cs = <2>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

	};
};
Commit	Line	Data
6aad8bf9 RJ	1	/*
	2	* BSD LICENSE
	3	*
59a5bede	4	* Copyright (c) 2015 Broadcom. All rights reserved.
6aad8bf9 RJ	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions
	8	* are met:
	9	*
	10	* * Redistributions of source code must retain the above copyright
	11	* notice, this list of conditions and the following disclaimer.
	12	* * Redistributions in binary form must reproduce the above copyright
	13	* notice, this list of conditions and the following disclaimer in
	14	* the documentation and/or other materials provided with the
	15	* distribution.
	16	* * Neither the name of Broadcom Corporation nor the names of its
	17	* contributors may be used to endorse or promote products derived
	18	* from this software without specific prior written permission.
	19	*
	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	21	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	22	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	23	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	24	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	25	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	26	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	27	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	28	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	29	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	30	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	31	*/
	32
	33	#include <dt-bindings/interrupt-controller/arm-gic.h>
d8bd64c1	34	#include <dt-bindings/clock/bcm-ns2.h>
6aad8bf9	35
6aad8bf9 RJ	36	/ {
	37	compatible = "brcm,ns2";
	38	interrupt-parent = <&gic>;
	39	#address-cells = <2>;
	40	#size-cells = <2>;
	41
	42	cpus {
	43	#address-cells = <2>;
	44	#size-cells = <0>;
	45
5b31d875	46	A57_0: cpu@0 {
6aad8bf9 RJ	47	device_type = "cpu";
	48	compatible = "arm,cortex-a57", "arm,armv8";
	49	reg = <0 0>;
a9abb475	50	enable-method = "psci";
33a93aa4	51	next-level-cache = <&CLUSTER0_L2>;
6aad8bf9 RJ	52	};
6aad8bf9 RJ	53
5b31d875	54	A57_1: cpu@1 {
6aad8bf9 RJ	55	device_type = "cpu";
	56	compatible = "arm,cortex-a57", "arm,armv8";
	57	reg = <0 1>;
a9abb475	58	enable-method = "psci";
33a93aa4	59	next-level-cache = <&CLUSTER0_L2>;
6aad8bf9 RJ	60	};
6aad8bf9 RJ	61
5b31d875	62	A57_2: cpu@2 {
6aad8bf9 RJ	63	device_type = "cpu";
	64	compatible = "arm,cortex-a57", "arm,armv8";
	65	reg = <0 2>;
a9abb475	66	enable-method = "psci";
33a93aa4	67	next-level-cache = <&CLUSTER0_L2>;
6aad8bf9 RJ	68	};
6aad8bf9 RJ	69
5b31d875	70	A57_3: cpu@3 {
6aad8bf9 RJ	71	device_type = "cpu";
	72	compatible = "arm,cortex-a57", "arm,armv8";
	73	reg = <0 3>;
a9abb475	74	enable-method = "psci";
33a93aa4 AP	75	next-level-cache = <&CLUSTER0_L2>;
	76	};
	77
	78	CLUSTER0_L2: l2-cache@000 {
	79	compatible = "cache";
6aad8bf9 RJ	80	};
	81	};
	82
a9abb475 LS	83	psci {
	84	compatible = "arm,psci-1.0";
	85	method = "smc";
	86	};
	87
6aad8bf9 RJ	88	timer {
	89	compatible = "arm,armv8-timer";
	90	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xff) \|
f2a89d3b	91	IRQ_TYPE_LEVEL_LOW)>,
6aad8bf9	92	<GIC_PPI 14 (GIC_CPU_MASK_RAW(0xff) \|
f2a89d3b	93	IRQ_TYPE_LEVEL_LOW)>,
6aad8bf9	94	<GIC_PPI 11 (GIC_CPU_MASK_RAW(0xff) \|
f2a89d3b	95	IRQ_TYPE_LEVEL_LOW)>,
6aad8bf9	96	<GIC_PPI 10 (GIC_CPU_MASK_RAW(0xff) \|
f2a89d3b	97	IRQ_TYPE_LEVEL_LOW)>;
6aad8bf9 RJ	98	};
6aad8bf9 RJ	99
5b31d875 AP	100	pmu {
	101	compatible = "arm,armv8-pmuv3";
	102	interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
	103	<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
	104	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
	105	<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
	106	interrupt-affinity = <&A57_0>,
	107	<&A57_1>,
	108	<&A57_2>,
	109	<&A57_3>;
	110	};
	111
fd5e5dd5 RJ	112	pcie0: pcie@20020000 {
	113	compatible = "brcm,iproc-pcie";
	114	reg = <0 0x20020000 0 0x1000>;
	115
	116	#interrupt-cells = <1>;
	117	interrupt-map-mask = <0 0 0 0>;
	118	interrupt-map = <0 0 0 0 &gic GIC_SPI 281 IRQ_TYPE_NONE>;
	119
	120	linux,pci-domain = <0>;
	121
	122	bus-range = <0x00 0xff>;
	123
	124	#address-cells = <3>;
	125	#size-cells = <2>;
	126	device_type = "pci";
	127	ranges = <0x83000000 0 0x00000000 0 0x00000000 0 0x20000000>;
	128
	129	brcm,pcie-ob;
	130	brcm,pcie-ob-oarr-size;
	131	brcm,pcie-ob-axi-offset = <0x00000000>;
	132	brcm,pcie-ob-window-size = <256>;
	133
	134	status = "disabled";
	135
	136	msi-parent = <&msi0>;
	137	msi0: msi@20020000 {
	138	compatible = "brcm,iproc-msi";
	139	msi-controller;
	140	interrupt-parent = <&gic>;
	141	interrupts = <GIC_SPI 277 IRQ_TYPE_NONE>,
	142	<GIC_SPI 278 IRQ_TYPE_NONE>,
	143	<GIC_SPI 279 IRQ_TYPE_NONE>,
	144	<GIC_SPI 280 IRQ_TYPE_NONE>;
	145	brcm,num-eq-region = <1>;
	146	brcm,num-msi-msg-region = <1>;
	147	};
	148	};
	149
	150	pcie4: pcie@50020000 {
	151	compatible = "brcm,iproc-pcie";
	152	reg = <0 0x50020000 0 0x1000>;
	153
	154	#interrupt-cells = <1>;
	155	interrupt-map-mask = <0 0 0 0>;
	156	interrupt-map = <0 0 0 0 &gic GIC_SPI 305 IRQ_TYPE_NONE>;
	157
	158	linux,pci-domain = <4>;
	159
	160	bus-range = <0x00 0xff>;
	161
	162	#address-cells = <3>;
	163	#size-cells = <2>;
	164	device_type = "pci";
	165	ranges = <0x83000000 0 0x00000000 0 0x30000000 0 0x20000000>;
	166
	167	brcm,pcie-ob;
	168	brcm,pcie-ob-oarr-size;
	169	brcm,pcie-ob-axi-offset = <0x30000000>;
	170	brcm,pcie-ob-window-size = <256>;
	171
	172	status = "disabled";
	173
	174	msi-parent = <&msi4>;
	175	msi4: msi@50020000 {
176	compatible = "brcm,iproc-msi";
177	msi-controller;
178	interrupt-parent = <&gic>;
179	interrupts = <GIC_SPI 301 IRQ_TYPE_NONE>,
180	<GIC_SPI 302 IRQ_TYPE_NONE>,
181	<GIC_SPI 303 IRQ_TYPE_NONE>,
182	<GIC_SPI 304 IRQ_TYPE_NONE>;
183	};
184	};
185
6aad8bf9 RJ	186	soc: soc {
	187	compatible = "simple-bus";
	188	#address-cells = <1>;
	189	#size-cells = <1>;
	190	ranges = <0 0 0 0xffffffff>;
	191
59a5bede AP	192	#include "ns2-clock.dtsi"
59a5bede AP	193
e7924914 RR	194	pdc0: iproc-pdc0@612c0000 {
	195	compatible = "brcm,iproc-pdc-mbox";
	196	reg = <0x612c0000 0x445>; /* PDC FS0 regs */
	197	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
	198	#mbox-cells = <1>;
	199	brcm,rx-status-len = <32>;
	200	brcm,use-bcm-hdr;
	201	};
	202
	203	pdc1: iproc-pdc1@612e0000 {
	204	compatible = "brcm,iproc-pdc-mbox";
	205	reg = <0x612e0000 0x445>; /* PDC FS1 regs */
	206	interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
	207	#mbox-cells = <1>;
	208	brcm,rx-status-len = <32>;
	209	brcm,use-bcm-hdr;
	210	};
	211
	212	pdc2: iproc-pdc2@61300000 {
	213	compatible = "brcm,iproc-pdc-mbox";
	214	reg = <0x61300000 0x445>; /* PDC FS2 regs */
	215	interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
	216	#mbox-cells = <1>;
	217	brcm,rx-status-len = <32>;
	218	brcm,use-bcm-hdr;
	219	};
	220
	221	pdc3: iproc-pdc3@61320000 {
	222	compatible = "brcm,iproc-pdc-mbox";
	223	reg = <0x61320000 0x445>; /* PDC FS3 regs */
	224	interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
	225	#mbox-cells = <1>;
	226	brcm,rx-status-len = <32>;
	227	brcm,use-bcm-hdr;
	228	};
	229
538fb37c AP	230	dma0: dma@61360000 {
	231	compatible = "arm,pl330", "arm,primecell";
	232	reg = <0x61360000 0x1000>;
	233	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
	234	<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
	235	<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
	236	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
	237	<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	238	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
	239	<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
	240	<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
	241	<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
	242	#dma-cells = <1>;
	243	#dma-channels = <8>;
	244	#dma-requests = <32>;
	245	clocks = <&iprocslow>;
	246	clock-names = "apb_pclk";
	247	};
	248
6ec5f3c5 AP	249	smmu: mmu@64000000 {
	250	compatible = "arm,mmu-500";
	251	reg = <0x64000000 0x40000>;
	252	#global-interrupts = <2>;
	253	interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
	254	<GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
	255	<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
	256	<GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
	257	<GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
	258	<GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>,
	259	<GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>,
	260	<GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>,
	261	<GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
	262	<GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
	263	<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
	264	<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
	265	<GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
	266	<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
	267	<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
	268	<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
	269	<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
	270	<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
	271	<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
	272	<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
	273	<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
	274	<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
	275	<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
	276	<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
	277	<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
	278	<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
	279	<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
	280	<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
	281	<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
	282	<GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
	283	<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
	284	<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
	285	<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
	286	<GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
62b69232	287	#iommu-cells = <1>;
6ec5f3c5 AP	288	};
6ec5f3c5 AP	289
97b1504a YRDR	290	pinctrl: pinctrl@6501d130 {
	291	compatible = "brcm,ns2-pinmux";
	292	reg = <0x6501d130 0x08>,
	293	<0x660a0028 0x04>,
	294	<0x660009b0 0x40>;
	295	};
	296
5f2fb241 YRDR	297	gpio_aon: gpio@65024800 {
	298	compatible = "brcm,iproc-gpio";
	299	reg = <0x65024800 0x50>,
	300	<0x65024008 0x18>;
	301	ngpios = <6>;
	302	#gpio-cells = <2>;
	303	gpio-controller;
	304	};
	305
6aad8bf9 RJ	306	gic: interrupt-controller@65210000 {
	307	compatible = "arm,gic-400";
	308	#interrupt-cells = <3>;
	309	interrupt-controller;
	310	reg = <0x65210000 0x1000>,
	311	<0x65220000 0x1000>,
	312	<0x65240000 0x2000>,
	313	<0x65260000 0x1000>;
b2f9cd48 AP	314	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) \|
b2f9cd48 AP	315	IRQ_TYPE_LEVEL_HIGH)>;
6aad8bf9 RJ	316	};
6aad8bf9 RJ	317
5dcc9c76 JM	318	cci@65590000 {
	319	compatible = "arm,cci-400";
	320	#address-cells = <1>;
	321	#size-cells = <1>;
	322	reg = <0x65590000 0x1000>;
	323	ranges = <0 0x65590000 0x10000>;
	324
	325	pmu@9000 {
	326	compatible = "arm,cci-400-pmu,r1",
	327	"arm,cci-400-pmu";
	328	reg = <0x9000 0x4000>;
	329	interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
	330	<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
	331	<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
	332	<GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
	333	<GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
	334	<GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
	335	};
	336	};
	337
5072ed1f YRDR	338	pwm: pwm@66010000 {
	339	compatible = "brcm,iproc-pwm";
	340	reg = <0x66010000 0x28>;
	341	clocks = <&osc>;
	342	#pwm-cells = <3>;
	343	status = "disabled";
	344	};
	345
5f1a067b PK	346	mdio_mux_iproc: mdio-mux@6602023c {
	347	compatible = "brcm,mdio-mux-iproc";
	348	reg = <0x6602023c 0x14>;
	349	#address-cells = <1>;
	350	#size-cells = <0>;
	351
	352	mdio@0 {
	353	reg = <0x0>;
	354	#address-cells = <1>;
	355	#size-cells = <0>;
	356
	357	pci_phy0: pci-phy@0 {
	358	compatible = "brcm,ns2-pcie-phy";
	359	reg = <0x0>;
	360	#phy-cells = <0>;
	361	status = "disabled";
	362	};
	363	};
	364
	365	mdio@7 {
	366	reg = <0x7>;
	367	#address-cells = <1>;
	368	#size-cells = <0>;
	369
	370	pci_phy1: pci-phy@0 {
	371	compatible = "brcm,ns2-pcie-phy";
	372	reg = <0x0>;
	373	#phy-cells = <0>;
	374	status = "disabled";
	375	};
	376	};
	377
	378	mdio@10 {
	379	reg = <0x10>;
	380	#address-cells = <1>;
	381	#size-cells = <0>;
	382	};
	383	};
	384
e99df8fd AP	385	timer0: timer@66030000 {
	386	compatible = "arm,sp804", "arm,primecell";
	387	reg = <0x66030000 0x1000>;
	388	interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
	389	clocks = <&iprocslow>,
	390	<&iprocslow>,
	391	<&iprocslow>;
	392	clock-names = "timer1", "timer2", "apb_pclk";
	393	};
	394
	395	timer1: timer@66040000 {
	396	compatible = "arm,sp804", "arm,primecell";
	397	reg = <0x66040000 0x1000>;
	398	interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
	399	clocks = <&iprocslow>,
	400	<&iprocslow>,
	401	<&iprocslow>;
	402	clock-names = "timer1", "timer2", "apb_pclk";
	403	};
	404
	405	timer2: timer@66050000 {
	406	compatible = "arm,sp804", "arm,primecell";
	407	reg = <0x66050000 0x1000>;
	408	interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
	409	clocks = <&iprocslow>,
	410	<&iprocslow>,
	411	<&iprocslow>;
	412	clock-names = "timer1", "timer2", "apb_pclk";
	413	};
	414
	415	timer3: timer@66060000 {
	416	compatible = "arm,sp804", "arm,primecell";
	417	reg = <0x66060000 0x1000>;
	418	interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
	419	clocks = <&iprocslow>,
	420	<&iprocslow>,
	421	<&iprocslow>;
	422	clock-names = "timer1", "timer2", "apb_pclk";
	423	};
	424
7ac674e8 RJ	425	i2c0: i2c@66080000 {
	426	compatible = "brcm,iproc-i2c";
	427	reg = <0x66080000 0x100>;
	428	#address-cells = <1>;
	429	#size-cells = <0>;
	430	interrupts = <GIC_SPI 394 IRQ_TYPE_NONE>;
	431	clock-frequency = <100000>;
	432	status = "disabled";
	433	};
	434
6e79e7cf AP	435	wdt0: watchdog@66090000 {
	436	compatible = "arm,sp805", "arm,primecell";
	437	reg = <0x66090000 0x1000>;
	438	interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
	439	clocks = <&iprocslow>, <&iprocslow>;
	440	clock-names = "wdogclk", "apb_pclk";
	441	};
	442
5f2fb241 YRDR	443	gpio_g: gpio@660a0000 {
	444	compatible = "brcm,iproc-gpio";
	445	reg = <0x660a0000 0x50>;
	446	ngpios = <32>;
	447	#gpio-cells = <2>;
	448	gpio-controller;
	449	interrupt-controller;
	450	interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
	451	};
	452
7ac674e8 RJ	453	i2c1: i2c@660b0000 {
	454	compatible = "brcm,iproc-i2c";
	455	reg = <0x660b0000 0x100>;
	456	#address-cells = <1>;
	457	#size-cells = <0>;
	458	interrupts = <GIC_SPI 395 IRQ_TYPE_NONE>;
	459	clock-frequency = <100000>;
	460	status = "disabled";
	461	};
	462
1e0fdee8 JM	463	uart0: serial@66100000 {
	464	compatible = "snps,dw-apb-uart";
	465	reg = <0x66100000 0x100>;
	466	interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>;
	467	clocks = <&iprocslow>;
	468	reg-shift = <2>;
	469	reg-io-width = <4>;
	470	status = "disabled";
	471	};
	472
	473	uart1: serial@66110000 {
	474	compatible = "snps,dw-apb-uart";
	475	reg = <0x66110000 0x100>;
	476	interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
	477	clocks = <&iprocslow>;
	478	reg-shift = <2>;
	479	reg-io-width = <4>;
	480	status = "disabled";
	481	};
	482
	483	uart2: serial@66120000 {
	484	compatible = "snps,dw-apb-uart";
	485	reg = <0x66120000 0x100>;
	486	interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
	487	clocks = <&iprocslow>;
	488	reg-shift = <2>;
	489	reg-io-width = <4>;
	490	status = "disabled";
	491	};
	492
6aad8bf9 RJ	493	uart3: serial@66130000 {
	494	compatible = "snps,dw-apb-uart";
	495	reg = <0x66130000 0x100>;
	496	interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
	497	reg-shift = <2>;
	498	reg-io-width = <4>;
d8bd64c1	499	clocks = <&osc>;
6aad8bf9 RJ	500	status = "disabled";
6aad8bf9 RJ	501	};
e8a6e265	502
d69dbd9f AP	503	ssp0: ssp@66180000 {
	504	compatible = "arm,pl022", "arm,primecell";
	505	reg = <0x66180000 0x1000>;
	506	interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
	507	clocks = <&iprocslow>, <&iprocslow>;
	508	clock-names = "spiclk", "apb_pclk";
	509	#address-cells = <1>;
	510	#size-cells = <0>;
	511	status = "disabled";
	512	};
	513
	514	ssp1: ssp@66190000 {
	515	compatible = "arm,pl022", "arm,primecell";
	516	reg = <0x66190000 0x1000>;
	517	interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
	518	clocks = <&iprocslow>, <&iprocslow>;
	519	clock-names = "spiclk", "apb_pclk";
	520	#address-cells = <1>;
	521	#size-cells = <0>;
	522	status = "disabled";
	523	};
	524
e8a6e265 AP	525	hwrng: hwrng@66220000 {
	526	compatible = "brcm,iproc-rng200";
	527	reg = <0x66220000 0x28>;
	528	};
c6fe9a2e	529
ac9aae00 AP	530	sata_phy: sata_phy@663f0100 {
	531	compatible = "brcm,iproc-ns2-sata-phy";
	532	reg = <0x663f0100 0x1f00>,
	533	<0x663f004c 0x10>;
	534	reg-names = "phy", "phy-ctrl";
	535	#address-cells = <1>;
	536	#size-cells = <0>;
	537
	538	sata_phy0: sata-phy@0 {
	539	reg = <0>;
	540	#phy-cells = <0>;
	541	status = "disabled";
	542	};
	543
	544	sata_phy1: sata-phy@1 {
	545	reg = <1>;
	546	#phy-cells = <0>;
	547	status = "disabled";
	548	};
	549	};
	550
	551	sata: ahci@663f2000 {
	552	compatible = "brcm,iproc-ahci", "generic-ahci";
	553	reg = <0x663f2000 0x1000>;
	554	reg-names = "ahci";
	555	interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
	556	#address-cells = <1>;
	557	#size-cells = <0>;
	558	status = "disabled";
	559
	560	sata0: sata-port@0 {
	561	reg = <0>;
	562	phys = <&sata_phy0>;
	563	phy-names = "sata-phy";
	564	};
	565
	566	sata1: sata-port@1 {
	567	reg = <1>;
	568	phys = <&sata_phy1>;
	569	phy-names = "sata-phy";
	570	};
	571	};
	572
efc87767 AP	573	sdio0: sdhci@66420000 {
	574	compatible = "brcm,sdhci-iproc-cygnus";
	575	reg = <0x66420000 0x100>;
	576	interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
	577	bus-width = <8>;
	578	clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
	579	status = "disabled";
	580	};
	581
	582	sdio1: sdhci@66430000 {
	583	compatible = "brcm,sdhci-iproc-cygnus";
	584	reg = <0x66430000 0x100>;
	585	interrupts = <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
	586	bus-width = <8>;
	587	clocks = <&genpll_sw BCM_NS2_GENPLL_SW_SDIO_CLK>;
	588	status = "disabled";
	589	};
	590
c6fe9a2e AP	591	nand: nand@66460000 {
	592	compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
	593	reg = <0x66460000 0x600>,
	594	<0x67015408 0x600>,
	595	<0x66460f00 0x20>;
	596	reg-names = "nand", "iproc-idm", "iproc-ext";
	597	interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
	598
	599	#address-cells = <1>;
	600	#size-cells = <0>;
	601
	602	brcm,nand-has-wp;
	603	};
ff73917d KD	604
	605	qspi: spi@66470200 {
	606	compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi";
	607	reg = <0x66470200 0x184>,
	608	<0x66470000 0x124>,
	609	<0x67017408 0x004>,
	610	<0x664703a0 0x01c>;
	611	reg-names = "mspi", "bspi", "intr_regs",
	612	"intr_status_reg";
	613	interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
	614	interrupt-names = "spi_l1_intr";
	615	clocks = <&iprocmed>;
	616	clock-names = "iprocmed";
	617	num-cs = <2>;
	618	#address-cells = <1>;
	619	#size-cells = <0>;
	620	};
	621
6aad8bf9 RJ	622	};
6aad8bf9 RJ	623	};