[mirror_ubuntu-focal-kernel.git] / arch / arm64 / boot / dts / broadcom / stingray / stingray.dtsi

/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2015-2017 Broadcom.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "brcm,stingray";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu@000 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER0_L2>;
		};

		cpu@001 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0 0x1>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER0_L2>;
		};

		cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0 0x100>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER1_L2>;
		};

		cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0 0x101>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER1_L2>;
		};

		cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0 0x200>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER2_L2>;
		};

		cpu@201 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0 0x201>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER2_L2>;
		};

		cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0 0x300>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER3_L2>;
		};

		cpu@301 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0 0x301>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER3_L2>;
		};

		CLUSTER0_L2: l2-cache@000 {
			compatible = "cache";
		};

		CLUSTER1_L2: l2-cache@100 {
			compatible = "cache";
		};

		CLUSTER2_L2: l2-cache@200 {
			compatible = "cache";
		};

		CLUSTER3_L2: l2-cache@300 {
			compatible = "cache";
		};
	};

	memory: memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0 0x40000000>;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	scr {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x61000000 0x05000000>;

		ccn: ccn@00000000 {
			compatible = "arm,ccn-502";
			reg = <0x00000000 0x900000>;
			interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
		};

		gic: interrupt-controller@02c00000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <3>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			interrupt-controller;
			reg = <0x02c00000 0x010000>, /* GICD */
			      <0x02e00000 0x600000>; /* GICR */
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

			gic_its: gic-its@63c20000 {
				compatible = "arm,gic-v3-its";
				msi-controller;
				#msi-cells = <1>;
				reg = <0x02c20000 0x10000>;
			};
		};

		smmu: mmu@03000000 {
			compatible = "arm,mmu-500";
			reg = <0x03000000 0x80000>;
			#global-interrupts = <1>;
			interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>;
			#iommu-cells = <2>;
		};
	};

	crmu: crmu {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x66400000 0x100000>;

		#include "stingray-clock.dtsi"

		gpio_crmu: gpio@00024800 {
			compatible = "brcm,iproc-gpio";
			reg = <0x00024800 0x4c>;
			ngpios = <6>;
			#gpio-cells = <2>;
			gpio-controller;
		};
	};

	hsls {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x68900000 0x17700000>;

		#include "stingray-pinctrl.dtsi"

		mdio_mux_iproc: mdio-mux@0002023c {
			compatible = "brcm,mdio-mux-iproc";
			reg = <0x0002023c 0x14>;
			#address-cells = <1>;
			#size-cells = <0>;

			mdio@0 { /* PCIe serdes */
				reg = <0x0>;
				#address-cells = <1>;
				#size-cells = <0>;
			};

			mdio@2 { /* SATA */
				reg = <0x2>;
				#address-cells = <1>;
				#size-cells = <0>;
			};

			mdio@3 { /* USB */
				reg = <0x3>;
				#address-cells = <1>;
				#size-cells = <0>;
			};

			mdio@10 { /* RGMII */
				reg = <0x10>;
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		pwm: pwm@00010000 {
			compatible = "brcm,iproc-pwm";
			reg = <0x00010000 0x1000>;
			clocks = <&crmu_ref25m>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		timer0: timer@00030000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x00030000 0x1000>;
			interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>,
				 <&hsls_25m_div2_clk>,
				 <&hsls_div4_clk>;
			clock-names = "timer1", "timer2", "apb_pclk";
			status = "disabled";
		};

		timer1: timer@00040000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x00040000 0x1000>;
			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>,
				 <&hsls_25m_div2_clk>,
				 <&hsls_div4_clk>;
			clock-names = "timer1", "timer2", "apb_pclk";
		};

		timer2: timer@00050000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x00050000 0x1000>;
			interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>,
				 <&hsls_25m_div2_clk>,
				 <&hsls_div4_clk>;
			clock-names = "timer1", "timer2", "apb_pclk";
			status = "disabled";
		};

		timer3: timer@00060000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x00060000 0x1000>;
			interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>,
				 <&hsls_25m_div2_clk>,
				 <&hsls_div4_clk>;
			clock-names = "timer1", "timer2", "apb_pclk";
			status = "disabled";
		};

		timer4: timer@00070000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x00070000 0x1000>;
			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>,
				 <&hsls_25m_div2_clk>,
				 <&hsls_div4_clk>;
			clock-names = "timer1", "timer2", "apb_pclk";
			status = "disabled";
		};

		timer5: timer@00080000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x00080000 0x1000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>,
				 <&hsls_25m_div2_clk>,
				 <&hsls_div4_clk>;
			clock-names = "timer1", "timer2", "apb_pclk";
			status = "disabled";
		};

		timer6: timer@00090000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x00090000 0x1000>;
			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>,
				 <&hsls_25m_div2_clk>,
				 <&hsls_div4_clk>;
			clock-names = "timer1", "timer2", "apb_pclk";
			status = "disabled";
		};

		timer7: timer@000a0000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x000a0000 0x1000>;
			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>,
				 <&hsls_25m_div2_clk>,
				 <&hsls_div4_clk>;
			clock-names = "timer1", "timer2", "apb_pclk";
			status = "disabled";
		};

		i2c0: i2c@000b0000 {
			compatible = "brcm,iproc-i2c";
			reg = <0x000b0000 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 177 IRQ_TYPE_NONE>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		wdt0: watchdog@000c0000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x000c0000 0x1000>;
			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>;
			clock-names = "wdogclk", "apb_pclk";
		};

		gpio_hsls: gpio@000d0000 {
			compatible = "brcm,iproc-gpio";
			reg = <0x000d0000 0x864>;
			ngpios = <151>;
			#gpio-cells = <2>;
			gpio-controller;
			interrupt-controller;
			interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
			gpio-ranges = <&pinmux 0 0 16>,
					<&pinmux 16 71 2>,
					<&pinmux 18 131 8>,
					<&pinmux 26 83 6>,
					<&pinmux 32 123 4>,
					<&pinmux 36 43 24>,
					<&pinmux 60 89 2>,
					<&pinmux 62 73 4>,
					<&pinmux 66 95 28>,
					<&pinmux 94 127 4>,
					<&pinmux 98 139 10>,
					<&pinmux 108 16 27>,
					<&pinmux 135 77 6>,
					<&pinmux 141 67 4>,
					<&pinmux 145 149 6>,
					<&pinmux 151 91 4>;
		};

		i2c1: i2c@000e0000 {
			compatible = "brcm,iproc-i2c";
			reg = <0x000e0000 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 178 IRQ_TYPE_NONE>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		uart0: uart@00100000 {
			device_type = "serial";
			compatible = "snps,dw-apb-uart";
			reg = <0x00100000 0x1000>;
			reg-shift = <2>;
			clock-frequency = <25000000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart1: uart@00110000 {
			device_type = "serial";
			compatible = "snps,dw-apb-uart";
			reg = <0x00110000 0x1000>;
			reg-shift = <2>;
			clock-frequency = <25000000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart2: uart@00120000 {
			device_type = "serial";
			compatible = "snps,dw-apb-uart";
			reg = <0x00120000 0x1000>;
			reg-shift = <2>;
			clock-frequency = <25000000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart3: uart@00130000 {
			device_type = "serial";
			compatible = "snps,dw-apb-uart";
			reg = <0x00130000 0x1000>;
			reg-shift = <2>;
			clock-frequency = <25000000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		ssp0: ssp@00180000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x00180000 0x1000>;
			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
			clock-names = "spiclk", "apb_pclk";
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		ssp1: ssp@00190000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x00190000 0x1000>;
			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
			clock-names = "spiclk", "apb_pclk";
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		hwrng: hwrng@00220000 {
			compatible = "brcm,iproc-rng200";
			reg = <0x00220000 0x28>;
		};

		dma0: dma@00310000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x00310000 0x1000>;
			interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			#dma-channels = <8>;
			#dma-requests = <32>;
			clocks = <&hsls_div2_clk>;
			clock-names = "apb_pclk";
			iommus = <&smmu 0x6000 0x0000>;
		};

		enet: ethernet@00340000{
			compatible = "brcm,amac";
			reg = <0x00340000 0x1000>;
			reg-names = "amac_base";
			dma-coherent;
			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
			status= "disabled";
		};

		nand: nand@00360000 {
			compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
			reg = <0x00360000 0x600>,
			      <0x0050a408 0x600>,
			      <0x00360f00 0x20>;
			reg-names = "nand", "iproc-idm", "iproc-ext";
			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			brcm,nand-has-wp;
			status = "disabled";
		};

		sdio0: sdhci@003f1000 {
			compatible = "brcm,sdhci-iproc";
			reg = <0x003f1000 0x100>;
			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
			bus-width = <8>;
			clocks = <&sdio0_clk>;
			iommus = <&smmu 0x6002 0x0000>;
			status = "disabled";
		};

		sdio1: sdhci@003f2000 {
			compatible = "brcm,sdhci-iproc";
			reg = <0x003f2000 0x100>;
			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
			bus-width = <8>;
			clocks = <&sdio1_clk>;
			iommus = <&smmu 0x6003 0x0000>;
			status = "disabled";
		};
	};
};
Commit	Line	Data
d4b4aba6 AP	1	/*
	2	* BSD LICENSE
	3	*
	4	* Copyright(c) 2015-2017 Broadcom. All rights reserved.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions
	8	* are met:
	9	*
	10	* * Redistributions of source code must retain the above copyright
	11	* notice, this list of conditions and the following disclaimer.
	12	* * Redistributions in binary form must reproduce the above copyright
	13	* notice, this list of conditions and the following disclaimer in
	14	* the documentation and/or other materials provided with the
	15	* distribution.
	16	* * Neither the name of Broadcom nor the names of its
	17	* contributors may be used to endorse or promote products derived
	18	* from this software without specific prior written permission.
	19	*
	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	21	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	22	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	23	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	24	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	25	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	26	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	27	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	28	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	29	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	30	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	31	*/
	32
	33	#include <dt-bindings/interrupt-controller/arm-gic.h>
	34
	35	/ {
	36	compatible = "brcm,stingray";
	37	interrupt-parent = <&gic>;
	38	#address-cells = <2>;
	39	#size-cells = <2>;
	40
	41	cpus {
	42	#address-cells = <2>;
	43	#size-cells = <0>;
	44
	45	cpu@000 {
	46	device_type = "cpu";
	47	compatible = "arm,cortex-a72", "arm,armv8";
	48	reg = <0x0 0x0>;
	49	enable-method = "psci";
	50	next-level-cache = <&CLUSTER0_L2>;
	51	};
	52
	53	cpu@001 {
	54	device_type = "cpu";
	55	compatible = "arm,cortex-a72", "arm,armv8";
	56	reg = <0x0 0x1>;
	57	enable-method = "psci";
	58	next-level-cache = <&CLUSTER0_L2>;
	59	};
	60
	61	cpu@100 {
	62	device_type = "cpu";
	63	compatible = "arm,cortex-a72", "arm,armv8";
	64	reg = <0x0 0x100>;
65	enable-method = "psci";
66	next-level-cache = <&CLUSTER1_L2>;
67	};
68
69	cpu@101 {
70	device_type = "cpu";
71	compatible = "arm,cortex-a72", "arm,armv8";
72	reg = <0x0 0x101>;
73	enable-method = "psci";
74	next-level-cache = <&CLUSTER1_L2>;
75	};
76
77	cpu@200 {
78	device_type = "cpu";
79	compatible = "arm,cortex-a72", "arm,armv8";
80	reg = <0x0 0x200>;
81	enable-method = "psci";
82	next-level-cache = <&CLUSTER2_L2>;
83	};
84
85	cpu@201 {
86	device_type = "cpu";
87	compatible = "arm,cortex-a72", "arm,armv8";
88	reg = <0x0 0x201>;
89	enable-method = "psci";
90	next-level-cache = <&CLUSTER2_L2>;
91	};
92
93	cpu@300 {
94	device_type = "cpu";
95	compatible = "arm,cortex-a72", "arm,armv8";
96	reg = <0x0 0x300>;
97	enable-method = "psci";
98	next-level-cache = <&CLUSTER3_L2>;
99	};
100
101	cpu@301 {
102	device_type = "cpu";
103	compatible = "arm,cortex-a72", "arm,armv8";
104	reg = <0x0 0x301>;
105	enable-method = "psci";
106	next-level-cache = <&CLUSTER3_L2>;
107	};
108
109	CLUSTER0_L2: l2-cache@000 {
110	compatible = "cache";
111	};
112
113	CLUSTER1_L2: l2-cache@100 {
114	compatible = "cache";
115	};
116
117	CLUSTER2_L2: l2-cache@200 {
118	compatible = "cache";
119	};
120
121	CLUSTER3_L2: l2-cache@300 {
122	compatible = "cache";
123	};
124	};
125
126	memory: memory@80000000 {
127	device_type = "memory";
128	reg = <0x00000000 0x80000000 0 0x40000000>;
129	};
130
131	psci {
132	compatible = "arm,psci-0.2";
133	method = "smc";
134	};
135
136	pmu {
137	compatible = "arm,armv8-pmuv3";
138	interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
139	};
140
141	timer {
142	compatible = "arm,armv8-timer";
143	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
144	<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
145	<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
146	<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
147	};
148
149	scr {
150	compatible = "simple-bus";
151	#address-cells = <1>;
152	#size-cells = <1>;
153	ranges = <0x0 0x0 0x61000000 0x05000000>;
154
5ace3533 VM	155	ccn: ccn@00000000 {
	156	compatible = "arm,ccn-502";
	157	reg = <0x00000000 0x900000>;
	158	interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
	159	};
	160
d4b4aba6 AP	161	gic: interrupt-controller@02c00000 {
	162	compatible = "arm,gic-v3";
	163	#interrupt-cells = <3>;
	164	#address-cells = <1>;
	165	#size-cells = <1>;
	166	ranges;
	167	interrupt-controller;
	168	reg = <0x02c00000 0x010000>, /* GICD */
	169	<0x02e00000 0x600000>; /* GICR */
	170	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	171
	172	gic_its: gic-its@63c20000 {
	173	compatible = "arm,gic-v3-its";
	174	msi-controller;
	175	#msi-cells = <1>;
	176	reg = <0x02c20000 0x10000>;
	177	};
	178	};
	179
	180	smmu: mmu@03000000 {
	181	compatible = "arm,mmu-500";
	182	reg = <0x03000000 0x80000>;
	183	#global-interrupts = <1>;
	184	interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>,
	185	<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
	186	<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
	187	<GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
	188	<GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
	189	<GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
	190	<GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
	191	<GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>,
	192	<GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>,
	193	<GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>,
	194	<GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>,
	195	<GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>,
	196	<GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>,
	197	<GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>,
	198	<GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>,
	199	<GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>,
	200	<GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>,
	201	<GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>,
	202	<GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>,
	203	<GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>,
	204	<GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>,
	205	<GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>,
	206	<GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>,
	207	<GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>,
	208	<GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>,
	209	<GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
	210	<GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>,
	211	<GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
	212	<GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>,
	213	<GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
	214	<GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>,
	215	<GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>,
	216	<GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>,
	217	<GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>,
	218	<GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>,
	219	<GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
	220	<GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>,
	221	<GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>,
	222	<GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>,
	223	<GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>,
	224	<GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>,
225	<GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>,
226	<GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
227	<GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
228	<GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>,
229	<GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>,
230	<GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
231	<GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
232	<GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
233	<GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
234	<GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
235	<GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
236	<GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
237	<GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>,
238	<GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>,
239	<GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
240	<GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
241	<GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
242	<GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
243	<GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
244	<GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
245	<GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
246	<GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
247	<GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
248	<GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>;
249	#iommu-cells = <2>;
250	};
251	};
252
73da8f97 ST	253	crmu: crmu {
	254	compatible = "simple-bus";
	255	#address-cells = <1>;
	256	#size-cells = <1>;
	257	ranges = <0x0 0x0 0x66400000 0x100000>;
	258
	259	#include "stingray-clock.dtsi"
2fa9e9e2 PK	260
	261	gpio_crmu: gpio@00024800 {
	262	compatible = "brcm,iproc-gpio";
	263	reg = <0x00024800 0x4c>;
	264	ngpios = <6>;
	265	#gpio-cells = <2>;
	266	gpio-controller;
	267	};
73da8f97 ST	268	};
73da8f97 ST	269
d4b4aba6 AP	270	hsls {
	271	compatible = "simple-bus";
	272	#address-cells = <1>;
	273	#size-cells = <1>;
	274	ranges = <0x0 0x0 0x68900000 0x17700000>;
	275
8aa428cc PK	276	#include "stingray-pinctrl.dtsi"
8aa428cc PK	277
fd898f75 SM	278	mdio_mux_iproc: mdio-mux@0002023c {
	279	compatible = "brcm,mdio-mux-iproc";
	280	reg = <0x0002023c 0x14>;
	281	#address-cells = <1>;
	282	#size-cells = <0>;
	283
	284	mdio@0 { /* PCIe serdes */
	285	reg = <0x0>;
	286	#address-cells = <1>;
	287	#size-cells = <0>;
	288	};
	289
	290	mdio@2 { /* SATA */
	291	reg = <0x2>;
	292	#address-cells = <1>;
	293	#size-cells = <0>;
	294	};
	295
	296	mdio@3 { /* USB */
	297	reg = <0x3>;
	298	#address-cells = <1>;
	299	#size-cells = <0>;
	300	};
	301
	302	mdio@10 { /* RGMII */
	303	reg = <0x10>;
	304	#address-cells = <1>;
	305	#size-cells = <0>;
	306	};
	307	};
	308
552df263 SM	309	pwm: pwm@00010000 {
	310	compatible = "brcm,iproc-pwm";
	311	reg = <0x00010000 0x1000>;
	312	clocks = <&crmu_ref25m>;
	313	#pwm-cells = <3>;
	314	status = "disabled";
	315	};
	316
567b3b0a AP	317	timer0: timer@00030000 {
	318	compatible = "arm,sp804", "arm,primecell";
	319	reg = <0x00030000 0x1000>;
	320	interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
	321	clocks = <&hsls_25m_div2_clk>,
	322	<&hsls_25m_div2_clk>,
	323	<&hsls_div4_clk>;
	324	clock-names = "timer1", "timer2", "apb_pclk";
	325	status = "disabled";
	326	};
	327
	328	timer1: timer@00040000 {
	329	compatible = "arm,sp804", "arm,primecell";
	330	reg = <0x00040000 0x1000>;
	331	interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
	332	clocks = <&hsls_25m_div2_clk>,
	333	<&hsls_25m_div2_clk>,
	334	<&hsls_div4_clk>;
	335	clock-names = "timer1", "timer2", "apb_pclk";
	336	};
	337
	338	timer2: timer@00050000 {
	339	compatible = "arm,sp804", "arm,primecell";
	340	reg = <0x00050000 0x1000>;
	341	interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
	342	clocks = <&hsls_25m_div2_clk>,
	343	<&hsls_25m_div2_clk>,
	344	<&hsls_div4_clk>;
	345	clock-names = "timer1", "timer2", "apb_pclk";
	346	status = "disabled";
	347	};
	348
	349	timer3: timer@00060000 {
	350	compatible = "arm,sp804", "arm,primecell";
	351	reg = <0x00060000 0x1000>;
	352	interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
	353	clocks = <&hsls_25m_div2_clk>,
	354	<&hsls_25m_div2_clk>,
	355	<&hsls_div4_clk>;
	356	clock-names = "timer1", "timer2", "apb_pclk";
	357	status = "disabled";
	358	};
	359
	360	timer4: timer@00070000 {
	361	compatible = "arm,sp804", "arm,primecell";
	362	reg = <0x00070000 0x1000>;
	363	interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
	364	clocks = <&hsls_25m_div2_clk>,
	365	<&hsls_25m_div2_clk>,
	366	<&hsls_div4_clk>;
	367	clock-names = "timer1", "timer2", "apb_pclk";
	368	status = "disabled";
	369	};
	370
	371	timer5: timer@00080000 {
	372	compatible = "arm,sp804", "arm,primecell";
	373	reg = <0x00080000 0x1000>;
	374	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	375	clocks = <&hsls_25m_div2_clk>,
	376	<&hsls_25m_div2_clk>,
	377	<&hsls_div4_clk>;
	378	clock-names = "timer1", "timer2", "apb_pclk";
	379	status = "disabled";
	380	};
381
382	timer6: timer@00090000 {
383	compatible = "arm,sp804", "arm,primecell";
384	reg = <0x00090000 0x1000>;
385	interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
386	clocks = <&hsls_25m_div2_clk>,
387	<&hsls_25m_div2_clk>,
388	<&hsls_div4_clk>;
389	clock-names = "timer1", "timer2", "apb_pclk";
390	status = "disabled";
391	};
392
393	timer7: timer@000a0000 {
394	compatible = "arm,sp804", "arm,primecell";
395	reg = <0x000a0000 0x1000>;
396	interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
397	clocks = <&hsls_25m_div2_clk>,
398	<&hsls_25m_div2_clk>,
399	<&hsls_div4_clk>;
400	clock-names = "timer1", "timer2", "apb_pclk";
401	status = "disabled";
402	};
403
1256ea18 OP	404	i2c0: i2c@000b0000 {
	405	compatible = "brcm,iproc-i2c";
	406	reg = <0x000b0000 0x100>;
	407	#address-cells = <1>;
	408	#size-cells = <0>;
	409	interrupts = <GIC_SPI 177 IRQ_TYPE_NONE>;
	410	clock-frequency = <100000>;
	411	status = "disabled";
	412	};
	413
0dc454ee AP	414	wdt0: watchdog@000c0000 {
	415	compatible = "arm,sp805", "arm,primecell";
	416	reg = <0x000c0000 0x1000>;
	417	interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
	418	clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>;
	419	clock-names = "wdogclk", "apb_pclk";
	420	};
	421
2fa9e9e2 PK	422	gpio_hsls: gpio@000d0000 {
	423	compatible = "brcm,iproc-gpio";
	424	reg = <0x000d0000 0x864>;
	425	ngpios = <151>;
	426	#gpio-cells = <2>;
	427	gpio-controller;
	428	interrupt-controller;
	429	interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
	430	gpio-ranges = <&pinmux 0 0 16>,
	431	<&pinmux 16 71 2>,
	432	<&pinmux 18 131 8>,
	433	<&pinmux 26 83 6>,
	434	<&pinmux 32 123 4>,
	435	<&pinmux 36 43 24>,
	436	<&pinmux 60 89 2>,
	437	<&pinmux 62 73 4>,
	438	<&pinmux 66 95 28>,
	439	<&pinmux 94 127 4>,
	440	<&pinmux 98 139 10>,
	441	<&pinmux 108 16 27>,
	442	<&pinmux 135 77 6>,
	443	<&pinmux 141 67 4>,
	444	<&pinmux 145 149 6>,
	445	<&pinmux 151 91 4>;
	446	};
	447
1256ea18 OP	448	i2c1: i2c@000e0000 {
	449	compatible = "brcm,iproc-i2c";
	450	reg = <0x000e0000 0x100>;
	451	#address-cells = <1>;
	452	#size-cells = <0>;
	453	interrupts = <GIC_SPI 178 IRQ_TYPE_NONE>;
	454	clock-frequency = <100000>;
	455	status = "disabled";
	456	};
	457
d4b4aba6 AP	458	uart0: uart@00100000 {
	459	device_type = "serial";
	460	compatible = "snps,dw-apb-uart";
	461	reg = <0x00100000 0x1000>;
	462	reg-shift = <2>;
	463	clock-frequency = <25000000>;
	464	interrupt-parent = <&gic>;
	465	interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
	466	status = "disabled";
	467	};
	468
	469	uart1: uart@00110000 {
	470	device_type = "serial";
	471	compatible = "snps,dw-apb-uart";
	472	reg = <0x00110000 0x1000>;
	473	reg-shift = <2>;
	474	clock-frequency = <25000000>;
	475	interrupt-parent = <&gic>;
	476	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	477	status = "disabled";
	478	};
	479
	480	uart2: uart@00120000 {
	481	device_type = "serial";
	482	compatible = "snps,dw-apb-uart";
	483	reg = <0x00120000 0x1000>;
	484	reg-shift = <2>;
	485	clock-frequency = <25000000>;
	486	interrupt-parent = <&gic>;
	487	interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
	488	status = "disabled";
	489	};
	490
	491	uart3: uart@00130000 {
	492	device_type = "serial";
	493	compatible = "snps,dw-apb-uart";
	494	reg = <0x00130000 0x1000>;
	495	reg-shift = <2>;
	496	clock-frequency = <25000000>;
	497	interrupt-parent = <&gic>;
	498	interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
	499	status = "disabled";
	500	};
	501
0dc454ee AP	502	ssp0: ssp@00180000 {
	503	compatible = "arm,pl022", "arm,primecell";
	504	reg = <0x00180000 0x1000>;
	505	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
	506	clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
	507	clock-names = "spiclk", "apb_pclk";
	508	num-cs = <1>;
	509	#address-cells = <1>;
	510	#size-cells = <0>;
	511	status = "disabled";
	512	};
	513
	514	ssp1: ssp@00190000 {
	515	compatible = "arm,pl022", "arm,primecell";
	516	reg = <0x00190000 0x1000>;
	517	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
	518	clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
	519	clock-names = "spiclk", "apb_pclk";
	520	num-cs = <1>;
	521	#address-cells = <1>;
	522	#size-cells = <0>;
	523	status = "disabled";
	524	};
	525
d4b4aba6 AP	526	hwrng: hwrng@00220000 {
	527	compatible = "brcm,iproc-rng200";
	528	reg = <0x00220000 0x28>;
	529	};
0f67ae37	530
0dc454ee AP	531	dma0: dma@00310000 {
	532	compatible = "arm,pl330", "arm,primecell";
	533	reg = <0x00310000 0x1000>;
	534	interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
	535	<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
	536	<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
	537	<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
	538	<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
	539	<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
	540	<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
	541	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	542	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
	543	#dma-cells = <1>;
	544	#dma-channels = <8>;
	545	#dma-requests = <32>;
	546	clocks = <&hsls_div2_clk>;
	547	clock-names = "apb_pclk";
	548	iommus = <&smmu 0x6000 0x0000>;
	549	};
	550
80e2cbc1 AS	551	enet: ethernet@00340000{
	552	compatible = "brcm,amac";
	553	reg = <0x00340000 0x1000>;
	554	reg-names = "amac_base";
	555	dma-coherent;
	556	interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
	557	status= "disabled";
	558	};
	559
0f67ae37 PK	560	nand: nand@00360000 {
	561	compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
	562	reg = <0x00360000 0x600>,
	563	<0x0050a408 0x600>,
	564	<0x00360f00 0x20>;
	565	reg-names = "nand", "iproc-idm", "iproc-ext";
	566	interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
	567	#address-cells = <1>;
	568	#size-cells = <0>;
	569	brcm,nand-has-wp;
	570	status = "disabled";
	571	};
552df263 SM	572
	573	sdio0: sdhci@003f1000 {
	574	compatible = "brcm,sdhci-iproc";
	575	reg = <0x003f1000 0x100>;
	576	interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
	577	bus-width = <8>;
	578	clocks = <&sdio0_clk>;
	579	iommus = <&smmu 0x6002 0x0000>;
	580	status = "disabled";
	581	};
	582
	583	sdio1: sdhci@003f2000 {
	584	compatible = "brcm,sdhci-iproc";
	585	reg = <0x003f2000 0x100>;
	586	interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
	587	bus-width = <8>;
	588	clocks = <&sdio1_clk>;
	589	iommus = <&smmu 0x6003 0x0000>;
	590	status = "disabled";
	591	};
d4b4aba6 AP	592	};
d4b4aba6 AP	593	};