[mirror_ubuntu-focal-kernel.git] / arch / arm64 / boot / dts / broadcom / stingray / stingray.dtsi

/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2015-2017 Broadcom.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "brcm,stingray";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu@000 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER0_L2>;
		};

		cpu@001 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0 0x1>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER0_L2>;
		};

		cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0 0x100>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER1_L2>;
		};

		cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0 0x101>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER1_L2>;
		};

		cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0 0x200>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER2_L2>;
		};

		cpu@201 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0 0x201>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER2_L2>;
		};

		cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0 0x300>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER3_L2>;
		};

		cpu@301 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0 0x301>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER3_L2>;
		};

		CLUSTER0_L2: l2-cache@000 {
			compatible = "cache";
		};

		CLUSTER1_L2: l2-cache@100 {
			compatible = "cache";
		};

		CLUSTER2_L2: l2-cache@200 {
			compatible = "cache";
		};

		CLUSTER3_L2: l2-cache@300 {
			compatible = "cache";
		};
	};

	memory: memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0 0x40000000>;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	scr {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x61000000 0x05000000>;

		gic: interrupt-controller@02c00000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <3>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			interrupt-controller;
			reg = <0x02c00000 0x010000>, /* GICD */
			      <0x02e00000 0x600000>; /* GICR */
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

			gic_its: gic-its@63c20000 {
				compatible = "arm,gic-v3-its";
				msi-controller;
				#msi-cells = <1>;
				reg = <0x02c20000 0x10000>;
			};
		};

		smmu: mmu@03000000 {
			compatible = "arm,mmu-500";
			reg = <0x03000000 0x80000>;
			#global-interrupts = <1>;
			interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>;
			#iommu-cells = <2>;
		};
	};

	crmu: crmu {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x66400000 0x100000>;

		#include "stingray-clock.dtsi"
	};

	hsls {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x68900000 0x17700000>;

		#include "stingray-pinctrl.dtsi"

		uart0: uart@00100000 {
			device_type = "serial";
			compatible = "snps,dw-apb-uart";
			reg = <0x00100000 0x1000>;
			reg-shift = <2>;
			clock-frequency = <25000000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart1: uart@00110000 {
			device_type = "serial";
			compatible = "snps,dw-apb-uart";
			reg = <0x00110000 0x1000>;
			reg-shift = <2>;
			clock-frequency = <25000000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart2: uart@00120000 {
			device_type = "serial";
			compatible = "snps,dw-apb-uart";
			reg = <0x00120000 0x1000>;
			reg-shift = <2>;
			clock-frequency = <25000000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart3: uart@00130000 {
			device_type = "serial";
			compatible = "snps,dw-apb-uart";
			reg = <0x00130000 0x1000>;
			reg-shift = <2>;
			clock-frequency = <25000000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		hwrng: hwrng@00220000 {
			compatible = "brcm,iproc-rng200";
			reg = <0x00220000 0x28>;
		};

		nand: nand@00360000 {
			compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
			reg = <0x00360000 0x600>,
			      <0x0050a408 0x600>,
			      <0x00360f00 0x20>;
			reg-names = "nand", "iproc-idm", "iproc-ext";
			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			brcm,nand-has-wp;
			status = "disabled";
		};
	};
};
Commit	Line	Data
d4b4aba6 AP	1	/*
	2	* BSD LICENSE
	3	*
	4	* Copyright(c) 2015-2017 Broadcom. All rights reserved.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions
	8	* are met:
	9	*
	10	* * Redistributions of source code must retain the above copyright
	11	* notice, this list of conditions and the following disclaimer.
	12	* * Redistributions in binary form must reproduce the above copyright
	13	* notice, this list of conditions and the following disclaimer in
	14	* the documentation and/or other materials provided with the
	15	* distribution.
	16	* * Neither the name of Broadcom nor the names of its
	17	* contributors may be used to endorse or promote products derived
	18	* from this software without specific prior written permission.
	19	*
	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	21	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	22	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	23	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	24	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	25	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	26	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	27	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	28	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	29	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	30	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	31	*/
	32
	33	#include <dt-bindings/interrupt-controller/arm-gic.h>
	34
	35	/ {
	36	compatible = "brcm,stingray";
	37	interrupt-parent = <&gic>;
	38	#address-cells = <2>;
	39	#size-cells = <2>;
	40
	41	cpus {
	42	#address-cells = <2>;
	43	#size-cells = <0>;
	44
	45	cpu@000 {
	46	device_type = "cpu";
	47	compatible = "arm,cortex-a72", "arm,armv8";
	48	reg = <0x0 0x0>;
	49	enable-method = "psci";
	50	next-level-cache = <&CLUSTER0_L2>;
	51	};
	52
	53	cpu@001 {
	54	device_type = "cpu";
	55	compatible = "arm,cortex-a72", "arm,armv8";
	56	reg = <0x0 0x1>;
	57	enable-method = "psci";
	58	next-level-cache = <&CLUSTER0_L2>;
	59	};
	60
	61	cpu@100 {
	62	device_type = "cpu";
	63	compatible = "arm,cortex-a72", "arm,armv8";
	64	reg = <0x0 0x100>;
65	enable-method = "psci";
66	next-level-cache = <&CLUSTER1_L2>;
67	};
68
69	cpu@101 {
70	device_type = "cpu";
71	compatible = "arm,cortex-a72", "arm,armv8";
72	reg = <0x0 0x101>;
73	enable-method = "psci";
74	next-level-cache = <&CLUSTER1_L2>;
75	};
76
77	cpu@200 {
78	device_type = "cpu";
79	compatible = "arm,cortex-a72", "arm,armv8";
80	reg = <0x0 0x200>;
81	enable-method = "psci";
82	next-level-cache = <&CLUSTER2_L2>;
83	};
84
85	cpu@201 {
86	device_type = "cpu";
87	compatible = "arm,cortex-a72", "arm,armv8";
88	reg = <0x0 0x201>;
89	enable-method = "psci";
90	next-level-cache = <&CLUSTER2_L2>;
91	};
92
93	cpu@300 {
94	device_type = "cpu";
95	compatible = "arm,cortex-a72", "arm,armv8";
96	reg = <0x0 0x300>;
97	enable-method = "psci";
98	next-level-cache = <&CLUSTER3_L2>;
99	};
100
101	cpu@301 {
102	device_type = "cpu";
103	compatible = "arm,cortex-a72", "arm,armv8";
104	reg = <0x0 0x301>;
105	enable-method = "psci";
106	next-level-cache = <&CLUSTER3_L2>;
107	};
108
109	CLUSTER0_L2: l2-cache@000 {
110	compatible = "cache";
111	};
112
113	CLUSTER1_L2: l2-cache@100 {
114	compatible = "cache";
115	};
116
117	CLUSTER2_L2: l2-cache@200 {
118	compatible = "cache";
119	};
120
121	CLUSTER3_L2: l2-cache@300 {
122	compatible = "cache";
123	};
124	};
125
126	memory: memory@80000000 {
127	device_type = "memory";
128	reg = <0x00000000 0x80000000 0 0x40000000>;
129	};
130
131	psci {
132	compatible = "arm,psci-0.2";
133	method = "smc";
134	};
135
136	pmu {
137	compatible = "arm,armv8-pmuv3";
138	interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
139	};
140
141	timer {
142	compatible = "arm,armv8-timer";
143	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
144	<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
145	<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
146	<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
147	};
148
149	scr {
150	compatible = "simple-bus";
151	#address-cells = <1>;
152	#size-cells = <1>;
153	ranges = <0x0 0x0 0x61000000 0x05000000>;
154
155	gic: interrupt-controller@02c00000 {
156	compatible = "arm,gic-v3";
157	#interrupt-cells = <3>;
158	#address-cells = <1>;
159	#size-cells = <1>;
160	ranges;
161	interrupt-controller;
162	reg = <0x02c00000 0x010000>, /* GICD */
163	<0x02e00000 0x600000>; /* GICR */
164	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
165
166	gic_its: gic-its@63c20000 {
167	compatible = "arm,gic-v3-its";
168	msi-controller;
169	#msi-cells = <1>;
170	reg = <0x02c20000 0x10000>;
171	};
172	};
173
174	smmu: mmu@03000000 {
175	compatible = "arm,mmu-500";
176	reg = <0x03000000 0x80000>;
177	#global-interrupts = <1>;
178	interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>,
179	<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
180	<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
181	<GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
182	<GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
183	<GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
184	<GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
185	<GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>,
186	<GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>,
187	<GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>,
188	<GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>,
189	<GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>,
190	<GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>,
191	<GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>,
192	<GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>,
193	<GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>,
194	<GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>,
195	<GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>,
196	<GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>,
197	<GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>,
198	<GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>,
199	<GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>,
200	<GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>,
201	<GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>,
202	<GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>,
203	<GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
204	<GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>,
205	<GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
206	<GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>,
207	<GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
208	<GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>,
209	<GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>,
210	<GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>,
211	<GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>,
212	<GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>,
213	<GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
214	<GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>,
215	<GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>,
216	<GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>,
217	<GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>,
218	<GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>,
219	<GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>,
220	<GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
221	<GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
222	<GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>,
223	<GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>,
224	<GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
225	<GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
226	<GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
227	<GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
228	<GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
229	<GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
230	<GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
231	<GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>,
232	<GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>,
233	<GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
234	<GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
235	<GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
236	<GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
237	<GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
238	<GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
239	<GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
240	<GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
241	<GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
242	<GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>;
243	#iommu-cells = <2>;
244	};
245	};
246
73da8f97 ST	247	crmu: crmu {
	248	compatible = "simple-bus";
	249	#address-cells = <1>;
	250	#size-cells = <1>;
	251	ranges = <0x0 0x0 0x66400000 0x100000>;
	252
	253	#include "stingray-clock.dtsi"
	254	};
	255
d4b4aba6 AP	256	hsls {
	257	compatible = "simple-bus";
	258	#address-cells = <1>;
	259	#size-cells = <1>;
	260	ranges = <0x0 0x0 0x68900000 0x17700000>;
	261
8aa428cc PK	262	#include "stingray-pinctrl.dtsi"
8aa428cc PK	263
d4b4aba6 AP	264	uart0: uart@00100000 {
	265	device_type = "serial";
	266	compatible = "snps,dw-apb-uart";
	267	reg = <0x00100000 0x1000>;
	268	reg-shift = <2>;
	269	clock-frequency = <25000000>;
	270	interrupt-parent = <&gic>;
	271	interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
	272	status = "disabled";
	273	};
	274
	275	uart1: uart@00110000 {
	276	device_type = "serial";
	277	compatible = "snps,dw-apb-uart";
	278	reg = <0x00110000 0x1000>;
	279	reg-shift = <2>;
	280	clock-frequency = <25000000>;
	281	interrupt-parent = <&gic>;
	282	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	283	status = "disabled";
	284	};
	285
	286	uart2: uart@00120000 {
	287	device_type = "serial";
	288	compatible = "snps,dw-apb-uart";
	289	reg = <0x00120000 0x1000>;
	290	reg-shift = <2>;
	291	clock-frequency = <25000000>;
	292	interrupt-parent = <&gic>;
	293	interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
	294	status = "disabled";
	295	};
	296
	297	uart3: uart@00130000 {
	298	device_type = "serial";
	299	compatible = "snps,dw-apb-uart";
	300	reg = <0x00130000 0x1000>;
	301	reg-shift = <2>;
	302	clock-frequency = <25000000>;
	303	interrupt-parent = <&gic>;
	304	interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
	305	status = "disabled";
	306	};
	307
	308	hwrng: hwrng@00220000 {
	309	compatible = "brcm,iproc-rng200";
	310	reg = <0x00220000 0x28>;
	311	};
0f67ae37 PK	312
	313	nand: nand@00360000 {
	314	compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
	315	reg = <0x00360000 0x600>,
	316	<0x0050a408 0x600>,
	317	<0x00360f00 0x20>;
	318	reg-names = "nand", "iproc-idm", "iproc-ext";
	319	interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
	320	#address-cells = <1>;
	321	#size-cells = <0>;
	322	brcm,nand-has-wp;
	323	status = "disabled";
	324	};
d4b4aba6 AP	325	};
d4b4aba6 AP	326	};