[mirror_ubuntu-focal-kernel.git] / arch / arm64 / boot / dts / broadcom / stingray / stingray.dtsi

/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2015-2017 Broadcom.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "brcm,stingray";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER0_L2>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0 0x1>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER0_L2>;
		};

		cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0 0x100>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER1_L2>;
		};

		cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0 0x101>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER1_L2>;
		};

		cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0 0x200>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER2_L2>;
		};

		cpu@201 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0 0x201>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER2_L2>;
		};

		cpu@300 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0 0x300>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER3_L2>;
		};

		cpu@301 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x0 0x301>;
			enable-method = "psci";
			next-level-cache = <&CLUSTER3_L2>;
		};

		CLUSTER0_L2: l2-cache@0 {
			compatible = "cache";
		};

		CLUSTER1_L2: l2-cache@100 {
			compatible = "cache";
		};

		CLUSTER2_L2: l2-cache@200 {
			compatible = "cache";
		};

		CLUSTER3_L2: l2-cache@300 {
			compatible = "cache";
		};
	};

	memory: memory@80000000 {
		device_type = "memory";
		reg = <0x00000000 0x80000000 0 0x40000000>;
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	mhb: syscon@60401000 {
		compatible = "brcm,sr-mhb", "syscon";
		reg = <0 0x60401000 0 0x38c>;
	};

	scr {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x61000000 0x05000000>;

		ccn: ccn@0 {
			compatible = "arm,ccn-502";
			reg = <0x00000000 0x900000>;
			interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
		};

		gic: interrupt-controller@2c00000 {
			compatible = "arm,gic-v3";
			#interrupt-cells = <3>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			interrupt-controller;
			reg = <0x02c00000 0x010000>, /* GICD */
			      <0x02e00000 0x600000>; /* GICR */
			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

			gic_its: gic-its@63c20000 {
				compatible = "arm,gic-v3-its";
				msi-controller;
				#msi-cells = <1>;
				reg = <0x02c20000 0x10000>;
			};
		};

		smmu: mmu@3000000 {
			compatible = "arm,mmu-500";
			reg = <0x03000000 0x80000>;
			#global-interrupts = <1>;
			interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>;
			#iommu-cells = <2>;
		};
	};

	crmu: crmu {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x66400000 0x100000>;

		#include "stingray-clock.dtsi"

		otp: otp@1c400 {
			compatible = "brcm,ocotp-v2";
			reg = <0x0001c400 0x68>;
			brcm,ocotp-size = <2048>;
			status = "okay";
		};

		cdru: syscon@1d000 {
			compatible = "brcm,sr-cdru", "syscon";
			reg = <0x0001d000 0x400>;
		};

		gpio_crmu: gpio@24800 {
			compatible = "brcm,iproc-gpio";
			reg = <0x00024800 0x4c>;
			ngpios = <6>;
			#gpio-cells = <2>;
			gpio-controller;
		};
	};

	#include "stingray-fs4.dtsi"
	#include "stingray-sata.dtsi"
	#include "stingray-pcie.dtsi"

	hsls {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x68900000 0x17700000>;

		#include "stingray-pinctrl.dtsi"

		mdio_mux_iproc: mdio-mux@20000 {
			compatible = "brcm,mdio-mux-iproc";
			reg = <0x00020000 0x250>;
			#address-cells = <1>;
			#size-cells = <0>;

			mdio@0 { /* PCIe serdes */
				reg = <0x0>;
				#address-cells = <1>;
				#size-cells = <0>;
			};

			mdio@2 { /* SATA */
				reg = <0x2>;
				#address-cells = <1>;
				#size-cells = <0>;
			};

			mdio@3 { /* USB */
				reg = <0x3>;
				#address-cells = <1>;
				#size-cells = <0>;
			};

			mdio@10 { /* RGMII */
				reg = <0x10>;
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		pwm: pwm@10000 {
			compatible = "brcm,iproc-pwm";
			reg = <0x00010000 0x1000>;
			clocks = <&crmu_ref25m>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		timer0: timer@30000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x00030000 0x1000>;
			interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>,
				 <&hsls_25m_div2_clk>,
				 <&hsls_div4_clk>;
			clock-names = "timer1", "timer2", "apb_pclk";
			status = "disabled";
		};

		timer1: timer@40000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x00040000 0x1000>;
			interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>,
				 <&hsls_25m_div2_clk>,
				 <&hsls_div4_clk>;
			clock-names = "timer1", "timer2", "apb_pclk";
		};

		timer2: timer@50000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x00050000 0x1000>;
			interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>,
				 <&hsls_25m_div2_clk>,
				 <&hsls_div4_clk>;
			clock-names = "timer1", "timer2", "apb_pclk";
			status = "disabled";
		};

		timer3: timer@60000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x00060000 0x1000>;
			interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>,
				 <&hsls_25m_div2_clk>,
				 <&hsls_div4_clk>;
			clock-names = "timer1", "timer2", "apb_pclk";
			status = "disabled";
		};

		timer4: timer@70000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x00070000 0x1000>;
			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>,
				 <&hsls_25m_div2_clk>,
				 <&hsls_div4_clk>;
			clock-names = "timer1", "timer2", "apb_pclk";
			status = "disabled";
		};

		timer5: timer@80000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x00080000 0x1000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>,
				 <&hsls_25m_div2_clk>,
				 <&hsls_div4_clk>;
			clock-names = "timer1", "timer2", "apb_pclk";
			status = "disabled";
		};

		timer6: timer@90000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x00090000 0x1000>;
			interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>,
				 <&hsls_25m_div2_clk>,
				 <&hsls_div4_clk>;
			clock-names = "timer1", "timer2", "apb_pclk";
			status = "disabled";
		};

		timer7: timer@a0000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x000a0000 0x1000>;
			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>,
				 <&hsls_25m_div2_clk>,
				 <&hsls_div4_clk>;
			clock-names = "timer1", "timer2", "apb_pclk";
			status = "disabled";
		};

		i2c0: i2c@b0000 {
			compatible = "brcm,iproc-i2c";
			reg = <0x000b0000 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		wdt0: watchdog@c0000 {
			compatible = "arm,sp805", "arm,primecell";
			reg = <0x000c0000 0x1000>;
			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>;
			clock-names = "wdogclk", "apb_pclk";
			timeout-sec = <60>;
		};

		gpio_hsls: gpio@d0000 {
			compatible = "brcm,iproc-gpio";
			reg = <0x000d0000 0x864>;
			ngpios = <151>;
			#gpio-cells = <2>;
			gpio-controller;
			interrupt-controller;
			interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
			gpio-ranges = <&pinmux 0 0 16>,
					<&pinmux 16 71 2>,
					<&pinmux 18 131 8>,
					<&pinmux 26 83 6>,
					<&pinmux 32 123 4>,
					<&pinmux 36 43 24>,
					<&pinmux 60 89 2>,
					<&pinmux 62 73 4>,
					<&pinmux 66 95 28>,
					<&pinmux 94 127 4>,
					<&pinmux 98 139 10>,
					<&pinmux 108 16 27>,
					<&pinmux 135 77 6>,
					<&pinmux 141 67 4>,
					<&pinmux 145 149 6>,
					<&pinmux 151 91 4>;
		};

		i2c1: i2c@e0000 {
			compatible = "brcm,iproc-i2c";
			reg = <0x000e0000 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <100000>;
			status = "disabled";
		};

		uart0: uart@100000 {
			device_type = "serial";
			compatible = "snps,dw-apb-uart";
			reg = <0x00100000 0x1000>;
			reg-shift = <2>;
			clock-frequency = <25000000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart1: uart@110000 {
			device_type = "serial";
			compatible = "snps,dw-apb-uart";
			reg = <0x00110000 0x1000>;
			reg-shift = <2>;
			clock-frequency = <25000000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart2: uart@120000 {
			device_type = "serial";
			compatible = "snps,dw-apb-uart";
			reg = <0x00120000 0x1000>;
			reg-shift = <2>;
			clock-frequency = <25000000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		uart3: uart@130000 {
			device_type = "serial";
			compatible = "snps,dw-apb-uart";
			reg = <0x00130000 0x1000>;
			reg-shift = <2>;
			clock-frequency = <25000000>;
			interrupt-parent = <&gic>;
			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		ssp0: spi@180000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x00180000 0x1000>;
			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
			clock-names = "spiclk", "apb_pclk";
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		ssp1: spi@190000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x00190000 0x1000>;
			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
			clock-names = "spiclk", "apb_pclk";
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		hwrng: hwrng@220000 {
			compatible = "brcm,iproc-rng200";
			reg = <0x00220000 0x28>;
		};

		dma0: dma@310000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x00310000 0x1000>;
			interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
			#dma-cells = <1>;
			#dma-channels = <8>;
			#dma-requests = <32>;
			clocks = <&hsls_div2_clk>;
			clock-names = "apb_pclk";
			iommus = <&smmu 0x6000 0x0000>;
		};

		enet: ethernet@340000{
			compatible = "brcm,amac";
			reg = <0x00340000 0x1000>;
			reg-names = "amac_base";
			dma-coherent;
			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
			status= "disabled";
		};

		nand: nand@360000 {
			compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
			reg = <0x00360000 0x600>,
			      <0x0050a408 0x600>,
			      <0x00360f00 0x20>;
			reg-names = "nand", "iproc-idm", "iproc-ext";
			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			brcm,nand-has-wp;
			status = "disabled";
		};

		sdio0: sdhci@3f1000 {
			compatible = "brcm,sdhci-iproc";
			reg = <0x003f1000 0x100>;
			interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
			bus-width = <8>;
			clocks = <&sdio0_clk>;
			iommus = <&smmu 0x6002 0x0000>;
			status = "disabled";
		};

		sdio1: sdhci@3f2000 {
			compatible = "brcm,sdhci-iproc";
			reg = <0x003f2000 0x100>;
			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
			bus-width = <8>;
			clocks = <&sdio1_clk>;
			iommus = <&smmu 0x6003 0x0000>;
			status = "disabled";
		};
	};
};
Commit	Line	Data
d4b4aba6 AP	1	/*
	2	* BSD LICENSE
	3	*
	4	* Copyright(c) 2015-2017 Broadcom. All rights reserved.
	5	*
	6	* Redistribution and use in source and binary forms, with or without
	7	* modification, are permitted provided that the following conditions
	8	* are met:
	9	*
	10	* * Redistributions of source code must retain the above copyright
	11	* notice, this list of conditions and the following disclaimer.
	12	* * Redistributions in binary form must reproduce the above copyright
	13	* notice, this list of conditions and the following disclaimer in
	14	* the documentation and/or other materials provided with the
	15	* distribution.
	16	* * Neither the name of Broadcom nor the names of its
	17	* contributors may be used to endorse or promote products derived
	18	* from this software without specific prior written permission.
	19	*
	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	21	* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	22	* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	23	* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	24	* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	25	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	26	* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	27	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	28	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	29	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	30	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	31	*/
	32
	33	#include <dt-bindings/interrupt-controller/arm-gic.h>
	34
	35	/ {
	36	compatible = "brcm,stingray";
	37	interrupt-parent = <&gic>;
	38	#address-cells = <2>;
	39	#size-cells = <2>;
	40
	41	cpus {
	42	#address-cells = <2>;
	43	#size-cells = <0>;
	44
d8bcaabe	45	cpu@0 {
d4b4aba6 AP	46	device_type = "cpu";
	47	compatible = "arm,cortex-a72", "arm,armv8";
	48	reg = <0x0 0x0>;
	49	enable-method = "psci";
	50	next-level-cache = <&CLUSTER0_L2>;
	51	};
	52
d8bcaabe	53	cpu@1 {
d4b4aba6 AP	54	device_type = "cpu";
	55	compatible = "arm,cortex-a72", "arm,armv8";
	56	reg = <0x0 0x1>;
	57	enable-method = "psci";
	58	next-level-cache = <&CLUSTER0_L2>;
	59	};
	60
	61	cpu@100 {
	62	device_type = "cpu";
	63	compatible = "arm,cortex-a72", "arm,armv8";
	64	reg = <0x0 0x100>;
	65	enable-method = "psci";
	66	next-level-cache = <&CLUSTER1_L2>;
	67	};
	68
	69	cpu@101 {
	70	device_type = "cpu";
	71	compatible = "arm,cortex-a72", "arm,armv8";
	72	reg = <0x0 0x101>;
	73	enable-method = "psci";
	74	next-level-cache = <&CLUSTER1_L2>;
	75	};
	76
	77	cpu@200 {
	78	device_type = "cpu";
	79	compatible = "arm,cortex-a72", "arm,armv8";
	80	reg = <0x0 0x200>;
	81	enable-method = "psci";
	82	next-level-cache = <&CLUSTER2_L2>;
	83	};
	84
	85	cpu@201 {
	86	device_type = "cpu";
	87	compatible = "arm,cortex-a72", "arm,armv8";
	88	reg = <0x0 0x201>;
	89	enable-method = "psci";
	90	next-level-cache = <&CLUSTER2_L2>;
	91	};
	92
	93	cpu@300 {
	94	device_type = "cpu";
	95	compatible = "arm,cortex-a72", "arm,armv8";
	96	reg = <0x0 0x300>;
	97	enable-method = "psci";
	98	next-level-cache = <&CLUSTER3_L2>;
	99	};
	100
	101	cpu@301 {
	102	device_type = "cpu";
	103	compatible = "arm,cortex-a72", "arm,armv8";
	104	reg = <0x0 0x301>;
	105	enable-method = "psci";
	106	next-level-cache = <&CLUSTER3_L2>;
	107	};
	108
d8bcaabe	109	CLUSTER0_L2: l2-cache@0 {
d4b4aba6 AP	110	compatible = "cache";
	111	};
	112
	113	CLUSTER1_L2: l2-cache@100 {
	114	compatible = "cache";
	115	};
	116
	117	CLUSTER2_L2: l2-cache@200 {
	118	compatible = "cache";
	119	};
	120
	121	CLUSTER3_L2: l2-cache@300 {
	122	compatible = "cache";
	123	};
	124	};
	125
	126	memory: memory@80000000 {
	127	device_type = "memory";
	128	reg = <0x00000000 0x80000000 0 0x40000000>;
	129	};
	130
	131	psci {
	132	compatible = "arm,psci-0.2";
	133	method = "smc";
	134	};
	135
	136	pmu {
	137	compatible = "arm,armv8-pmuv3";
	138	interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	139	};
	140
	141	timer {
	142	compatible = "arm,armv8-timer";
	143	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
	144	<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
	145	<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
	146	<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	147	};
	148
133de204 RJ	149	mhb: syscon@60401000 {
	150	compatible = "brcm,sr-mhb", "syscon";
	151	reg = <0 0x60401000 0 0x38c>;
	152	};
	153
d4b4aba6 AP	154	scr {
	155	compatible = "simple-bus";
	156	#address-cells = <1>;
	157	#size-cells = <1>;
	158	ranges = <0x0 0x0 0x61000000 0x05000000>;
	159
d8bcaabe	160	ccn: ccn@0 {
5ace3533 VM	161	compatible = "arm,ccn-502";
	162	reg = <0x00000000 0x900000>;
	163	interrupts = <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
	164	};
	165
d8bcaabe	166	gic: interrupt-controller@2c00000 {
d4b4aba6 AP	167	compatible = "arm,gic-v3";
	168	#interrupt-cells = <3>;
	169	#address-cells = <1>;
	170	#size-cells = <1>;
	171	ranges;
	172	interrupt-controller;
	173	reg = <0x02c00000 0x010000>, /* GICD */
	174	<0x02e00000 0x600000>; /* GICR */
	175	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	176
	177	gic_its: gic-its@63c20000 {
	178	compatible = "arm,gic-v3-its";
	179	msi-controller;
	180	#msi-cells = <1>;
	181	reg = <0x02c20000 0x10000>;
	182	};
	183	};
	184
d8bcaabe	185	smmu: mmu@3000000 {
d4b4aba6 AP	186	compatible = "arm,mmu-500";
	187	reg = <0x03000000 0x80000>;
	188	#global-interrupts = <1>;
	189	interrupts = <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>,
	190	<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
	191	<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
	192	<GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
	193	<GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
	194	<GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
	195	<GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>,
	196	<GIC_SPI 717 IRQ_TYPE_LEVEL_HIGH>,
	197	<GIC_SPI 718 IRQ_TYPE_LEVEL_HIGH>,
	198	<GIC_SPI 719 IRQ_TYPE_LEVEL_HIGH>,
	199	<GIC_SPI 720 IRQ_TYPE_LEVEL_HIGH>,
	200	<GIC_SPI 721 IRQ_TYPE_LEVEL_HIGH>,
	201	<GIC_SPI 722 IRQ_TYPE_LEVEL_HIGH>,
	202	<GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH>,
	203	<GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH>,
	204	<GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH>,
	205	<GIC_SPI 726 IRQ_TYPE_LEVEL_HIGH>,
	206	<GIC_SPI 727 IRQ_TYPE_LEVEL_HIGH>,
	207	<GIC_SPI 728 IRQ_TYPE_LEVEL_HIGH>,
	208	<GIC_SPI 729 IRQ_TYPE_LEVEL_HIGH>,
	209	<GIC_SPI 730 IRQ_TYPE_LEVEL_HIGH>,
	210	<GIC_SPI 731 IRQ_TYPE_LEVEL_HIGH>,
	211	<GIC_SPI 732 IRQ_TYPE_LEVEL_HIGH>,
	212	<GIC_SPI 733 IRQ_TYPE_LEVEL_HIGH>,
	213	<GIC_SPI 734 IRQ_TYPE_LEVEL_HIGH>,
	214	<GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>,
	215	<GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>,
	216	<GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>,
	217	<GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>,
	218	<GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>,
	219	<GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>,
	220	<GIC_SPI 741 IRQ_TYPE_LEVEL_HIGH>,
	221	<GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>,
	222	<GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>,
	223	<GIC_SPI 744 IRQ_TYPE_LEVEL_HIGH>,
	224	<GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>,
	225	<GIC_SPI 746 IRQ_TYPE_LEVEL_HIGH>,
	226	<GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>,
	227	<GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>,
	228	<GIC_SPI 749 IRQ_TYPE_LEVEL_HIGH>,
	229	<GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>,
	230	<GIC_SPI 751 IRQ_TYPE_LEVEL_HIGH>,
	231	<GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>,
	232	<GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>,
	233	<GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>,
	234	<GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH>,
	235	<GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH>,
	236	<GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH>,
	237	<GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH>,
	238	<GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH>,
	239	<GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH>,
	240	<GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>,
	241	<GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH>,
	242	<GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH>,
	243	<GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>,
	244	<GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>,
	245	<GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>,
	246	<GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>,
	247	<GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>,
	248	<GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
	249	<GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>,
250	<GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>,
251	<GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>,
252	<GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
253	<GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>;
254	#iommu-cells = <2>;
255	};
256	};
257
73da8f97 ST	258	crmu: crmu {
	259	compatible = "simple-bus";
	260	#address-cells = <1>;
	261	#size-cells = <1>;
	262	ranges = <0x0 0x0 0x66400000 0x100000>;
	263
	264	#include "stingray-clock.dtsi"
2fa9e9e2	265
8dd970a2 SB	266	otp: otp@1c400 {
	267	compatible = "brcm,ocotp-v2";
	268	reg = <0x0001c400 0x68>;
	269	brcm,ocotp-size = <2048>;
	270	status = "okay";
	271	};
	272
133de204 RJ	273	cdru: syscon@1d000 {
	274	compatible = "brcm,sr-cdru", "syscon";
	275	reg = <0x0001d000 0x400>;
	276	};
	277
d8bcaabe	278	gpio_crmu: gpio@24800 {
2fa9e9e2 PK	279	compatible = "brcm,iproc-gpio";
	280	reg = <0x00024800 0x4c>;
	281	ngpios = <6>;
	282	#gpio-cells = <2>;
	283	gpio-controller;
	284	};
73da8f97 ST	285	};
73da8f97 ST	286
c6e95598	287	#include "stingray-fs4.dtsi"
344a2e51	288	#include "stingray-sata.dtsi"
133de204	289	#include "stingray-pcie.dtsi"
344a2e51	290
d4b4aba6 AP	291	hsls {
	292	compatible = "simple-bus";
	293	#address-cells = <1>;
	294	#size-cells = <1>;
	295	ranges = <0x0 0x0 0x68900000 0x17700000>;
	296
8aa428cc PK	297	#include "stingray-pinctrl.dtsi"
8aa428cc PK	298
18b872d8	299	mdio_mux_iproc: mdio-mux@20000 {
fd898f75	300	compatible = "brcm,mdio-mux-iproc";
18b872d8	301	reg = <0x00020000 0x250>;
fd898f75 SM	302	#address-cells = <1>;
	303	#size-cells = <0>;
	304
	305	mdio@0 { /* PCIe serdes */
	306	reg = <0x0>;
	307	#address-cells = <1>;
	308	#size-cells = <0>;
	309	};
	310
	311	mdio@2 { /* SATA */
	312	reg = <0x2>;
	313	#address-cells = <1>;
	314	#size-cells = <0>;
	315	};
	316
	317	mdio@3 { /* USB */
	318	reg = <0x3>;
	319	#address-cells = <1>;
	320	#size-cells = <0>;
	321	};
	322
	323	mdio@10 { /* RGMII */
	324	reg = <0x10>;
	325	#address-cells = <1>;
	326	#size-cells = <0>;
	327	};
	328	};
	329
d8bcaabe	330	pwm: pwm@10000 {
552df263 SM	331	compatible = "brcm,iproc-pwm";
	332	reg = <0x00010000 0x1000>;
	333	clocks = <&crmu_ref25m>;
	334	#pwm-cells = <3>;
	335	status = "disabled";
	336	};
	337
d8bcaabe	338	timer0: timer@30000 {
567b3b0a AP	339	compatible = "arm,sp804", "arm,primecell";
	340	reg = <0x00030000 0x1000>;
	341	interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
	342	clocks = <&hsls_25m_div2_clk>,
	343	<&hsls_25m_div2_clk>,
	344	<&hsls_div4_clk>;
	345	clock-names = "timer1", "timer2", "apb_pclk";
	346	status = "disabled";
	347	};
	348
d8bcaabe	349	timer1: timer@40000 {
567b3b0a AP	350	compatible = "arm,sp804", "arm,primecell";
	351	reg = <0x00040000 0x1000>;
	352	interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
	353	clocks = <&hsls_25m_div2_clk>,
	354	<&hsls_25m_div2_clk>,
	355	<&hsls_div4_clk>;
	356	clock-names = "timer1", "timer2", "apb_pclk";
	357	};
	358
d8bcaabe	359	timer2: timer@50000 {
567b3b0a AP	360	compatible = "arm,sp804", "arm,primecell";
	361	reg = <0x00050000 0x1000>;
	362	interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
	363	clocks = <&hsls_25m_div2_clk>,
	364	<&hsls_25m_div2_clk>,
	365	<&hsls_div4_clk>;
	366	clock-names = "timer1", "timer2", "apb_pclk";
	367	status = "disabled";
	368	};
	369
d8bcaabe	370	timer3: timer@60000 {
567b3b0a AP	371	compatible = "arm,sp804", "arm,primecell";
	372	reg = <0x00060000 0x1000>;
	373	interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
	374	clocks = <&hsls_25m_div2_clk>,
	375	<&hsls_25m_div2_clk>,
	376	<&hsls_div4_clk>;
	377	clock-names = "timer1", "timer2", "apb_pclk";
	378	status = "disabled";
	379	};
	380
d8bcaabe	381	timer4: timer@70000 {
567b3b0a AP	382	compatible = "arm,sp804", "arm,primecell";
	383	reg = <0x00070000 0x1000>;
	384	interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
	385	clocks = <&hsls_25m_div2_clk>,
	386	<&hsls_25m_div2_clk>,
	387	<&hsls_div4_clk>;
	388	clock-names = "timer1", "timer2", "apb_pclk";
	389	status = "disabled";
	390	};
	391
d8bcaabe	392	timer5: timer@80000 {
567b3b0a AP	393	compatible = "arm,sp804", "arm,primecell";
	394	reg = <0x00080000 0x1000>;
	395	interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	396	clocks = <&hsls_25m_div2_clk>,
	397	<&hsls_25m_div2_clk>,
	398	<&hsls_div4_clk>;
	399	clock-names = "timer1", "timer2", "apb_pclk";
	400	status = "disabled";
	401	};
	402
d8bcaabe	403	timer6: timer@90000 {
567b3b0a AP	404	compatible = "arm,sp804", "arm,primecell";
	405	reg = <0x00090000 0x1000>;
	406	interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
	407	clocks = <&hsls_25m_div2_clk>,
	408	<&hsls_25m_div2_clk>,
	409	<&hsls_div4_clk>;
	410	clock-names = "timer1", "timer2", "apb_pclk";
	411	status = "disabled";
	412	};
	413
d8bcaabe	414	timer7: timer@a0000 {
567b3b0a AP	415	compatible = "arm,sp804", "arm,primecell";
	416	reg = <0x000a0000 0x1000>;
	417	interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
	418	clocks = <&hsls_25m_div2_clk>,
	419	<&hsls_25m_div2_clk>,
	420	<&hsls_div4_clk>;
	421	clock-names = "timer1", "timer2", "apb_pclk";
	422	status = "disabled";
	423	};
	424
d8bcaabe	425	i2c0: i2c@b0000 {
1256ea18 OP	426	compatible = "brcm,iproc-i2c";
	427	reg = <0x000b0000 0x100>;
	428	#address-cells = <1>;
	429	#size-cells = <0>;
75af23c4	430	interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
1256ea18 OP	431	clock-frequency = <100000>;
	432	status = "disabled";
	433	};
	434
d8bcaabe	435	wdt0: watchdog@c0000 {
0dc454ee AP	436	compatible = "arm,sp805", "arm,primecell";
	437	reg = <0x000c0000 0x1000>;
	438	interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
	439	clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>;
	440	clock-names = "wdogclk", "apb_pclk";
71e962a0	441	timeout-sec = <60>;
0dc454ee AP	442	};
0dc454ee AP	443
d8bcaabe	444	gpio_hsls: gpio@d0000 {
2fa9e9e2 PK	445	compatible = "brcm,iproc-gpio";
	446	reg = <0x000d0000 0x864>;
	447	ngpios = <151>;
	448	#gpio-cells = <2>;
	449	gpio-controller;
	450	interrupt-controller;
	451	interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
	452	gpio-ranges = <&pinmux 0 0 16>,
	453	<&pinmux 16 71 2>,
	454	<&pinmux 18 131 8>,
	455	<&pinmux 26 83 6>,
	456	<&pinmux 32 123 4>,
	457	<&pinmux 36 43 24>,
	458	<&pinmux 60 89 2>,
	459	<&pinmux 62 73 4>,
	460	<&pinmux 66 95 28>,
	461	<&pinmux 94 127 4>,
	462	<&pinmux 98 139 10>,
	463	<&pinmux 108 16 27>,
	464	<&pinmux 135 77 6>,
	465	<&pinmux 141 67 4>,
	466	<&pinmux 145 149 6>,
	467	<&pinmux 151 91 4>;
	468	};
	469
d8bcaabe	470	i2c1: i2c@e0000 {
1256ea18 OP	471	compatible = "brcm,iproc-i2c";
	472	reg = <0x000e0000 0x100>;
	473	#address-cells = <1>;
	474	#size-cells = <0>;
75af23c4	475	interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
1256ea18 OP	476	clock-frequency = <100000>;
	477	status = "disabled";
	478	};
	479
d8bcaabe	480	uart0: uart@100000 {
d4b4aba6 AP	481	device_type = "serial";
	482	compatible = "snps,dw-apb-uart";
	483	reg = <0x00100000 0x1000>;
	484	reg-shift = <2>;
	485	clock-frequency = <25000000>;
	486	interrupt-parent = <&gic>;
	487	interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
	488	status = "disabled";
	489	};
	490
d8bcaabe	491	uart1: uart@110000 {
d4b4aba6 AP	492	device_type = "serial";
	493	compatible = "snps,dw-apb-uart";
	494	reg = <0x00110000 0x1000>;
	495	reg-shift = <2>;
	496	clock-frequency = <25000000>;
	497	interrupt-parent = <&gic>;
	498	interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	499	status = "disabled";
	500	};
	501
d8bcaabe	502	uart2: uart@120000 {
d4b4aba6 AP	503	device_type = "serial";
	504	compatible = "snps,dw-apb-uart";
	505	reg = <0x00120000 0x1000>;
	506	reg-shift = <2>;
	507	clock-frequency = <25000000>;
	508	interrupt-parent = <&gic>;
	509	interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
	510	status = "disabled";
	511	};
	512
d8bcaabe	513	uart3: uart@130000 {
d4b4aba6 AP	514	device_type = "serial";
	515	compatible = "snps,dw-apb-uart";
	516	reg = <0x00130000 0x1000>;
	517	reg-shift = <2>;
	518	clock-frequency = <25000000>;
	519	interrupt-parent = <&gic>;
	520	interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
	521	status = "disabled";
	522	};
	523
7cdbe45d	524	ssp0: spi@180000 {
0dc454ee AP	525	compatible = "arm,pl022", "arm,primecell";
	526	reg = <0x00180000 0x1000>;
	527	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
	528	clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
	529	clock-names = "spiclk", "apb_pclk";
	530	num-cs = <1>;
	531	#address-cells = <1>;
	532	#size-cells = <0>;
	533	status = "disabled";
	534	};
	535
7cdbe45d	536	ssp1: spi@190000 {
0dc454ee AP	537	compatible = "arm,pl022", "arm,primecell";
	538	reg = <0x00190000 0x1000>;
	539	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
	540	clocks = <&hsls_div2_clk>, <&hsls_div2_clk>;
	541	clock-names = "spiclk", "apb_pclk";
	542	num-cs = <1>;
	543	#address-cells = <1>;
	544	#size-cells = <0>;
	545	status = "disabled";
	546	};
	547
d8bcaabe	548	hwrng: hwrng@220000 {
d4b4aba6 AP	549	compatible = "brcm,iproc-rng200";
	550	reg = <0x00220000 0x28>;
	551	};
0f67ae37	552
d8bcaabe	553	dma0: dma@310000 {
0dc454ee AP	554	compatible = "arm,pl330", "arm,primecell";
	555	reg = <0x00310000 0x1000>;
	556	interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
	557	<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
	558	<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
	559	<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
	560	<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
	561	<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
	562	<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
	563	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
	564	<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
	565	#dma-cells = <1>;
	566	#dma-channels = <8>;
	567	#dma-requests = <32>;
	568	clocks = <&hsls_div2_clk>;
	569	clock-names = "apb_pclk";
	570	iommus = <&smmu 0x6000 0x0000>;
	571	};
	572
d8bcaabe	573	enet: ethernet@340000{
80e2cbc1 AS	574	compatible = "brcm,amac";
	575	reg = <0x00340000 0x1000>;
	576	reg-names = "amac_base";
	577	dma-coherent;
	578	interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
	579	status= "disabled";
	580	};
	581
d8bcaabe	582	nand: nand@360000 {
0f67ae37 PK	583	compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
	584	reg = <0x00360000 0x600>,
	585	<0x0050a408 0x600>,
	586	<0x00360f00 0x20>;
	587	reg-names = "nand", "iproc-idm", "iproc-ext";
	588	interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
	589	#address-cells = <1>;
	590	#size-cells = <0>;
	591	brcm,nand-has-wp;
	592	status = "disabled";
	593	};
552df263	594
d8bcaabe	595	sdio0: sdhci@3f1000 {
552df263 SM	596	compatible = "brcm,sdhci-iproc";
	597	reg = <0x003f1000 0x100>;
	598	interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
	599	bus-width = <8>;
	600	clocks = <&sdio0_clk>;
	601	iommus = <&smmu 0x6002 0x0000>;
	602	status = "disabled";
	603	};
	604
d8bcaabe	605	sdio1: sdhci@3f2000 {
552df263 SM	606	compatible = "brcm,sdhci-iproc";
	607	reg = <0x003f2000 0x100>;
	608	interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
	609	bus-width = <8>;
	610	clocks = <&sdio1_clk>;
	611	iommus = <&smmu 0x6003 0x0000>;
	612	status = "disabled";
	613	};
d4b4aba6 AP	614	};
d4b4aba6 AP	615	};