[mirror_ubuntu-hirsute-kernel.git] / arch / arm64 / boot / dts / exynos / exynos5433-tm2.dts

// SPDX-License-Identifier: GPL-2.0
/*
 * SAMSUNG Exynos5433 TM2 board device tree source
 *
 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
 *
 * Device tree source file for Samsung's TM2 board which is based on
 * Samsung Exynos5433 SoC.
 */

#include "exynos5433-tm2-common.dtsi"

/ {
	model = "Samsung TM2 board";
	compatible = "samsung,tm2", "samsung,exynos5433";
};

&cmu_disp {
	/*
	 * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned
	 * clocks properties for DISP CMU for each board to keep them together
	 * for easier review and maintenance.
	 */
	assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
			  <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
			  <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
			  <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
			  <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
			  <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
			  <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
			  <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
			  <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
			  <&cmu_disp CLK_MOUT_DISP_PLL>,
			  <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
			  <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
			  <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>,
			  <&cmu_disp CLK_MOUT_SCLK_DSD_USER>;
	assigned-clock-parents = <0>, <0>,
				 <&cmu_mif CLK_ACLK_DISP_333>,
				 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
				 <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
				 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
				 <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
				 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
				 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
				 <&cmu_disp CLK_FOUT_DISP_PLL>,
				 <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
				 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
				 <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
				 <&cmu_mif CLK_SCLK_DSD_DISP>;
	assigned-clock-rates = <250000000>, <400000000>;
};

&dsi {
	panel@0 {
		compatible = "samsung,s6e3ha2";
		reg = <0>;
		vdd3-supply = <&ldo27_reg>;
		vci-supply = <&ldo28_reg>;
		reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>;
		enable-gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>;
	};
};

&hsi2c_9 {
	status = "okay";

	touchkey@20 {
		compatible = "cypress,tm2-touchkey";
		reg = <0x20>;
		interrupt-parent = <&gpa3>;
		interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
		vcc-supply = <&ldo32_reg>;
		vdd-supply = <&ldo33_reg>;
	};
};

&ldo31_reg {
	regulator-name = "TSP_VDD_1.85V_AP";
	regulator-min-microvolt = <1850000>;
	regulator-max-microvolt = <1850000>;
};

&ldo38_reg {
	regulator-name = "VCC_3.0V_MOTOR_AP";
	regulator-min-microvolt = <3000000>;
	regulator-max-microvolt = <3000000>;
};

&stmfts {
	touchscreen-size-x = <1439>;
	touchscreen-size-y = <2559>;
};
Commit	Line	Data
45fef752	1	// SPDX-License-Identifier: GPL-2.0
01e5d235 CC	2	/*
	3	* SAMSUNG Exynos5433 TM2 board device tree source
	4	*
	5	* Copyright (c) 2016 Samsung Electronics Co., Ltd.
	6	*
	7	* Device tree source file for Samsung's TM2 board which is based on
	8	* Samsung Exynos5433 SoC.
01e5d235 CC	9	*/
01e5d235 CC	10
83089bb9	11	#include "exynos5433-tm2-common.dtsi"
01e5d235 CC	12
	13	/ {
	14	model = "Samsung TM2 board";
	15	compatible = "samsung,tm2", "samsung,exynos5433";
01e5d235 CC	16	};
01e5d235 CC	17
d1160ebf MS	18	&cmu_disp {
	19	/*
	20	* TM2 and TM2e differ only by DISP_PLL rate, but define all assigned
	21	* clocks properties for DISP CMU for each board to keep them together
	22	* for easier review and maintenance.
	23	*/
	24	assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
	25	<&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
	26	<&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
	27	<&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
	28	<&cmu_disp CLK_MOUT_SCLK_DSIM0>,
	29	<&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
	30	<&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
	31	<&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
	32	<&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
	33	<&cmu_disp CLK_MOUT_DISP_PLL>,
	34	<&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
	35	<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
7698ffaf AH	36	<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>,
7698ffaf AH	37	<&cmu_disp CLK_MOUT_SCLK_DSD_USER>;
d1160ebf MS	38	assigned-clock-parents = <0>, <0>,
	39	<&cmu_mif CLK_ACLK_DISP_333>,
	40	<&cmu_mif CLK_SCLK_DSIM0_DISP>,
	41	<&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
	42	<&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
	43	<&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
	44	<&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
	45	<&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
	46	<&cmu_disp CLK_FOUT_DISP_PLL>,
	47	<&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
	48	<&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
7698ffaf AH	49	<&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
7698ffaf AH	50	<&cmu_mif CLK_SCLK_DSD_DISP>;
d1160ebf MS	51	assigned-clock-rates = <250000000>, <400000000>;
	52	};
	53
6a611d14 VK	54	&dsi {
	55	panel@0 {
	56	compatible = "samsung,s6e3ha2";
	57	reg = <0>;
	58	vdd3-supply = <&ldo27_reg>;
	59	vci-supply = <&ldo28_reg>;
	60	reset-gpios = <&gpg0 0 GPIO_ACTIVE_LOW>;
	61	enable-gpios = <&gpf1 5 GPIO_ACTIVE_HIGH>;
6a611d14 VK	62	};
	63	};
	64
5205761d JL	65	&hsi2c_9 {
	66	status = "okay";
	67
	68	touchkey@20 {
	69	compatible = "cypress,tm2-touchkey";
	70	reg = <0x20>;
	71	interrupt-parent = <&gpa3>;
	72	interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
	73	vcc-supply = <&ldo32_reg>;
	74	vdd-supply = <&ldo33_reg>;
	75	};
	76	};
	77
83089bb9 AS	78	&ldo31_reg {
	79	regulator-name = "TSP_VDD_1.85V_AP";
	80	regulator-min-microvolt = <1850000>;
	81	regulator-max-microvolt = <1850000>;
01e5d235 CC	82	};
01e5d235 CC	83
83089bb9 AS	84	&ldo38_reg {
	85	regulator-name = "VCC_3.0V_MOTOR_AP";
	86	regulator-min-microvolt = <3000000>;
	87	regulator-max-microvolt = <3000000>;
01e5d235	88	};
6a611d14 VK	89
	90	&stmfts {
	91	touchscreen-size-x = <1439>;
	92	touchscreen-size-y = <2559>;
	93	};