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1 | /* |
2 | * SAMSUNG Exynos5433 TM2E board device tree source | |
3 | * | |
4 | * Copyright (c) 2016 Samsung Electronics Co., Ltd. | |
5 | * | |
6 | * Device tree source file for Samsung's TM2E(TM2 EDGE) board which is based on | |
7 | * Samsung Exynos5433 SoC. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
83089bb9 | 14 | #include "exynos5433-tm2-common.dtsi" |
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15 | |
16 | / { | |
17 | model = "Samsung TM2E board"; | |
18 | compatible = "samsung,tm2e", "samsung,exynos5433"; | |
19 | }; | |
20 | ||
d1160ebf MS |
21 | &cmu_disp { |
22 | /* | |
23 | * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned | |
24 | * clocks properties for DISP CMU for each board to keep them together | |
25 | * for easier review and maintenance. | |
26 | */ | |
27 | assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>, | |
28 | <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>, | |
29 | <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>, | |
30 | <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, | |
31 | <&cmu_disp CLK_MOUT_SCLK_DSIM0>, | |
32 | <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, | |
33 | <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>, | |
34 | <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>, | |
35 | <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>, | |
36 | <&cmu_disp CLK_MOUT_DISP_PLL>, | |
37 | <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>, | |
38 | <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>, | |
39 | <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>; | |
40 | assigned-clock-parents = <0>, <0>, | |
41 | <&cmu_mif CLK_ACLK_DISP_333>, | |
42 | <&cmu_mif CLK_SCLK_DSIM0_DISP>, | |
43 | <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>, | |
44 | <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>, | |
45 | <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>, | |
46 | <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>, | |
47 | <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>, | |
48 | <&cmu_disp CLK_FOUT_DISP_PLL>, | |
49 | <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>, | |
50 | <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>, | |
51 | <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>; | |
52 | assigned-clock-rates = <278000000>, <400000000>; | |
53 | }; | |
54 | ||
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55 | &ldo31_reg { |
56 | regulator-name = "TSP_VDD_1.8V_AP"; | |
57 | regulator-min-microvolt = <1800000>; | |
58 | regulator-max-microvolt = <1800000>; | |
59 | }; | |
60 | ||
61 | &ldo38_reg { | |
62 | regulator-name = "VCC_3.3V_MOTOR_AP"; | |
63 | regulator-min-microvolt = <3300000>; | |
64 | regulator-max-microvolt = <3300000>; | |
65 | }; |