[mirror_ubuntu-hirsute-kernel.git] / arch / arm64 / boot / dts / freescale / fsl-ls1028a.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for NXP Layerscape-1028A family SoC.
 *
 * Copyright 2018 NXP
 *
 * Harninder Rai <harninder.rai@nxp.com>
 *
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>

/ {
	compatible = "fsl,ls1028a";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x0>;
			enable-method = "psci";
			clocks = <&clockgen 1 0>;
			next-level-cache = <&l2>;
			cpu-idle-states = <&CPU_PH20>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a72";
			reg = <0x1>;
			enable-method = "psci";
			clocks = <&clockgen 1 0>;
			next-level-cache = <&l2>;
			cpu-idle-states = <&CPU_PH20>;
		};

		l2: l2-cache {
			compatible = "cache";
		};
	};

	idle-states {
		/*
		 * PSCI node is not added default, U-boot will add missing
		 * parts if it determines to use PSCI.
		 */
		entry-method = "arm,psci";

		CPU_PH20: cpu-ph20 {
			compatible = "arm,idle-state";
			idle-state-name = "PH20";
			arm,psci-suspend-param = <0x00010000>;
			entry-latency-us = <1000>;
			exit-latency-us = <1000>;
			min-residency-us = <3000>;
		};
	};

	sysclk: clock-sysclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
		clock-output-names = "sysclk";
	};

	reboot {
		compatible ="syscon-reboot";
		regmap = <&dcfg>;
		offset = <0xb0>;
		mask = <0x02>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
					  IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu {
		compatible = "arm,cortex-a72-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	gic: interrupt-controller@6000000 {
		compatible= "arm,gic-v3";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */
			<0x0 0x06040000 0 0x40000>; /* GIC Redistributor */
		#interrupt-cells= <3>;
		interrupt-controller;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
					 IRQ_TYPE_LEVEL_LOW)>;
		its: gic-its@6020000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */
		};
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		ddr: memory-controller@1080000 {
			compatible = "fsl,qoriq-memory-controller";
			reg = <0x0 0x1080000 0x0 0x1000>;
			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
			big-endian;
		};

		dcfg: syscon@1e00000 {
			compatible = "fsl,ls1028a-dcfg", "syscon";
			reg = <0x0 0x1e00000 0x0 0x10000>;
			big-endian;
		};

		scfg: syscon@1fc0000 {
			compatible = "fsl,ls1028a-scfg", "syscon";
			reg = <0x0 0x1fc0000 0x0 0x10000>;
			big-endian;
		};

		clockgen: clock-controller@1300000 {
			compatible = "fsl,ls1028a-clockgen";
			reg = <0x0 0x1300000 0x0 0xa0000>;
			#clock-cells = <2>;
			clocks = <&sysclk>;
		};

		i2c0: i2c@2000000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2000000 0x0 0x10000>;
			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			status = "disabled";
		};

		i2c1: i2c@2010000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2010000 0x0 0x10000>;
			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			status = "disabled";
		};

		i2c2: i2c@2020000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2020000 0x0 0x10000>;
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			status = "disabled";
		};

		i2c3: i2c@2030000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2030000 0x0 0x10000>;
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			status = "disabled";
		};

		i2c4: i2c@2040000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2040000 0x0 0x10000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			status = "disabled";
		};

		i2c5: i2c@2050000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2050000 0x0 0x10000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			status = "disabled";
		};

		i2c6: i2c@2060000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2060000 0x0 0x10000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			status = "disabled";
		};

		i2c7: i2c@2070000 {
			compatible = "fsl,vf610-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x0 0x2070000 0x0 0x10000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			status = "disabled";
		};

		duart0: serial@21c0500 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x00 0x21c0500 0x0 0x100>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			status = "disabled";
		};

		duart1: serial@21c0600 {
			compatible = "fsl,ns16550", "ns16550a";
			reg = <0x00 0x21c0600 0x0 0x100>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			status = "disabled";
		};

		edma0: dma-controller@22c0000 {
			#dma-cells = <2>;
			compatible = "fsl,vf610-edma";
			reg = <0x0 0x22c0000 0x0 0x10000>,
			      <0x0 0x22d0000 0x0 0x10000>,
			      <0x0 0x22e0000 0x0 0x10000>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "edma-tx", "edma-err";
			dma-channels = <32>;
			clock-names = "dmamux0", "dmamux1";
			clocks = <&clockgen 4 1>,
				 <&clockgen 4 1>;
		};

		gpio1: gpio@2300000 {
			compatible = "fsl,qoriq-gpio";
			reg = <0x0 0x2300000 0x0 0x10000>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@2310000 {
			compatible = "fsl,qoriq-gpio";
			reg = <0x0 0x2310000 0x0 0x10000>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@2320000 {
			compatible = "fsl,qoriq-gpio";
			reg = <0x0 0x2320000 0x0 0x10000>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		wdog0: watchdog@23c0000 {
			compatible = "fsl,ls1028a-wdt", "fsl,imx21-wdt";
			reg = <0x0 0x23c0000 0x0 0x10000>;
			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			big-endian;
			status = "disabled";
		};

		sata: sata@3200000 {
			compatible = "fsl,ls1028a-ahci";
			reg = <0x0 0x3200000 0x0 0x10000>,
				<0x7 0x100520 0x0 0x4>;
			reg-names = "ahci", "sata-ecc";
			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>;
			status = "disabled";
		};

		smmu: iommu@5000000 {
			compatible = "arm,mmu-500";
			reg = <0 0x5000000 0 0x800000>;
			#global-interrupts = <8>;
			#iommu-cells = <1>;
			stream-match-mask = <0x7c00>;
			/* global secure fault */
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
			/* combined secure interrupt */
				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
			/* global non-secure fault */
				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
			/* combined non-secure interrupt */
				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
			/* performance counter interrupts 0-7 */
				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
			/* per context interrupt, 64 interrupts */
				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
		};

		sai1: audio-controller@f100000 {
			#sound-dai-cells = <0>;
			compatible = "fsl,vf610-sai";
			reg = <0x0 0xf100000 0x0 0x10000>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>, <&clockgen 4 1>,
				 <&clockgen 4 1>, <&clockgen 4 1>;
			clock-names = "bus", "mclk1", "mclk2", "mclk3";
			dma-names = "tx", "rx";
			dmas = <&edma0 1 4>,
			       <&edma0 1 3>;
			status = "disabled";
		};

		sai2: audio-controller@f110000 {
			#sound-dai-cells = <0>;
			compatible = "fsl,vf610-sai";
			reg = <0x0 0xf110000 0x0 0x10000>;
			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>, <&clockgen 4 1>,
				 <&clockgen 4 1>, <&clockgen 4 1>;
			clock-names = "bus", "mclk1", "mclk2", "mclk3";
			dma-names = "tx", "rx";
			dmas = <&edma0 1 6>,
			       <&edma0 1 5>;
			status = "disabled";
		};

		sai4: audio-controller@f130000 {
			#sound-dai-cells = <0>;
			compatible = "fsl,vf610-sai";
			reg = <0x0 0xf130000 0x0 0x10000>;
			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clockgen 4 1>, <&clockgen 4 1>,
				 <&clockgen 4 1>, <&clockgen 4 1>;
			clock-names = "bus", "mclk1", "mclk2", "mclk3";
			dma-names = "tx", "rx";
			dmas = <&edma0 1 10>,
			       <&edma0 1 9>;
			status = "disabled";
		};

		pcie@1f0000000 { /* Integrated Endpoint Root Complex */
			compatible = "pci-host-ecam-generic";
			reg = <0x01 0xf0000000 0x0 0x100000>;
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			msi-parent = <&its>;
			device_type = "pci";
			bus-range = <0x0 0x0>;
			dma-coherent;
			msi-map = <0 &its 0x17 0xe>;
			iommu-map = <0 &smmu 0x17 0xe>;
				  /* PF0-6 BAR0 - non-prefetchable memory */
			ranges = <0x82000000 0x0 0x00000000  0x1 0xf8000000  0x0 0x160000
				  /* PF0-6 BAR2 - prefetchable memory */
				  0xc2000000 0x0 0x00000000  0x1 0xf8160000  0x0 0x070000
				  /* PF0: VF0-1 BAR0 - non-prefetchable memory */
				  0x82000000 0x0 0x00000000  0x1 0xf81d0000  0x0 0x020000
				  /* PF0: VF0-1 BAR2 - prefetchable memory */
				  0xc2000000 0x0 0x00000000  0x1 0xf81f0000  0x0 0x020000
				  /* PF1: VF0-1 BAR0 - non-prefetchable memory */
				  0x82000000 0x0 0x00000000  0x1 0xf8210000  0x0 0x020000
				  /* PF1: VF0-1 BAR2 - prefetchable memory */
				  0xc2000000 0x0 0x00000000  0x1 0xf8230000  0x0 0x020000>;

			enetc_port0: ethernet@0,0 {
				compatible = "fsl,enetc";
				reg = <0x000000 0 0 0 0>;
			};
			enetc_port1: ethernet@0,1 {
				compatible = "fsl,enetc";
				reg = <0x000100 0 0 0 0>;
			};
		};
	};
};
Commit	Line	Data
8897f325 BU	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Device Tree Include file for NXP Layerscape-1028A family SoC.
	4	*
	5	* Copyright 2018 NXP
	6	*
	7	* Harninder Rai <harninder.rai@nxp.com>
	8	*
	9	*/
	10
	11	#include <dt-bindings/interrupt-controller/arm-gic.h>
	12	#include <dt-bindings/thermal/thermal.h>
	13
	14	/ {
	15	compatible = "fsl,ls1028a";
	16	interrupt-parent = <&gic>;
	17	#address-cells = <2>;
	18	#size-cells = <2>;
	19
	20	cpus {
	21	#address-cells = <1>;
	22	#size-cells = <0>;
	23
	24	cpu0: cpu@0 {
	25	device_type = "cpu";
	26	compatible = "arm,cortex-a72";
	27	reg = <0x0>;
	28	enable-method = "psci";
	29	clocks = <&clockgen 1 0>;
	30	next-level-cache = <&l2>;
	31	cpu-idle-states = <&CPU_PH20>;
	32	};
	33
	34	cpu1: cpu@1 {
	35	device_type = "cpu";
	36	compatible = "arm,cortex-a72";
	37	reg = <0x1>;
	38	enable-method = "psci";
	39	clocks = <&clockgen 1 0>;
	40	next-level-cache = <&l2>;
	41	cpu-idle-states = <&CPU_PH20>;
	42	};
	43
	44	l2: l2-cache {
	45	compatible = "cache";
	46	};
	47	};
	48
	49	idle-states {
	50	/*
	51	* PSCI node is not added default, U-boot will add missing
	52	* parts if it determines to use PSCI.
	53	*/
	54	entry-method = "arm,psci";
	55
	56	CPU_PH20: cpu-ph20 {
	57	compatible = "arm,idle-state";
	58	idle-state-name = "PH20";
	59	arm,psci-suspend-param = <0x00010000>;
	60	entry-latency-us = <1000>;
	61	exit-latency-us = <1000>;
	62	min-residency-us = <3000>;
	63	};
	64	};
65
66	sysclk: clock-sysclk {
67	compatible = "fixed-clock";
68	#clock-cells = <0>;
69	clock-frequency = <100000000>;
70	clock-output-names = "sysclk";
71	};
72
73	reboot {
74	compatible ="syscon-reboot";
75	regmap = <&dcfg>;
76	offset = <0xb0>;
77	mask = <0x02>;
78	};
79
80	timer {
81	compatible = "arm,armv8-timer";
82	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \|
83	IRQ_TYPE_LEVEL_LOW)>,
84	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \|
85	IRQ_TYPE_LEVEL_LOW)>,
86	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) \|
87	IRQ_TYPE_LEVEL_LOW)>,
88	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) \|
89	IRQ_TYPE_LEVEL_LOW)>;
90	};
91
b9eb314a AW	92	pmu {
	93	compatible = "arm,cortex-a72-pmu";
	94	interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	95	};
	96
8897f325 BU	97	gic: interrupt-controller@6000000 {
	98	compatible= "arm,gic-v3";
	99	#address-cells = <2>;
	100	#size-cells = <2>;
	101	ranges;
	102	reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */
	103	<0x0 0x06040000 0 0x40000>; /* GIC Redistributor */
	104	#interrupt-cells= <3>;
	105	interrupt-controller;
	106	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) \|
	107	IRQ_TYPE_LEVEL_LOW)>;
	108	its: gic-its@6020000 {
	109	compatible = "arm,gic-v3-its";
	110	msi-controller;
	111	reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */
	112	};
	113	};
	114
	115	soc: soc {
	116	compatible = "simple-bus";
	117	#address-cells = <2>;
	118	#size-cells = <2>;
	119	ranges;
	120
	121	ddr: memory-controller@1080000 {
	122	compatible = "fsl,qoriq-memory-controller";
	123	reg = <0x0 0x1080000 0x0 0x1000>;
	124	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
	125	big-endian;
	126	};
	127
	128	dcfg: syscon@1e00000 {
	129	compatible = "fsl,ls1028a-dcfg", "syscon";
	130	reg = <0x0 0x1e00000 0x0 0x10000>;
	131	big-endian;
	132	};
	133
	134	scfg: syscon@1fc0000 {
	135	compatible = "fsl,ls1028a-scfg", "syscon";
	136	reg = <0x0 0x1fc0000 0x0 0x10000>;
	137	big-endian;
	138	};
	139
	140	clockgen: clock-controller@1300000 {
	141	compatible = "fsl,ls1028a-clockgen";
	142	reg = <0x0 0x1300000 0x0 0xa0000>;
	143	#clock-cells = <2>;
	144	clocks = <&sysclk>;
	145	};
	146
	147	i2c0: i2c@2000000 {
	148	compatible = "fsl,vf610-i2c";
	149	#address-cells = <1>;
	150	#size-cells = <0>;
	151	reg = <0x0 0x2000000 0x0 0x10000>;
	152	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
	153	clocks = <&clockgen 4 1>;
	154	status = "disabled";
	155	};
	156
	157	i2c1: i2c@2010000 {
	158	compatible = "fsl,vf610-i2c";
	159	#address-cells = <1>;
	160	#size-cells = <0>;
161	reg = <0x0 0x2010000 0x0 0x10000>;
162	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
163	clocks = <&clockgen 4 1>;
164	status = "disabled";
165	};
166
167	i2c2: i2c@2020000 {
168	compatible = "fsl,vf610-i2c";
169	#address-cells = <1>;
170	#size-cells = <0>;
171	reg = <0x0 0x2020000 0x0 0x10000>;
172	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
173	clocks = <&clockgen 4 1>;
174	status = "disabled";
175	};
176
177	i2c3: i2c@2030000 {
178	compatible = "fsl,vf610-i2c";
179	#address-cells = <1>;
180	#size-cells = <0>;
181	reg = <0x0 0x2030000 0x0 0x10000>;
182	interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
183	clocks = <&clockgen 4 1>;
184	status = "disabled";
185	};
186
187	i2c4: i2c@2040000 {
188	compatible = "fsl,vf610-i2c";
189	#address-cells = <1>;
190	#size-cells = <0>;
191	reg = <0x0 0x2040000 0x0 0x10000>;
192	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
193	clocks = <&clockgen 4 1>;
194	status = "disabled";
195	};
196
197	i2c5: i2c@2050000 {
198	compatible = "fsl,vf610-i2c";
199	#address-cells = <1>;
200	#size-cells = <0>;
201	reg = <0x0 0x2050000 0x0 0x10000>;
202	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
203	clocks = <&clockgen 4 1>;
204	status = "disabled";
205	};
206
207	i2c6: i2c@2060000 {
208	compatible = "fsl,vf610-i2c";
209	#address-cells = <1>;
210	#size-cells = <0>;
211	reg = <0x0 0x2060000 0x0 0x10000>;
212	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
213	clocks = <&clockgen 4 1>;
214	status = "disabled";
215	};
216
217	i2c7: i2c@2070000 {
218	compatible = "fsl,vf610-i2c";
219	#address-cells = <1>;
220	#size-cells = <0>;
221	reg = <0x0 0x2070000 0x0 0x10000>;
222	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
223	clocks = <&clockgen 4 1>;
224	status = "disabled";
225	};
226
227	duart0: serial@21c0500 {
228	compatible = "fsl,ns16550", "ns16550a";
229	reg = <0x00 0x21c0500 0x0 0x100>;
230	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
231	clocks = <&clockgen 4 1>;
232	status = "disabled";
233	};
234
235	duart1: serial@21c0600 {
236	compatible = "fsl,ns16550", "ns16550a";
237	reg = <0x00 0x21c0600 0x0 0x100>;
238	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
239	clocks = <&clockgen 4 1>;
240	status = "disabled";
241	};
242
f54f7be5 AW	243	edma0: dma-controller@22c0000 {
	244	#dma-cells = <2>;
	245	compatible = "fsl,vf610-edma";
	246	reg = <0x0 0x22c0000 0x0 0x10000>,
	247	<0x0 0x22d0000 0x0 0x10000>,
	248	<0x0 0x22e0000 0x0 0x10000>;
	249	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	250	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
	251	interrupt-names = "edma-tx", "edma-err";
	252	dma-channels = <32>;
	253	clock-names = "dmamux0", "dmamux1";
	254	clocks = <&clockgen 4 1>,
	255	<&clockgen 4 1>;
	256	};
	257
8897f325 BU	258	gpio1: gpio@2300000 {
	259	compatible = "fsl,qoriq-gpio";
	260	reg = <0x0 0x2300000 0x0 0x10000>;
	261	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	262	gpio-controller;
	263	#gpio-cells = <2>;
	264	interrupt-controller;
	265	#interrupt-cells = <2>;
	266	};
	267
	268	gpio2: gpio@2310000 {
	269	compatible = "fsl,qoriq-gpio";
	270	reg = <0x0 0x2310000 0x0 0x10000>;
	271	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	272	gpio-controller;
	273	#gpio-cells = <2>;
	274	interrupt-controller;
	275	#interrupt-cells = <2>;
	276	};
	277
	278	gpio3: gpio@2320000 {
	279	compatible = "fsl,qoriq-gpio";
	280	reg = <0x0 0x2320000 0x0 0x10000>;
	281	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	282	gpio-controller;
	283	#gpio-cells = <2>;
	284	interrupt-controller;
	285	#interrupt-cells = <2>;
	286	};
	287
	288	wdog0: watchdog@23c0000 {
	289	compatible = "fsl,ls1028a-wdt", "fsl,imx21-wdt";
	290	reg = <0x0 0x23c0000 0x0 0x10000>;
	291	interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
	292	clocks = <&clockgen 4 1>;
	293	big-endian;
	294	status = "disabled";
	295	};
	296
	297	sata: sata@3200000 {
	298	compatible = "fsl,ls1028a-ahci";
	299	reg = <0x0 0x3200000 0x0 0x10000>,
3f3d7958	300	<0x7 0x100520 0x0 0x4>;
8897f325 BU	301	reg-names = "ahci", "sata-ecc";
	302	interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
	303	clocks = <&clockgen 4 1>;
	304	status = "disabled";
	305	};
	306
	307	smmu: iommu@5000000 {
	308	compatible = "arm,mmu-500";
	309	reg = <0 0x5000000 0 0x800000>;
	310	#global-interrupts = <8>;
	311	#iommu-cells = <1>;
	312	stream-match-mask = <0x7c00>;
	313	/* global secure fault */
	314	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
	315	/* combined secure interrupt */
	316	<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
	317	/* global non-secure fault */
	318	<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
	319	/* combined non-secure interrupt */
	320	<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
	321	/* performance counter interrupts 0-7 */
	322	<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
	323	<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
	324	/* per context interrupt, 64 interrupts */
	325	<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
	326	<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
	327	<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
	328	<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
	329	<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
	330	<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
	331	<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
	332	<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
	333	<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
	334	<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
	335	<GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
	336	<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
	337	<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
	338	<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
	339	<GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
	340	<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
	341	<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
	342	<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
	343	<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
	344	<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
	345	<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
	346	<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
	347	<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
	348	<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
	349	<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
	350	<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
	351	<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
	352	<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
	353	<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
	354	<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
	355	<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
	356	<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
	357	};
927d7f85	358
f54f7be5 AW	359	sai1: audio-controller@f100000 {
	360	#sound-dai-cells = <0>;
	361	compatible = "fsl,vf610-sai";
	362	reg = <0x0 0xf100000 0x0 0x10000>;
	363	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	364	clocks = <&clockgen 4 1>, <&clockgen 4 1>,
	365	<&clockgen 4 1>, <&clockgen 4 1>;
	366	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	367	dma-names = "tx", "rx";
	368	dmas = <&edma0 1 4>,
	369	<&edma0 1 3>;
	370	status = "disabled";
	371	};
	372
	373	sai2: audio-controller@f110000 {
	374	#sound-dai-cells = <0>;
	375	compatible = "fsl,vf610-sai";
	376	reg = <0x0 0xf110000 0x0 0x10000>;
	377	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
	378	clocks = <&clockgen 4 1>, <&clockgen 4 1>,
	379	<&clockgen 4 1>, <&clockgen 4 1>;
	380	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	381	dma-names = "tx", "rx";
	382	dmas = <&edma0 1 6>,
	383	<&edma0 1 5>;
	384	status = "disabled";
	385	};
	386
	387	sai4: audio-controller@f130000 {
	388	#sound-dai-cells = <0>;
	389	compatible = "fsl,vf610-sai";
	390	reg = <0x0 0xf130000 0x0 0x10000>;
	391	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
	392	clocks = <&clockgen 4 1>, <&clockgen 4 1>,
	393	<&clockgen 4 1>, <&clockgen 4 1>;
	394	clock-names = "bus", "mclk1", "mclk2", "mclk3";
	395	dma-names = "tx", "rx";
	396	dmas = <&edma0 1 10>,
	397	<&edma0 1 9>;
	398	status = "disabled";
	399	};
	400
927d7f85 CM	401	pcie@1f0000000 { /* Integrated Endpoint Root Complex */
	402	compatible = "pci-host-ecam-generic";
	403	reg = <0x01 0xf0000000 0x0 0x100000>;
	404	#address-cells = <3>;
	405	#size-cells = <2>;
	406	#interrupt-cells = <1>;
	407	msi-parent = <&its>;
	408	device_type = "pci";
	409	bus-range = <0x0 0x0>;
	410	dma-coherent;
	411	msi-map = <0 &its 0x17 0xe>;
	412	iommu-map = <0 &smmu 0x17 0xe>;
	413	/* PF0-6 BAR0 - non-prefetchable memory */
	414	ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000
	415	/* PF0-6 BAR2 - prefetchable memory */
	416	0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000
	417	/* PF0: VF0-1 BAR0 - non-prefetchable memory */
	418	0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000
	419	/* PF0: VF0-1 BAR2 - prefetchable memory */
	420	0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000
	421	/* PF1: VF0-1 BAR0 - non-prefetchable memory */
	422	0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000
	423	/* PF1: VF0-1 BAR2 - prefetchable memory */
	424	0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000>;
	425
	426	enetc_port0: ethernet@0,0 {
	427	compatible = "fsl,enetc";
	428	reg = <0x000000 0 0 0 0>;
	429	};
	430	enetc_port1: ethernet@0,1 {
	431	compatible = "fsl,enetc";
	432	reg = <0x000100 0 0 0 0>;
	433	};
	434	};
8897f325 BU	435	};
8897f325 BU	436	};