]>
Commit | Line | Data |
---|---|---|
7a2aeb91 | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
747c84d0 | 2 | /* |
f43a4b85 | 3 | * Device Tree Include file for Freescale Layerscape-2080A family SoC. |
747c84d0 | 4 | * |
8637f58b | 5 | * Copyright 2014-2016 Freescale Semiconductor, Inc. |
747c84d0 | 6 | * |
c2f6a472 | 7 | * Abhimanyu Saini <abhimanyu.saini@nxp.com> |
747c84d0 BS |
8 | * Bhupesh Sharma <bhupesh.sharma@freescale.com> |
9 | * | |
747c84d0 BS |
10 | */ |
11 | ||
c2f6a472 | 12 | #include "fsl-ls208xa.dtsi" |
236f794e | 13 | |
c2f6a472 AS |
14 | &cpu { |
15 | cpu0: cpu@0 { | |
16 | device_type = "cpu"; | |
17 | compatible = "arm,cortex-a57"; | |
18 | reg = <0x0>; | |
19 | clocks = <&clockgen 1 0>; | |
39a71db1 | 20 | cpu-idle-states = <&CPU_PW20>; |
c2f6a472 AS |
21 | next-level-cache = <&cluster0_l2>; |
22 | #cooling-cells = <2>; | |
747c84d0 BS |
23 | }; |
24 | ||
c2f6a472 AS |
25 | cpu1: cpu@1 { |
26 | device_type = "cpu"; | |
27 | compatible = "arm,cortex-a57"; | |
28 | reg = <0x1>; | |
29 | clocks = <&clockgen 1 0>; | |
39a71db1 | 30 | cpu-idle-states = <&CPU_PW20>; |
c2f6a472 | 31 | next-level-cache = <&cluster0_l2>; |
346f5976 | 32 | #cooling-cells = <2>; |
747c84d0 BS |
33 | }; |
34 | ||
c2f6a472 AS |
35 | cpu2: cpu@100 { |
36 | device_type = "cpu"; | |
37 | compatible = "arm,cortex-a57"; | |
38 | reg = <0x100>; | |
39 | clocks = <&clockgen 1 1>; | |
39a71db1 | 40 | cpu-idle-states = <&CPU_PW20>; |
c2f6a472 AS |
41 | next-level-cache = <&cluster1_l2>; |
42 | #cooling-cells = <2>; | |
5461597f BS |
43 | }; |
44 | ||
c2f6a472 AS |
45 | cpu3: cpu@101 { |
46 | device_type = "cpu"; | |
47 | compatible = "arm,cortex-a57"; | |
48 | reg = <0x101>; | |
49 | clocks = <&clockgen 1 1>; | |
39a71db1 | 50 | cpu-idle-states = <&CPU_PW20>; |
c2f6a472 | 51 | next-level-cache = <&cluster1_l2>; |
346f5976 | 52 | #cooling-cells = <2>; |
747c84d0 BS |
53 | }; |
54 | ||
c2f6a472 AS |
55 | cpu4: cpu@200 { |
56 | device_type = "cpu"; | |
57 | compatible = "arm,cortex-a57"; | |
58 | reg = <0x200>; | |
59 | clocks = <&clockgen 1 2>; | |
39a71db1 | 60 | cpu-idle-states = <&CPU_PW20>; |
c2f6a472 AS |
61 | next-level-cache = <&cluster2_l2>; |
62 | #cooling-cells = <2>; | |
c7a5675f GR |
63 | }; |
64 | ||
c2f6a472 AS |
65 | cpu5: cpu@201 { |
66 | device_type = "cpu"; | |
67 | compatible = "arm,cortex-a57"; | |
68 | reg = <0x201>; | |
69 | clocks = <&clockgen 1 2>; | |
39a71db1 | 70 | cpu-idle-states = <&CPU_PW20>; |
c2f6a472 | 71 | next-level-cache = <&cluster2_l2>; |
346f5976 | 72 | #cooling-cells = <2>; |
c7a5675f GR |
73 | }; |
74 | ||
c2f6a472 AS |
75 | cpu6: cpu@300 { |
76 | device_type = "cpu"; | |
77 | compatible = "arm,cortex-a57"; | |
78 | reg = <0x300>; | |
79 | clocks = <&clockgen 1 3>; | |
80 | next-level-cache = <&cluster3_l2>; | |
39a71db1 | 81 | cpu-idle-states = <&CPU_PW20>; |
c2f6a472 | 82 | #cooling-cells = <2>; |
747c84d0 BS |
83 | }; |
84 | ||
c2f6a472 AS |
85 | cpu7: cpu@301 { |
86 | device_type = "cpu"; | |
87 | compatible = "arm,cortex-a57"; | |
88 | reg = <0x301>; | |
89 | clocks = <&clockgen 1 3>; | |
39a71db1 | 90 | cpu-idle-states = <&CPU_PW20>; |
c2f6a472 | 91 | next-level-cache = <&cluster3_l2>; |
346f5976 | 92 | #cooling-cells = <2>; |
747c84d0 BS |
93 | }; |
94 | ||
c2f6a472 AS |
95 | cluster0_l2: l2-cache0 { |
96 | compatible = "cache"; | |
97 | }; | |
5461597f | 98 | |
c2f6a472 AS |
99 | cluster1_l2: l2-cache1 { |
100 | compatible = "cache"; | |
101 | }; | |
5461597f | 102 | |
c2f6a472 AS |
103 | cluster2_l2: l2-cache2 { |
104 | compatible = "cache"; | |
105 | }; | |
5461597f | 106 | |
c2f6a472 AS |
107 | cluster3_l2: l2-cache3 { |
108 | compatible = "cache"; | |
109 | }; | |
39a71db1 YT |
110 | |
111 | CPU_PW20: cpu-pw20 { | |
112 | compatible = "arm,idle-state"; | |
113 | idle-state-name = "PW20"; | |
114 | arm,psci-suspend-param = <0x00010000>; | |
115 | entry-latency-us = <2000>; | |
116 | exit-latency-us = <2000>; | |
117 | min-residency-us = <6000>; | |
118 | }; | |
c2f6a472 | 119 | }; |
5461597f | 120 | |
c2f6a472 AS |
121 | &pcie1 { |
122 | reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ | |
123 | 0x10 0x00000000 0x0 0x00002000>; /* configuration space */ | |
5461597f | 124 | |
c2f6a472 AS |
125 | ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */ |
126 | 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ | |
127 | }; | |
5461597f | 128 | |
c2f6a472 AS |
129 | &pcie2 { |
130 | reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ | |
131 | 0x12 0x00000000 0x0 0x00002000>; /* configuration space */ | |
5461597f | 132 | |
c2f6a472 AS |
133 | ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */ |
134 | 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ | |
135 | }; | |
5461597f | 136 | |
c2f6a472 AS |
137 | &pcie3 { |
138 | reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ | |
139 | 0x14 0x00000000 0x0 0x00002000>; /* configuration space */ | |
5461597f | 140 | |
c2f6a472 AS |
141 | ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */ |
142 | 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ | |
143 | }; | |
30062fb0 | 144 | |
c2f6a472 AS |
145 | &pcie4 { |
146 | reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ | |
147 | 0x16 0x00000000 0x0 0x00002000>; /* configuration space */ | |
30062fb0 | 148 | |
c2f6a472 AS |
149 | ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */ |
150 | 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ | |
747c84d0 | 151 | }; |