[mirror_ubuntu-focal-kernel.git] / arch / arm64 / boot / dts / freescale / fsl-ls2088a.dtsi

/*
 * Device Tree Include file for Freescale Layerscape-2088A family SoC.
 *
 * Copyright 2016 Freescale Semiconductor, Inc.
 * Copyright 2017 NXP
 *
 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPLv2 or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "fsl-ls208xa.dtsi"

&cpu {
	cpu0: cpu@0 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x0>;
		clocks = <&clockgen 1 0>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster0_l2>;
		#cooling-cells = <2>;
	};

	cpu1: cpu@1 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x1>;
		clocks = <&clockgen 1 0>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster0_l2>;
	};

	cpu2: cpu@100 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x100>;
		clocks = <&clockgen 1 1>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster1_l2>;
		#cooling-cells = <2>;
	};

	cpu3: cpu@101 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x101>;
		clocks = <&clockgen 1 1>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster1_l2>;
	};

	cpu4: cpu@200 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x200>;
		clocks = <&clockgen 1 2>;
		next-level-cache = <&cluster2_l2>;
		cpu-idle-states = <&CPU_PW20>;
		#cooling-cells = <2>;
	};

	cpu5: cpu@201 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x201>;
		clocks = <&clockgen 1 2>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster2_l2>;
	};

	cpu6: cpu@300 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x300>;
		clocks = <&clockgen 1 3>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster3_l2>;
		#cooling-cells = <2>;
	};

	cpu7: cpu@301 {
		device_type = "cpu";
		compatible = "arm,cortex-a72";
		reg = <0x301>;
		clocks = <&clockgen 1 3>;
		cpu-idle-states = <&CPU_PW20>;
		next-level-cache = <&cluster3_l2>;
	};

	cluster0_l2: l2-cache0 {
		compatible = "cache";
	};

	cluster1_l2: l2-cache1 {
		compatible = "cache";
	};

	cluster2_l2: l2-cache2 {
		compatible = "cache";
	};

	cluster3_l2: l2-cache3 {
		compatible = "cache";
	};

	CPU_PW20: cpu-pw20 {
		compatible = "arm,idle-state";
		idle-state-name = "PW20";
		arm,psci-suspend-param = <0x00010000>;
		entry-latency-us = <2000>;
		exit-latency-us = <2000>;
		min-residency-us = <6000>;
	};
};

&pcie1 {
	reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
	       0x20 0x00000000 0x0 0x00002000>; /* configuration space */

	ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000
		  0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>;
};

&pcie2 {
	reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
	       0x28 0x00000000 0x0 0x00002000>; /* configuration space */

	ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000
		  0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>;
};

&pcie3 {
	reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
	       0x30 0x00000000 0x0 0x00002000>; /* configuration space */

	ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000
		  0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>;
};

&pcie4 {
	reg = <0x00 0x03700000 0x0 0x00100000   /* controller registers */
	       0x38 0x00000000 0x0 0x00002000>; /* configuration space */

	ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000
		  0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>;
};
Commit	Line	Data
df72c23e AS	1	/*
	2	* Device Tree Include file for Freescale Layerscape-2088A family SoC.
	3	*
8637f58b LY	4	* Copyright 2016 Freescale Semiconductor, Inc.
8637f58b LY	5	* Copyright 2017 NXP
df72c23e AS	6	*
	7	* Abhimanyu Saini <abhimanyu.saini@nxp.com>
	8	*
	9	* This file is dual-licensed: you can use it either under the terms
	10	* of the GPLv2 or the X11 license, at your option. Note that this dual
	11	* licensing only applies to this file, and not this project as a
	12	* whole.
	13	*
	14	* a) This library is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of the
	17	* License, or (at your option) any later version.
	18	*
	19	* This library is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	22	* GNU General Public License for more details.
	23	*
	24	* Or, alternatively,
	25	*
	26	* b) Permission is hereby granted, free of charge, to any person
	27	* obtaining a copy of this software and associated documentation
	28	* files (the "Software"), to deal in the Software without
	29	* restriction, including without limitation the rights to use,
	30	* copy, modify, merge, publish, distribute, sublicense, and/or
	31	* sell copies of the Software, and to permit persons to whom the
	32	* Software is furnished to do so, subject to the following
	33	* conditions:
	34	*
	35	* The above copyright notice and this permission notice shall be
	36	* included in all copies or substantial portions of the Software.
	37	*
	38	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	39	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	40	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	41	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	42	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	43	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	44	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	45	* OTHER DEALINGS IN THE SOFTWARE.
	46	*/
	47
	48	#include "fsl-ls208xa.dtsi"
	49
	50	&cpu {
	51	cpu0: cpu@0 {
	52	device_type = "cpu";
	53	compatible = "arm,cortex-a72";
	54	reg = <0x0>;
	55	clocks = <&clockgen 1 0>;
39a71db1	56	cpu-idle-states = <&CPU_PW20>;
df72c23e AS	57	next-level-cache = <&cluster0_l2>;
	58	#cooling-cells = <2>;
	59	};
	60
	61	cpu1: cpu@1 {
	62	device_type = "cpu";
	63	compatible = "arm,cortex-a72";
	64	reg = <0x1>;
	65	clocks = <&clockgen 1 0>;
39a71db1	66	cpu-idle-states = <&CPU_PW20>;
df72c23e AS	67	next-level-cache = <&cluster0_l2>;
	68	};
	69
	70	cpu2: cpu@100 {
	71	device_type = "cpu";
	72	compatible = "arm,cortex-a72";
	73	reg = <0x100>;
	74	clocks = <&clockgen 1 1>;
39a71db1	75	cpu-idle-states = <&CPU_PW20>;
df72c23e AS	76	next-level-cache = <&cluster1_l2>;
	77	#cooling-cells = <2>;
	78	};
	79
	80	cpu3: cpu@101 {
	81	device_type = "cpu";
	82	compatible = "arm,cortex-a72";
	83	reg = <0x101>;
	84	clocks = <&clockgen 1 1>;
39a71db1	85	cpu-idle-states = <&CPU_PW20>;
df72c23e AS	86	next-level-cache = <&cluster1_l2>;
	87	};
	88
	89	cpu4: cpu@200 {
	90	device_type = "cpu";
	91	compatible = "arm,cortex-a72";
	92	reg = <0x200>;
	93	clocks = <&clockgen 1 2>;
	94	next-level-cache = <&cluster2_l2>;
39a71db1	95	cpu-idle-states = <&CPU_PW20>;
df72c23e AS	96	#cooling-cells = <2>;
	97	};
	98
	99	cpu5: cpu@201 {
	100	device_type = "cpu";
	101	compatible = "arm,cortex-a72";
	102	reg = <0x201>;
	103	clocks = <&clockgen 1 2>;
39a71db1	104	cpu-idle-states = <&CPU_PW20>;
df72c23e AS	105	next-level-cache = <&cluster2_l2>;
	106	};
	107
	108	cpu6: cpu@300 {
	109	device_type = "cpu";
	110	compatible = "arm,cortex-a72";
	111	reg = <0x300>;
	112	clocks = <&clockgen 1 3>;
39a71db1	113	cpu-idle-states = <&CPU_PW20>;
df72c23e AS	114	next-level-cache = <&cluster3_l2>;
	115	#cooling-cells = <2>;
	116	};
	117
	118	cpu7: cpu@301 {
	119	device_type = "cpu";
	120	compatible = "arm,cortex-a72";
	121	reg = <0x301>;
	122	clocks = <&clockgen 1 3>;
39a71db1	123	cpu-idle-states = <&CPU_PW20>;
df72c23e AS	124	next-level-cache = <&cluster3_l2>;
	125	};
	126
	127	cluster0_l2: l2-cache0 {
	128	compatible = "cache";
	129	};
	130
	131	cluster1_l2: l2-cache1 {
	132	compatible = "cache";
	133	};
	134
	135	cluster2_l2: l2-cache2 {
	136	compatible = "cache";
	137	};
	138
	139	cluster3_l2: l2-cache3 {
	140	compatible = "cache";
	141	};
39a71db1 YT	142
	143	CPU_PW20: cpu-pw20 {
	144	compatible = "arm,idle-state";
	145	idle-state-name = "PW20";
	146	arm,psci-suspend-param = <0x00010000>;
	147	entry-latency-us = <2000>;
	148	exit-latency-us = <2000>;
	149	min-residency-us = <6000>;
	150	};
df72c23e AS	151	};
	152
	153	&pcie1 {
	154	reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
	155	0x20 0x00000000 0x0 0x00002000>; /* configuration space */
	156
	157	ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000
	158	0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>;
	159	};
	160
	161	&pcie2 {
	162	reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
	163	0x28 0x00000000 0x0 0x00002000>; /* configuration space */
	164
	165	ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000
	166	0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>;
	167	};
	168
	169	&pcie3 {
	170	reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
	171	0x30 0x00000000 0x0 0x00002000>; /* configuration space */
	172
	173	ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000
	174	0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>;
	175	};
	176
	177	&pcie4 {
	178	reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
	179	0x38 0x00000000 0x0 0x00002000>; /* configuration space */
	180
	181	ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000
	182	0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>;
	183	};