]>
Commit | Line | Data |
---|---|---|
c2f6a472 AS |
1 | /* |
2 | * Device Tree Include file for Freescale Layerscape-2080A family SoC. | |
3 | * | |
8637f58b LY |
4 | * Copyright 2016 Freescale Semiconductor, Inc. |
5 | * Copyright 2017 NXP | |
c2f6a472 AS |
6 | * |
7 | * Abhimanyu Saini <abhimanyu.saini@nxp.com> | |
8 | * | |
9 | * This file is dual-licensed: you can use it either under the terms | |
10 | * of the GPLv2 or the X11 license, at your option. Note that this dual | |
11 | * licensing only applies to this file, and not this project as a | |
12 | * whole. | |
13 | * | |
14 | * a) This library is free software; you can redistribute it and/or | |
15 | * modify it under the terms of the GNU General Public License as | |
16 | * published by the Free Software Foundation; either version 2 of the | |
17 | * License, or (at your option) any later version. | |
18 | * | |
19 | * This library is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * Or, alternatively, | |
25 | * | |
26 | * b) Permission is hereby granted, free of charge, to any person | |
27 | * obtaining a copy of this software and associated documentation | |
28 | * files (the "Software"), to deal in the Software without | |
29 | * restriction, including without limitation the rights to use, | |
30 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
31 | * sell copies of the Software, and to permit persons to whom the | |
32 | * Software is furnished to do so, subject to the following | |
33 | * conditions: | |
34 | * | |
35 | * The above copyright notice and this permission notice shall be | |
36 | * included in all copies or substantial portions of the Software. | |
37 | * | |
38 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
39 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
40 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
41 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
42 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
43 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
44 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
45 | * OTHER DEALINGS IN THE SOFTWARE. | |
46 | */ | |
47 | ||
48 | #include <dt-bindings/thermal/thermal.h> | |
49 | ||
50 | / { | |
51 | compatible = "fsl,ls2080a"; | |
52 | interrupt-parent = <&gic>; | |
53 | #address-cells = <2>; | |
54 | #size-cells = <2>; | |
55 | ||
56 | cpu: cpus { | |
57 | #address-cells = <1>; | |
58 | #size-cells = <0>; | |
59 | }; | |
60 | ||
61 | memory@80000000 { | |
62 | device_type = "memory"; | |
63 | reg = <0x00000000 0x80000000 0 0x80000000>; | |
64 | /* DRAM space - 1, size : 2 GB DRAM */ | |
65 | }; | |
66 | ||
67 | sysclk: sysclk { | |
68 | compatible = "fixed-clock"; | |
69 | #clock-cells = <0>; | |
70 | clock-frequency = <100000000>; | |
71 | clock-output-names = "sysclk"; | |
72 | }; | |
73 | ||
74 | gic: interrupt-controller@6000000 { | |
75 | compatible = "arm,gic-v3"; | |
76 | reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ | |
77 | <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ | |
78 | <0x0 0x0c0c0000 0 0x2000>, /* GICC */ | |
79 | <0x0 0x0c0d0000 0 0x1000>, /* GICH */ | |
80 | <0x0 0x0c0e0000 0 0x20000>; /* GICV */ | |
81 | #interrupt-cells = <3>; | |
82 | #address-cells = <2>; | |
83 | #size-cells = <2>; | |
84 | ranges; | |
85 | interrupt-controller; | |
86 | interrupts = <1 9 0x4>; | |
87 | ||
88 | its: gic-its@6020000 { | |
89 | compatible = "arm,gic-v3-its"; | |
90 | msi-controller; | |
91 | reg = <0x0 0x6020000 0 0x20000>; | |
92 | }; | |
93 | }; | |
94 | ||
95 | rstcr: syscon@1e60000 { | |
96 | compatible = "fsl,ls2080a-rstcr", "syscon"; | |
97 | reg = <0x0 0x1e60000 0x0 0x4>; | |
98 | }; | |
99 | ||
100 | reboot { | |
101 | compatible ="syscon-reboot"; | |
102 | regmap = <&rstcr>; | |
103 | offset = <0x0>; | |
104 | mask = <0x2>; | |
105 | }; | |
106 | ||
107 | timer { | |
108 | compatible = "arm,armv8-timer"; | |
109 | interrupts = <1 13 4>, /* Physical Secure PPI, active-low */ | |
110 | <1 14 4>, /* Physical Non-Secure PPI, active-low */ | |
111 | <1 11 4>, /* Virtual PPI, active-low */ | |
112 | <1 10 4>; /* Hypervisor PPI, active-low */ | |
113 | fsl,erratum-a008585; | |
114 | }; | |
115 | ||
116 | pmu { | |
117 | compatible = "arm,armv8-pmuv3"; | |
118 | interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ | |
119 | }; | |
120 | ||
121 | soc { | |
122 | compatible = "simple-bus"; | |
123 | #address-cells = <2>; | |
124 | #size-cells = <2>; | |
125 | ranges; | |
126 | ||
127 | clockgen: clocking@1300000 { | |
128 | compatible = "fsl,ls2080a-clockgen"; | |
129 | reg = <0 0x1300000 0 0xa0000>; | |
130 | #clock-cells = <2>; | |
131 | clocks = <&sysclk>; | |
132 | }; | |
133 | ||
134 | dcfg: dcfg@1e00000 { | |
135 | compatible = "fsl,ls2080a-dcfg", "syscon"; | |
136 | reg = <0x0 0x1e00000 0x0 0x10000>; | |
137 | little-endian; | |
138 | }; | |
139 | ||
140 | tmu: tmu@1f80000 { | |
141 | compatible = "fsl,qoriq-tmu"; | |
142 | reg = <0x0 0x1f80000 0x0 0x10000>; | |
143 | interrupts = <0 23 0x4>; | |
144 | fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; | |
145 | fsl,tmu-calibration = <0x00000000 0x00000026 | |
146 | 0x00000001 0x0000002d | |
147 | 0x00000002 0x00000032 | |
148 | 0x00000003 0x00000039 | |
149 | 0x00000004 0x0000003f | |
150 | 0x00000005 0x00000046 | |
151 | 0x00000006 0x0000004d | |
152 | 0x00000007 0x00000054 | |
153 | 0x00000008 0x0000005a | |
154 | 0x00000009 0x00000061 | |
155 | 0x0000000a 0x0000006a | |
156 | 0x0000000b 0x00000071 | |
157 | ||
158 | 0x00010000 0x00000025 | |
159 | 0x00010001 0x0000002c | |
160 | 0x00010002 0x00000035 | |
161 | 0x00010003 0x0000003d | |
162 | 0x00010004 0x00000045 | |
163 | 0x00010005 0x0000004e | |
164 | 0x00010006 0x00000057 | |
165 | 0x00010007 0x00000061 | |
166 | 0x00010008 0x0000006b | |
167 | 0x00010009 0x00000076 | |
168 | ||
169 | 0x00020000 0x00000029 | |
170 | 0x00020001 0x00000033 | |
171 | 0x00020002 0x0000003d | |
172 | 0x00020003 0x00000049 | |
173 | 0x00020004 0x00000056 | |
174 | 0x00020005 0x00000061 | |
175 | 0x00020006 0x0000006d | |
176 | ||
177 | 0x00030000 0x00000021 | |
178 | 0x00030001 0x0000002a | |
179 | 0x00030002 0x0000003c | |
180 | 0x00030003 0x0000004e>; | |
181 | little-endian; | |
182 | #thermal-sensor-cells = <1>; | |
183 | }; | |
184 | ||
185 | thermal-zones { | |
186 | cpu_thermal: cpu-thermal { | |
187 | polling-delay-passive = <1000>; | |
188 | polling-delay = <5000>; | |
189 | ||
190 | thermal-sensors = <&tmu 4>; | |
191 | ||
192 | trips { | |
193 | cpu_alert: cpu-alert { | |
194 | temperature = <75000>; | |
195 | hysteresis = <2000>; | |
196 | type = "passive"; | |
197 | }; | |
198 | cpu_crit: cpu-crit { | |
199 | temperature = <85000>; | |
200 | hysteresis = <2000>; | |
201 | type = "critical"; | |
202 | }; | |
203 | }; | |
204 | ||
205 | cooling-maps { | |
206 | map0 { | |
207 | trip = <&cpu_alert>; | |
208 | cooling-device = | |
209 | <&cpu0 THERMAL_NO_LIMIT | |
210 | THERMAL_NO_LIMIT>; | |
211 | }; | |
212 | map1 { | |
213 | trip = <&cpu_alert>; | |
214 | cooling-device = | |
215 | <&cpu2 THERMAL_NO_LIMIT | |
216 | THERMAL_NO_LIMIT>; | |
217 | }; | |
218 | map2 { | |
219 | trip = <&cpu_alert>; | |
220 | cooling-device = | |
221 | <&cpu4 THERMAL_NO_LIMIT | |
222 | THERMAL_NO_LIMIT>; | |
223 | }; | |
224 | map3 { | |
225 | trip = <&cpu_alert>; | |
226 | cooling-device = | |
227 | <&cpu6 THERMAL_NO_LIMIT | |
228 | THERMAL_NO_LIMIT>; | |
229 | }; | |
230 | }; | |
231 | }; | |
232 | }; | |
233 | ||
234 | serial0: serial@21c0500 { | |
235 | compatible = "fsl,ns16550", "ns16550a"; | |
236 | reg = <0x0 0x21c0500 0x0 0x100>; | |
237 | clocks = <&clockgen 4 3>; | |
238 | interrupts = <0 32 0x4>; /* Level high type */ | |
239 | }; | |
240 | ||
241 | serial1: serial@21c0600 { | |
242 | compatible = "fsl,ns16550", "ns16550a"; | |
243 | reg = <0x0 0x21c0600 0x0 0x100>; | |
244 | clocks = <&clockgen 4 3>; | |
245 | interrupts = <0 32 0x4>; /* Level high type */ | |
246 | }; | |
247 | ||
248 | cluster1_core0_watchdog: wdt@c000000 { | |
249 | compatible = "arm,sp805-wdt", "arm,primecell"; | |
250 | reg = <0x0 0xc000000 0x0 0x1000>; | |
251 | clocks = <&clockgen 4 3>, <&clockgen 4 3>; | |
252 | clock-names = "apb_pclk", "wdog_clk"; | |
253 | }; | |
254 | ||
255 | cluster1_core1_watchdog: wdt@c010000 { | |
256 | compatible = "arm,sp805-wdt", "arm,primecell"; | |
257 | reg = <0x0 0xc010000 0x0 0x1000>; | |
258 | clocks = <&clockgen 4 3>, <&clockgen 4 3>; | |
259 | clock-names = "apb_pclk", "wdog_clk"; | |
260 | }; | |
261 | ||
262 | cluster2_core0_watchdog: wdt@c100000 { | |
263 | compatible = "arm,sp805-wdt", "arm,primecell"; | |
264 | reg = <0x0 0xc100000 0x0 0x1000>; | |
265 | clocks = <&clockgen 4 3>, <&clockgen 4 3>; | |
266 | clock-names = "apb_pclk", "wdog_clk"; | |
267 | }; | |
268 | ||
269 | cluster2_core1_watchdog: wdt@c110000 { | |
270 | compatible = "arm,sp805-wdt", "arm,primecell"; | |
271 | reg = <0x0 0xc110000 0x0 0x1000>; | |
272 | clocks = <&clockgen 4 3>, <&clockgen 4 3>; | |
273 | clock-names = "apb_pclk", "wdog_clk"; | |
274 | }; | |
275 | ||
276 | cluster3_core0_watchdog: wdt@c200000 { | |
277 | compatible = "arm,sp805-wdt", "arm,primecell"; | |
278 | reg = <0x0 0xc200000 0x0 0x1000>; | |
279 | clocks = <&clockgen 4 3>, <&clockgen 4 3>; | |
280 | clock-names = "apb_pclk", "wdog_clk"; | |
281 | }; | |
282 | ||
283 | cluster3_core1_watchdog: wdt@c210000 { | |
284 | compatible = "arm,sp805-wdt", "arm,primecell"; | |
285 | reg = <0x0 0xc210000 0x0 0x1000>; | |
286 | clocks = <&clockgen 4 3>, <&clockgen 4 3>; | |
287 | clock-names = "apb_pclk", "wdog_clk"; | |
288 | }; | |
289 | ||
290 | cluster4_core0_watchdog: wdt@c300000 { | |
291 | compatible = "arm,sp805-wdt", "arm,primecell"; | |
292 | reg = <0x0 0xc300000 0x0 0x1000>; | |
293 | clocks = <&clockgen 4 3>, <&clockgen 4 3>; | |
294 | clock-names = "apb_pclk", "wdog_clk"; | |
295 | }; | |
296 | ||
297 | cluster4_core1_watchdog: wdt@c310000 { | |
298 | compatible = "arm,sp805-wdt", "arm,primecell"; | |
299 | reg = <0x0 0xc310000 0x0 0x1000>; | |
300 | clocks = <&clockgen 4 3>, <&clockgen 4 3>; | |
301 | clock-names = "apb_pclk", "wdog_clk"; | |
302 | }; | |
303 | ||
304 | fsl_mc: fsl-mc@80c000000 { | |
305 | compatible = "fsl,qoriq-mc"; | |
306 | reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ | |
307 | <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ | |
308 | msi-parent = <&its>; | |
309 | #address-cells = <3>; | |
310 | #size-cells = <1>; | |
311 | ||
312 | /* | |
313 | * Region type 0x0 - MC portals | |
314 | * Region type 0x1 - QBMAN portals | |
315 | */ | |
316 | ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 | |
317 | 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; | |
318 | ||
319 | /* | |
320 | * Define the maximum number of MACs present on the SoC. | |
321 | */ | |
322 | dpmacs { | |
323 | #address-cells = <1>; | |
324 | #size-cells = <0>; | |
325 | ||
326 | dpmac1: dpmac@1 { | |
327 | compatible = "fsl,qoriq-mc-dpmac"; | |
328 | reg = <0x1>; | |
329 | }; | |
330 | ||
331 | dpmac2: dpmac@2 { | |
332 | compatible = "fsl,qoriq-mc-dpmac"; | |
333 | reg = <0x2>; | |
334 | }; | |
335 | ||
336 | dpmac3: dpmac@3 { | |
337 | compatible = "fsl,qoriq-mc-dpmac"; | |
338 | reg = <0x3>; | |
339 | }; | |
340 | ||
341 | dpmac4: dpmac@4 { | |
342 | compatible = "fsl,qoriq-mc-dpmac"; | |
343 | reg = <0x4>; | |
344 | }; | |
345 | ||
346 | dpmac5: dpmac@5 { | |
347 | compatible = "fsl,qoriq-mc-dpmac"; | |
348 | reg = <0x5>; | |
349 | }; | |
350 | ||
351 | dpmac6: dpmac@6 { | |
352 | compatible = "fsl,qoriq-mc-dpmac"; | |
353 | reg = <0x6>; | |
354 | }; | |
355 | ||
356 | dpmac7: dpmac@7 { | |
357 | compatible = "fsl,qoriq-mc-dpmac"; | |
358 | reg = <0x7>; | |
359 | }; | |
360 | ||
361 | dpmac8: dpmac@8 { | |
362 | compatible = "fsl,qoriq-mc-dpmac"; | |
363 | reg = <0x8>; | |
364 | }; | |
365 | ||
366 | dpmac9: dpmac@9 { | |
367 | compatible = "fsl,qoriq-mc-dpmac"; | |
368 | reg = <0x9>; | |
369 | }; | |
370 | ||
371 | dpmac10: dpmac@a { | |
372 | compatible = "fsl,qoriq-mc-dpmac"; | |
373 | reg = <0xa>; | |
374 | }; | |
375 | ||
376 | dpmac11: dpmac@b { | |
377 | compatible = "fsl,qoriq-mc-dpmac"; | |
378 | reg = <0xb>; | |
379 | }; | |
380 | ||
381 | dpmac12: dpmac@c { | |
382 | compatible = "fsl,qoriq-mc-dpmac"; | |
383 | reg = <0xc>; | |
384 | }; | |
385 | ||
386 | dpmac13: dpmac@d { | |
387 | compatible = "fsl,qoriq-mc-dpmac"; | |
388 | reg = <0xd>; | |
389 | }; | |
390 | ||
391 | dpmac14: dpmac@e { | |
392 | compatible = "fsl,qoriq-mc-dpmac"; | |
393 | reg = <0xe>; | |
394 | }; | |
395 | ||
396 | dpmac15: dpmac@f { | |
397 | compatible = "fsl,qoriq-mc-dpmac"; | |
398 | reg = <0xf>; | |
399 | }; | |
400 | ||
401 | dpmac16: dpmac@10 { | |
402 | compatible = "fsl,qoriq-mc-dpmac"; | |
403 | reg = <0x10>; | |
404 | }; | |
405 | }; | |
406 | }; | |
407 | ||
408 | smmu: iommu@5000000 { | |
409 | compatible = "arm,mmu-500"; | |
410 | reg = <0 0x5000000 0 0x800000>; | |
411 | #global-interrupts = <12>; | |
412 | interrupts = <0 13 4>, /* global secure fault */ | |
413 | <0 14 4>, /* combined secure interrupt */ | |
414 | <0 15 4>, /* global non-secure fault */ | |
415 | <0 16 4>, /* combined non-secure interrupt */ | |
416 | /* performance counter interrupts 0-7 */ | |
417 | <0 211 4>, <0 212 4>, | |
418 | <0 213 4>, <0 214 4>, | |
419 | <0 215 4>, <0 216 4>, | |
420 | <0 217 4>, <0 218 4>, | |
421 | /* per context interrupt, 64 interrupts */ | |
422 | <0 146 4>, <0 147 4>, | |
423 | <0 148 4>, <0 149 4>, | |
424 | <0 150 4>, <0 151 4>, | |
425 | <0 152 4>, <0 153 4>, | |
426 | <0 154 4>, <0 155 4>, | |
427 | <0 156 4>, <0 157 4>, | |
428 | <0 158 4>, <0 159 4>, | |
429 | <0 160 4>, <0 161 4>, | |
430 | <0 162 4>, <0 163 4>, | |
431 | <0 164 4>, <0 165 4>, | |
432 | <0 166 4>, <0 167 4>, | |
433 | <0 168 4>, <0 169 4>, | |
434 | <0 170 4>, <0 171 4>, | |
435 | <0 172 4>, <0 173 4>, | |
436 | <0 174 4>, <0 175 4>, | |
437 | <0 176 4>, <0 177 4>, | |
438 | <0 178 4>, <0 179 4>, | |
439 | <0 180 4>, <0 181 4>, | |
440 | <0 182 4>, <0 183 4>, | |
441 | <0 184 4>, <0 185 4>, | |
442 | <0 186 4>, <0 187 4>, | |
443 | <0 188 4>, <0 189 4>, | |
444 | <0 190 4>, <0 191 4>, | |
445 | <0 192 4>, <0 193 4>, | |
446 | <0 194 4>, <0 195 4>, | |
447 | <0 196 4>, <0 197 4>, | |
448 | <0 198 4>, <0 199 4>, | |
449 | <0 200 4>, <0 201 4>, | |
450 | <0 202 4>, <0 203 4>, | |
451 | <0 204 4>, <0 205 4>, | |
452 | <0 206 4>, <0 207 4>, | |
453 | <0 208 4>, <0 209 4>; | |
454 | mmu-masters = <&fsl_mc 0x300 0>; | |
455 | }; | |
456 | ||
457 | dspi: dspi@2100000 { | |
458 | status = "disabled"; | |
459 | compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi"; | |
460 | #address-cells = <1>; | |
461 | #size-cells = <0>; | |
462 | reg = <0x0 0x2100000 0x0 0x10000>; | |
463 | interrupts = <0 26 0x4>; /* Level high type */ | |
464 | clocks = <&clockgen 4 3>; | |
465 | clock-names = "dspi"; | |
466 | spi-num-chipselects = <5>; | |
467 | bus-num = <0>; | |
468 | }; | |
469 | ||
470 | esdhc: esdhc@2140000 { | |
471 | status = "disabled"; | |
472 | compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; | |
473 | reg = <0x0 0x2140000 0x0 0x10000>; | |
474 | interrupts = <0 28 0x4>; /* Level high type */ | |
6557a16c | 475 | clocks = <&clockgen 4 1>; |
c2f6a472 AS |
476 | voltage-ranges = <1800 1800 3300 3300>; |
477 | sdhci,auto-cmd12; | |
478 | little-endian; | |
479 | bus-width = <4>; | |
480 | }; | |
481 | ||
482 | gpio0: gpio@2300000 { | |
483 | compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; | |
484 | reg = <0x0 0x2300000 0x0 0x10000>; | |
485 | interrupts = <0 36 0x4>; /* Level high type */ | |
486 | gpio-controller; | |
487 | little-endian; | |
488 | #gpio-cells = <2>; | |
489 | interrupt-controller; | |
490 | #interrupt-cells = <2>; | |
491 | }; | |
492 | ||
493 | gpio1: gpio@2310000 { | |
494 | compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; | |
495 | reg = <0x0 0x2310000 0x0 0x10000>; | |
496 | interrupts = <0 36 0x4>; /* Level high type */ | |
497 | gpio-controller; | |
498 | little-endian; | |
499 | #gpio-cells = <2>; | |
500 | interrupt-controller; | |
501 | #interrupt-cells = <2>; | |
502 | }; | |
503 | ||
504 | gpio2: gpio@2320000 { | |
505 | compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; | |
506 | reg = <0x0 0x2320000 0x0 0x10000>; | |
507 | interrupts = <0 37 0x4>; /* Level high type */ | |
508 | gpio-controller; | |
509 | little-endian; | |
510 | #gpio-cells = <2>; | |
511 | interrupt-controller; | |
512 | #interrupt-cells = <2>; | |
513 | }; | |
514 | ||
515 | gpio3: gpio@2330000 { | |
516 | compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; | |
517 | reg = <0x0 0x2330000 0x0 0x10000>; | |
518 | interrupts = <0 37 0x4>; /* Level high type */ | |
519 | gpio-controller; | |
520 | little-endian; | |
521 | #gpio-cells = <2>; | |
522 | interrupt-controller; | |
523 | #interrupt-cells = <2>; | |
524 | }; | |
525 | ||
526 | i2c0: i2c@2000000 { | |
527 | status = "disabled"; | |
528 | compatible = "fsl,vf610-i2c"; | |
529 | #address-cells = <1>; | |
530 | #size-cells = <0>; | |
531 | reg = <0x0 0x2000000 0x0 0x10000>; | |
532 | interrupts = <0 34 0x4>; /* Level high type */ | |
533 | clock-names = "i2c"; | |
534 | clocks = <&clockgen 4 3>; | |
535 | }; | |
536 | ||
537 | i2c1: i2c@2010000 { | |
538 | status = "disabled"; | |
539 | compatible = "fsl,vf610-i2c"; | |
540 | #address-cells = <1>; | |
541 | #size-cells = <0>; | |
542 | reg = <0x0 0x2010000 0x0 0x10000>; | |
543 | interrupts = <0 34 0x4>; /* Level high type */ | |
544 | clock-names = "i2c"; | |
545 | clocks = <&clockgen 4 3>; | |
546 | }; | |
547 | ||
548 | i2c2: i2c@2020000 { | |
549 | status = "disabled"; | |
550 | compatible = "fsl,vf610-i2c"; | |
551 | #address-cells = <1>; | |
552 | #size-cells = <0>; | |
553 | reg = <0x0 0x2020000 0x0 0x10000>; | |
554 | interrupts = <0 35 0x4>; /* Level high type */ | |
555 | clock-names = "i2c"; | |
556 | clocks = <&clockgen 4 3>; | |
557 | }; | |
558 | ||
559 | i2c3: i2c@2030000 { | |
560 | status = "disabled"; | |
561 | compatible = "fsl,vf610-i2c"; | |
562 | #address-cells = <1>; | |
563 | #size-cells = <0>; | |
564 | reg = <0x0 0x2030000 0x0 0x10000>; | |
565 | interrupts = <0 35 0x4>; /* Level high type */ | |
566 | clock-names = "i2c"; | |
567 | clocks = <&clockgen 4 3>; | |
568 | }; | |
569 | ||
570 | ifc: ifc@2240000 { | |
571 | compatible = "fsl,ifc", "simple-bus"; | |
572 | reg = <0x0 0x2240000 0x0 0x20000>; | |
573 | interrupts = <0 21 0x4>; /* Level high type */ | |
574 | little-endian; | |
575 | #address-cells = <2>; | |
576 | #size-cells = <1>; | |
577 | ||
578 | ranges = <0 0 0x5 0x80000000 0x08000000 | |
579 | 2 0 0x5 0x30000000 0x00010000 | |
580 | 3 0 0x5 0x20000000 0x00010000>; | |
581 | }; | |
582 | ||
583 | qspi: quadspi@20c0000 { | |
584 | status = "disabled"; | |
585 | compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi"; | |
586 | #address-cells = <1>; | |
587 | #size-cells = <0>; | |
588 | reg = <0x0 0x20c0000 0x0 0x10000>, | |
589 | <0x0 0x20000000 0x0 0x10000000>; | |
590 | reg-names = "QuadSPI", "QuadSPI-memory"; | |
591 | interrupts = <0 25 0x4>; /* Level high type */ | |
592 | clocks = <&clockgen 4 3>, <&clockgen 4 3>; | |
593 | clock-names = "qspi_en", "qspi"; | |
594 | }; | |
595 | ||
596 | pcie1: pcie@3400000 { | |
597 | compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", | |
598 | "snps,dw-pcie"; | |
599 | reg-names = "regs", "config"; | |
600 | interrupts = <0 108 0x4>; /* Level high type */ | |
601 | interrupt-names = "intr"; | |
602 | #address-cells = <3>; | |
603 | #size-cells = <2>; | |
604 | device_type = "pci"; | |
605 | dma-coherent; | |
606 | num-lanes = <4>; | |
607 | bus-range = <0x0 0xff>; | |
608 | msi-parent = <&its>; | |
609 | #interrupt-cells = <1>; | |
610 | interrupt-map-mask = <0 0 0 7>; | |
611 | interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, | |
612 | <0000 0 0 2 &gic 0 0 0 110 4>, | |
613 | <0000 0 0 3 &gic 0 0 0 111 4>, | |
614 | <0000 0 0 4 &gic 0 0 0 112 4>; | |
615 | }; | |
616 | ||
617 | pcie2: pcie@3500000 { | |
618 | compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", | |
619 | "snps,dw-pcie"; | |
620 | reg-names = "regs", "config"; | |
621 | interrupts = <0 113 0x4>; /* Level high type */ | |
622 | interrupt-names = "intr"; | |
623 | #address-cells = <3>; | |
624 | #size-cells = <2>; | |
625 | device_type = "pci"; | |
626 | dma-coherent; | |
627 | num-lanes = <4>; | |
628 | bus-range = <0x0 0xff>; | |
629 | msi-parent = <&its>; | |
630 | #interrupt-cells = <1>; | |
631 | interrupt-map-mask = <0 0 0 7>; | |
632 | interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>, | |
633 | <0000 0 0 2 &gic 0 0 0 115 4>, | |
634 | <0000 0 0 3 &gic 0 0 0 116 4>, | |
635 | <0000 0 0 4 &gic 0 0 0 117 4>; | |
636 | }; | |
637 | ||
638 | pcie3: pcie@3600000 { | |
639 | compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", | |
640 | "snps,dw-pcie"; | |
641 | reg-names = "regs", "config"; | |
642 | interrupts = <0 118 0x4>; /* Level high type */ | |
643 | interrupt-names = "intr"; | |
644 | #address-cells = <3>; | |
645 | #size-cells = <2>; | |
646 | device_type = "pci"; | |
647 | dma-coherent; | |
648 | num-lanes = <8>; | |
649 | bus-range = <0x0 0xff>; | |
650 | msi-parent = <&its>; | |
651 | #interrupt-cells = <1>; | |
652 | interrupt-map-mask = <0 0 0 7>; | |
653 | interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>, | |
654 | <0000 0 0 2 &gic 0 0 0 120 4>, | |
655 | <0000 0 0 3 &gic 0 0 0 121 4>, | |
656 | <0000 0 0 4 &gic 0 0 0 122 4>; | |
657 | }; | |
658 | ||
659 | pcie4: pcie@3700000 { | |
660 | compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", | |
661 | "snps,dw-pcie"; | |
662 | reg-names = "regs", "config"; | |
663 | interrupts = <0 123 0x4>; /* Level high type */ | |
664 | interrupt-names = "intr"; | |
665 | #address-cells = <3>; | |
666 | #size-cells = <2>; | |
667 | device_type = "pci"; | |
668 | dma-coherent; | |
669 | num-lanes = <4>; | |
670 | bus-range = <0x0 0xff>; | |
671 | msi-parent = <&its>; | |
672 | #interrupt-cells = <1>; | |
673 | interrupt-map-mask = <0 0 0 7>; | |
674 | interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>, | |
675 | <0000 0 0 2 &gic 0 0 0 125 4>, | |
676 | <0000 0 0 3 &gic 0 0 0 126 4>, | |
677 | <0000 0 0 4 &gic 0 0 0 127 4>; | |
678 | }; | |
679 | ||
680 | sata0: sata@3200000 { | |
681 | status = "disabled"; | |
682 | compatible = "fsl,ls2080a-ahci"; | |
683 | reg = <0x0 0x3200000 0x0 0x10000>; | |
684 | interrupts = <0 133 0x4>; /* Level high type */ | |
685 | clocks = <&clockgen 4 3>; | |
686 | dma-coherent; | |
687 | }; | |
688 | ||
689 | sata1: sata@3210000 { | |
690 | status = "disabled"; | |
691 | compatible = "fsl,ls2080a-ahci"; | |
692 | reg = <0x0 0x3210000 0x0 0x10000>; | |
693 | interrupts = <0 136 0x4>; /* Level high type */ | |
694 | clocks = <&clockgen 4 3>; | |
695 | dma-coherent; | |
696 | }; | |
697 | ||
698 | usb0: usb3@3100000 { | |
699 | status = "disabled"; | |
700 | compatible = "snps,dwc3"; | |
701 | reg = <0x0 0x3100000 0x0 0x10000>; | |
702 | interrupts = <0 80 0x4>; /* Level high type */ | |
703 | dr_mode = "host"; | |
704 | snps,quirk-frame-length-adjustment = <0x20>; | |
705 | snps,dis_rxdet_inp3_quirk; | |
706 | }; | |
707 | ||
708 | usb1: usb3@3110000 { | |
709 | status = "disabled"; | |
710 | compatible = "snps,dwc3"; | |
711 | reg = <0x0 0x3110000 0x0 0x10000>; | |
712 | interrupts = <0 81 0x4>; /* Level high type */ | |
713 | dr_mode = "host"; | |
714 | snps,quirk-frame-length-adjustment = <0x20>; | |
715 | snps,dis_rxdet_inp3_quirk; | |
716 | }; | |
717 | ||
718 | ccn@4000000 { | |
719 | compatible = "arm,ccn-504"; | |
720 | reg = <0x0 0x04000000 0x0 0x01000000>; | |
721 | interrupts = <0 12 4>; | |
722 | }; | |
723 | }; | |
724 | ||
725 | ddr1: memory-controller@1080000 { | |
726 | compatible = "fsl,qoriq-memory-controller"; | |
727 | reg = <0x0 0x1080000 0x0 0x1000>; | |
728 | interrupts = <0 17 0x4>; | |
729 | little-endian; | |
730 | }; | |
731 | ||
732 | ddr2: memory-controller@1090000 { | |
733 | compatible = "fsl,qoriq-memory-controller"; | |
734 | reg = <0x0 0x1090000 0x0 0x1000>; | |
735 | interrupts = <0 18 0x4>; | |
736 | little-endian; | |
737 | }; | |
738 | }; |