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Merge tag 'powerpc-5.2-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc...
[mirror_ubuntu-hirsute-kernel.git] / arch / arm64 / boot / dts / freescale / imx8mq.dtsi
CommitLineData
748f908c
LS		 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2017 NXP
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5 */
6
7#include <dt-bindings/clock/imx8mq-clock.h>
fdbcc04d 8#include <dt-bindings/power/imx8mq-power.h>
fc26e600 9#include <dt-bindings/reset/imx8mq-reset.h>
748f908c
LS		 10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
e464fd2b 12#include <dt-bindings/thermal/thermal.h>
748f908c
LS		 13#include "imx8mq-pinfunc.h"
14
15/ {
c412123f 16 interrupt-parent = <&gpc>;
748f908c
LS		 17
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 aliases {
22 i2c0 = &i2c1;
23 i2c1 = &i2c2;
24 i2c2 = &i2c3;
25 i2c3 = &i2c4;
26 serial0 = &uart1;
27 serial1 = &uart2;
28 serial2 = &uart3;
29 serial3 = &uart4;
85761f45
FE		 30 spi0 = &ecspi1;
31 spi1 = &ecspi2;
32 spi2 = &ecspi3;
748f908c
LS		 33 };
34
35 ckil: clock-ckil {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <32768>;
39 clock-output-names = "ckil";
40 };
41
42 osc_25m: clock-osc-25m {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <25000000>;
46 clock-output-names = "osc_25m";
47 };
48
49 osc_27m: clock-osc-27m {
50 compatible = "fixed-clock";
51 #clock-cells = <0>;
52 clock-frequency = <27000000>;
53 clock-output-names = "osc_27m";
54 };
55
56 clk_ext1: clock-ext1 {
57 compatible = "fixed-clock";
58 #clock-cells = <0>;
59 clock-frequency = <133000000>;
60 clock-output-names = "clk_ext1";
61 };
62
63 clk_ext2: clock-ext2 {
64 compatible = "fixed-clock";
65 #clock-cells = <0>;
66 clock-frequency = <133000000>;
67 clock-output-names = "clk_ext2";
68 };
69
70 clk_ext3: clock-ext3 {
71 compatible = "fixed-clock";
72 #clock-cells = <0>;
73 clock-frequency = <133000000>;
74 clock-output-names = "clk_ext3";
75 };
76
77 clk_ext4: clock-ext4 {
78 compatible = "fixed-clock";
79 #clock-cells = <0>;
80 clock-frequency= <133000000>;
81 clock-output-names = "clk_ext4";
82 };
83
84 cpus {
85 #address-cells = <1>;
86 #size-cells = <0>;
87
88 A53_0: cpu@0 {
89 device_type = "cpu";
90 compatible = "arm,cortex-a53";
91 reg = <0x0>;
b810641a
AV		 92 clock-latency = <61036>; /* two CLK32 periods */
93 clocks = <&clk IMX8MQ_CLK_ARM>;
748f908c
LS		 94 enable-method = "psci";
95 next-level-cache = <&A53_L2>;
64d26f8c 96 operating-points-v2 = <&a53_opp_table>;
e464fd2b 97 #cooling-cells = <2>;
748f908c
LS		 98 };
99
100 A53_1: cpu@1 {
101 device_type = "cpu";
102 compatible = "arm,cortex-a53";
103 reg = <0x1>;
b810641a
AV		 104 clock-latency = <61036>; /* two CLK32 periods */
105 clocks = <&clk IMX8MQ_CLK_ARM>;
748f908c
LS		 106 enable-method = "psci";
107 next-level-cache = <&A53_L2>;
64d26f8c 108 operating-points-v2 = <&a53_opp_table>;
e464fd2b 109 #cooling-cells = <2>;
748f908c
LS		 110 };
111
112 A53_2: cpu@2 {
113 device_type = "cpu";
114 compatible = "arm,cortex-a53";
115 reg = <0x2>;
b810641a
AV		 116 clock-latency = <61036>; /* two CLK32 periods */
117 clocks = <&clk IMX8MQ_CLK_ARM>;
748f908c
LS		 118 enable-method = "psci";
119 next-level-cache = <&A53_L2>;
64d26f8c 120 operating-points-v2 = <&a53_opp_table>;
e464fd2b 121 #cooling-cells = <2>;
748f908c
LS		 122 };
123
124 A53_3: cpu@3 {
125 device_type = "cpu";
126 compatible = "arm,cortex-a53";
127 reg = <0x3>;
b810641a
AV		 128 clock-latency = <61036>; /* two CLK32 periods */
129 clocks = <&clk IMX8MQ_CLK_ARM>;
748f908c
LS		 130 enable-method = "psci";
131 next-level-cache = <&A53_L2>;
64d26f8c 132 operating-points-v2 = <&a53_opp_table>;
e464fd2b 133 #cooling-cells = <2>;
748f908c
LS		 134 };
135
136 A53_L2: l2-cache0 {
137 compatible = "cache";
138 };
139 };
140
dbde7ec3
FE		 141 a53_opp_table: opp-table {
142 compatible = "operating-points-v2";
143 opp-shared;
144
145 opp-800000000 {
146 opp-hz = /bits/ 64 <800000000>;
147 opp-microvolt = <900000>;
148 clock-latency-ns = <150000>;
149 };
150
8cfd813c
LS		 151 opp-1300000000 {
152 opp-hz = /bits/ 64 <1300000000>;
dbde7ec3
FE		 153 opp-microvolt = <1000000>;
154 clock-latency-ns = <150000>;
155 opp-suspend;
156 };
157 };
158
b3f6a5f2
CC		 159 pmu {
160 compatible = "arm,cortex-a53-pmu";
161 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
162 interrupt-parent = <&gic>;
163 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
164 };
165
748f908c
LS		 166 psci {
167 compatible = "arm,psci-1.0";
168 method = "smc";
169 };
170
cddbea8d
FE		 171 thermal-zones {
172 cpu-thermal {
173 polling-delay-passive = <250>;
174 polling-delay = <2000>;
175 thermal-sensors = <&tmu 0>;
176
177 trips {
178 cpu_alert: cpu-alert {
179 temperature = <80000>;
180 hysteresis = <2000>;
181 type = "passive";
182 };
183
184 cpu-crit {
185 temperature = <90000>;
186 hysteresis = <2000>;
187 type = "critical";
188 };
189 };
190
191 cooling-maps {
192 map0 {
193 trip = <&cpu_alert>;
194 cooling-device =
195 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
196 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
197 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
198 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
199 };
200 };
201 };
202
203 gpu-thermal {
204 polling-delay-passive = <250>;
205 polling-delay = <2000>;
206 thermal-sensors = <&tmu 1>;
207
208 trips {
209 gpu-crit {
210 temperature = <90000>;
211 hysteresis = <2000>;
212 type = "critical";
213 };
214 };
215 };
216
217 vpu-thermal {
218 polling-delay-passive = <250>;
219 polling-delay = <2000>;
220 thermal-sensors = <&tmu 2>;
221
222 trips {
223 vpu-crit {
224 temperature = <90000>;
225 hysteresis = <2000>;
226 type = "critical";
227 };
228 };
229 };
230 };
231
748f908c
LS		 232 timer {
233 compatible = "arm,armv8-timer";
234 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
235 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
236 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
237 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
238 interrupt-parent = <&gic>;
239 arm,no-tick-in-suspend;
240 };
241
242 soc@0 {
243 compatible = "simple-bus";
244 #address-cells = <1>;
245 #size-cells = <1>;
246 ranges = <0x0 0x0 0x0 0x3e000000>;
ca04fed4 247 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
748f908c
LS		 248
249 bus@30000000 { /* AIPS1 */
250 compatible = "fsl,imx8mq-aips-bus", "simple-bus";
251 #address-cells = <1>;
252 #size-cells = <1>;
253 ranges = <0x30000000 0x30000000 0x400000>;
254
255 gpio1: gpio@30200000 {
256 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
257 reg = <0x30200000 0x10000>;
258 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
259 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
580b064d 260 clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>;
748f908c
LS		 261 gpio-controller;
262 #gpio-cells = <2>;
263 interrupt-controller;
264 #interrupt-cells = <2>;
265 };
266
267 gpio2: gpio@30210000 {
268 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
269 reg = <0x30210000 0x10000>;
270 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
580b064d 272 clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>;
748f908c
LS		 273 gpio-controller;
274 #gpio-cells = <2>;
275 interrupt-controller;
276 #interrupt-cells = <2>;
277 };
278
279 gpio3: gpio@30220000 {
280 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
281 reg = <0x30220000 0x10000>;
282 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
580b064d 284 clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>;
748f908c
LS		 285 gpio-controller;
286 #gpio-cells = <2>;
287 interrupt-controller;
288 #interrupt-cells = <2>;
289 };
290
291 gpio4: gpio@30230000 {
292 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
293 reg = <0x30230000 0x10000>;
294 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
580b064d 296 clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>;
748f908c
LS		 297 gpio-controller;
298 #gpio-cells = <2>;
299 interrupt-controller;
300 #interrupt-cells = <2>;
301 };
302
303 gpio5: gpio@30240000 {
304 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
305 reg = <0x30240000 0x10000>;
306 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
580b064d 308 clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>;
748f908c
LS		 309 gpio-controller;
310 #gpio-cells = <2>;
311 interrupt-controller;
312 #interrupt-cells = <2>;
313 };
314
e464fd2b
AAP		 315 tmu: tmu@30260000 {
316 compatible = "fsl,imx8mq-tmu";
317 reg = <0x30260000 0x10000>;
318 interrupt = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
319 little-endian;
320 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
321 fsl,tmu-calibration = <0x00000000 0x00000023
322 0x00000001 0x00000029
323 0x00000002 0x0000002f
324 0x00000003 0x00000035
325 0x00000004 0x0000003d
326 0x00000005 0x00000043
327 0x00000006 0x0000004b
328 0x00000007 0x00000051
329 0x00000008 0x00000057
330 0x00000009 0x0000005f
331 0x0000000a 0x00000067
332 0x0000000b 0x0000006f
333
334 0x00010000 0x0000001b
335 0x00010001 0x00000023
336 0x00010002 0x0000002b
337 0x00010003 0x00000033
338 0x00010004 0x0000003b
339 0x00010005 0x00000043
340 0x00010006 0x0000004b
341 0x00010007 0x00000055
342 0x00010008 0x0000005d
343 0x00010009 0x00000067
344 0x0001000a 0x00000070
345
346 0x00020000 0x00000017
347 0x00020001 0x00000023
348 0x00020002 0x0000002d
349 0x00020003 0x00000037
350 0x00020004 0x00000041
351 0x00020005 0x0000004b
352 0x00020006 0x00000057
353 0x00020007 0x00000063
354 0x00020008 0x0000006f
355
356 0x00030000 0x00000015
357 0x00030001 0x00000021
358 0x00030002 0x0000002d
359 0x00030003 0x00000039
360 0x00030004 0x00000045
361 0x00030005 0x00000053
362 0x00030006 0x0000005f
363 0x00030007 0x00000071>;
364 #thermal-sensor-cells = <1>;
365 };
366
a2b91efd
LS		 367 wdog1: watchdog@30280000 {
368 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
369 reg = <0x30280000 0x10000>;
370 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>;
372 status = "disabled";
373 };
374
375 wdog2: watchdog@30290000 {
376 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
377 reg = <0x30290000 0x10000>;
378 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>;
380 status = "disabled";
381 };
382
383 wdog3: watchdog@302a0000 {
384 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
385 reg = <0x302a0000 0x10000>;
386 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>;
388 status = "disabled";
389 };
390
1474d48b
DB		 391 sdma2: sdma@302c0000 {
392 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
393 reg = <0x302c0000 0x10000>;
394 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>,
396 <&clk IMX8MQ_CLK_SDMA2_ROOT>;
397 clock-names = "ipg", "ahb";
398 #dma-cells = <3>;
399 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
400 };
401
748f908c
LS		 402 iomuxc: iomuxc@30330000 {
403 compatible = "fsl,imx8mq-iomuxc";
404 reg = <0x30330000 0x10000>;
405 };
406
407 iomuxc_gpr: syscon@30340000 {
beea0f22 408 compatible = "fsl,imx8mq-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
748f908c
LS		 409 reg = <0x30340000 0x10000>;
410 };
411
9e113b2e
CC		 412 ocotp: ocotp-ctrl@30350000 {
413 compatible = "fsl,imx8mq-ocotp", "syscon";
414 reg = <0x30350000 0x10000>;
415 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
416 #address-cells = <1>;
417 #size-cells = <1>;
418 };
419
748f908c
LS		 420 anatop: syscon@30360000 {
421 compatible = "fsl,imx8mq-anatop", "syscon";
422 reg = <0x30360000 0x10000>;
423 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
424 };
425
3ea95c31
AV		 426 snvs: snvs@30370000 {
427 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
428 reg = <0x30370000 0x10000>;
429
430 snvs_rtc: snvs-rtc-lp{
431 compatible = "fsl,sec-v4.0-mon-rtc-lp";
432 regmap =<&snvs>;
433 offset = <0x34>;
434 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
435 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
436 };
437
438 };
439
748f908c
LS		 440 clk: clock-controller@30380000 {
441 compatible = "fsl,imx8mq-ccm";
442 reg = <0x30380000 0x10000>;
443 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
445 #clock-cells = <1>;
446 clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
447 <&clk_ext1>, <&clk_ext2>,
448 <&clk_ext3>, <&clk_ext4>;
449 clock-names = "ckil", "osc_25m", "osc_27m",
450 "clk_ext1", "clk_ext2",
451 "clk_ext3", "clk_ext4";
452 };
d3a2d72b 453
d62a250e
AS		 454 src: reset-controller@30390000 {
455 compatible = "fsl,imx8mq-src", "syscon";
456 reg = <0x30390000 0x10000>;
457 #reset-cells = <1>;
458 };
459
fdbcc04d
LS		 460 gpc: gpc@303a0000 {
461 compatible = "fsl,imx8mq-gpc";
462 reg = <0x303a0000 0x10000>;
c412123f
LS		 463 interrupt-parent = <&gic>;
464 interrupt-controller;
465 #interrupt-cells = <3>;
fdbcc04d
LS		 466
467 pgc {
468 #address-cells = <1>;
469 #size-cells = <0>;
470
471 pgc_mipi: power-domain@0 {
472 #power-domain-cells = <0>;
473 reg = <IMX8M_POWER_DOMAIN_MIPI>;
474 };
475
de2a538b
AS		 476 /*
477 * As per comment in ATF source code:
478 *
479 * PCIE1 and PCIE2 share the
480 * same reset signal, if we
481 * power down PCIE2, PCIE1
482 * will be held in reset too.
483 *
484 * So instead of creating two
485 * separate power domains for
486 * PCIE1 and PCIE2 we create a
487 * link between both and use
488 * it as a shared PCIE power
489 * domain.
490 */
491 pgc_pcie: power-domain@1 {
fdbcc04d
LS		 492 #power-domain-cells = <0>;
493 reg = <IMX8M_POWER_DOMAIN_PCIE1>;
de2a538b 494 power-domains = <&pgc_pcie2>;
fdbcc04d
LS		 495 };
496
497 pgc_otg1: power-domain@2 {
498 #power-domain-cells = <0>;
499 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;
500 };
501
502 pgc_otg2: power-domain@3 {
503 #power-domain-cells = <0>;
504 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;
505 };
506
507 pgc_ddr1: power-domain@4 {
508 #power-domain-cells = <0>;
509 reg = <IMX8M_POWER_DOMAIN_DDR1>;
510 };
511
512 pgc_gpu: power-domain@5 {
513 #power-domain-cells = <0>;
514 reg = <IMX8M_POWER_DOMAIN_GPU>;
515 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
516 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
517 <&clk IMX8MQ_CLK_GPU_AXI>,
518 <&clk IMX8MQ_CLK_GPU_AHB>;
519 };
520
521 pgc_vpu: power-domain@6 {
522 #power-domain-cells = <0>;
523 reg = <IMX8M_POWER_DOMAIN_VPU>;
524 };
525
526 pgc_disp: power-domain@7 {
527 #power-domain-cells = <0>;
528 reg = <IMX8M_POWER_DOMAIN_DISP>;
529 };
530
531 pgc_mipi_csi1: power-domain@8 {
532 #power-domain-cells = <0>;
533 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;
534 };
535
536 pgc_mipi_csi2: power-domain@9 {
537 #power-domain-cells = <0>;
538 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;
539 };
540
541 pgc_pcie2: power-domain@a {
542 #power-domain-cells = <0>;
543 reg = <IMX8M_POWER_DOMAIN_PCIE2>;
544 };
545 };
546 };
748f908c
LS		 547 };
548
549 bus@30400000 { /* AIPS2 */
550 compatible = "fsl,imx8mq-aips-bus", "simple-bus";
551 #address-cells = <1>;
552 #size-cells = <1>;
553 ranges = <0x30400000 0x30400000 0x400000>;
a0e046e6
GG		 554
555 pwm1: pwm@30660000 {
556 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
557 reg = <0x30660000 0x10000>;
558 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>,
560 <&clk IMX8MQ_CLK_PWM1_ROOT>;
561 clock-names = "ipg", "per";
562 #pwm-cells = <2>;
d3a2d72b
BS		 563 status = "disabled";
564 };
565
a0e046e6
GG		 566 pwm2: pwm@30670000 {
567 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
568 reg = <0x30670000 0x10000>;
569 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>,
571 <&clk IMX8MQ_CLK_PWM2_ROOT>;
572 clock-names = "ipg", "per";
573 #pwm-cells = <2>;
d3a2d72b
BS		 574 status = "disabled";
575 };
576
a0e046e6
GG		 577 pwm3: pwm@30680000 {
578 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
579 reg = <0x30680000 0x10000>;
580 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
581 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>,
582 <&clk IMX8MQ_CLK_PWM3_ROOT>;
583 clock-names = "ipg", "per";
584 #pwm-cells = <2>;
d3a2d72b
BS		 585 status = "disabled";
586 };
748f908c 587
a0e046e6
GG		 588 pwm4: pwm@30690000 {
589 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
590 reg = <0x30690000 0x10000>;
591 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>,
593 <&clk IMX8MQ_CLK_PWM4_ROOT>;
594 clock-names = "ipg", "per";
595 #pwm-cells = <2>;
596 status = "disabled";
597 };
748f908c
LS		 598 };
599
600 bus@30800000 { /* AIPS3 */
601 compatible = "fsl,imx8mq-aips-bus", "simple-bus";
602 #address-cells = <1>;
603 #size-cells = <1>;
39f1622b
CC		 604 ranges = <0x30800000 0x30800000 0x400000>,
605 <0x08000000 0x08000000 0x10000000>;
748f908c 606
85761f45
FE		 607 ecspi1: spi@30820000 {
608 #address-cells = <1>;
609 #size-cells = <0>;
610 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
611 reg = <0x30820000 0x10000>;
612 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
614 <&clk IMX8MQ_CLK_ECSPI1_ROOT>;
615 clock-names = "ipg", "per";
616 status = "disabled";
617 };
618
619 ecspi2: spi@30830000 {
620 #address-cells = <1>;
621 #size-cells = <0>;
622 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
623 reg = <0x30830000 0x10000>;
624 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
625 clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>,
626 <&clk IMX8MQ_CLK_ECSPI2_ROOT>;
627 clock-names = "ipg", "per";
628 status = "disabled";
629 };
630
631 ecspi3: spi@30840000 {
632 #address-cells = <1>;
633 #size-cells = <0>;
634 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
635 reg = <0x30840000 0x10000>;
636 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>,
638 <&clk IMX8MQ_CLK_ECSPI3_ROOT>;
639 clock-names = "ipg", "per";
640 status = "disabled";
641 };
748f908c
LS		 642
643 uart1: serial@30860000 {
644 compatible = "fsl,imx8mq-uart",
645 "fsl,imx6q-uart";
646 reg = <0x30860000 0x10000>;
647 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
649 <&clk IMX8MQ_CLK_UART1_ROOT>;
650 clock-names = "ipg", "per";
651 status = "disabled";
652 };
653
654 uart3: serial@30880000 {
655 compatible = "fsl,imx8mq-uart",
656 "fsl,imx6q-uart";
657 reg = <0x30880000 0x10000>;
658 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
660 <&clk IMX8MQ_CLK_UART3_ROOT>;
661 clock-names = "ipg", "per";
662 status = "disabled";
663 };
664
665 uart2: serial@30890000 {
666 compatible = "fsl,imx8mq-uart",
667 "fsl,imx6q-uart";
668 reg = <0x30890000 0x10000>;
669 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
671 <&clk IMX8MQ_CLK_UART2_ROOT>;
672 clock-names = "ipg", "per";
673 status = "disabled";
674 };
675
8c61538d
DB		 676 sai2: sai@308b0000 {
677 #sound-dai-cells = <0>;
678 compatible = "fsl,imx8mq-sai",
679 "fsl,imx6sx-sai";
680 reg = <0x308b0000 0x10000>;
681 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
683 <&clk IMX8MQ_CLK_SAI2_ROOT>,
684 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>;
685 clock-names = "bus", "mclk1", "mclk2", "mclk3";
686 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
687 dma-names = "rx", "tx";
688 status = "disabled";
689 };
690
748f908c
LS		 691 i2c1: i2c@30a20000 {
692 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
693 reg = <0x30a20000 0x10000>;
694 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
695 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
696 #address-cells = <1>;
697 #size-cells = <0>;
698 status = "disabled";
699 };
700
701 i2c2: i2c@30a30000 {
702 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
703 reg = <0x30a30000 0x10000>;
704 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
705 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
706 #address-cells = <1>;
707 #size-cells = <0>;
708 status = "disabled";
709 };
710
711 i2c3: i2c@30a40000 {
712 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
713 reg = <0x30a40000 0x10000>;
714 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
716 #address-cells = <1>;
717 #size-cells = <0>;
718 status = "disabled";
719 };
720
721 i2c4: i2c@30a50000 {
722 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
723 reg = <0x30a50000 0x10000>;
724 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
726 #address-cells = <1>;
727 #size-cells = <0>;
728 status = "disabled";
729 };
730
731 uart4: serial@30a60000 {
732 compatible = "fsl,imx8mq-uart",
733 "fsl,imx6q-uart";
734 reg = <0x30a60000 0x10000>;
735 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
736 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
737 <&clk IMX8MQ_CLK_UART4_ROOT>;
738 clock-names = "ipg", "per";
739 status = "disabled";
740 };
741
742 usdhc1: mmc@30b40000 {
743 compatible = "fsl,imx8mq-usdhc",
744 "fsl,imx7d-usdhc";
745 reg = <0x30b40000 0x10000>;
746 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
747 clocks = <&clk IMX8MQ_CLK_DUMMY>,
748 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
749 <&clk IMX8MQ_CLK_USDHC1_ROOT>;
750 clock-names = "ipg", "ahb", "per";
f2ce6ed3
CC		 751 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
752 assigned-clock-rates = <400000000>;
748f908c
LS		 753 fsl,tuning-start-tap = <20>;
754 fsl,tuning-step = <2>;
755 bus-width = <4>;
756 status = "disabled";
757 };
758
759 usdhc2: mmc@30b50000 {
760 compatible = "fsl,imx8mq-usdhc",
761 "fsl,imx7d-usdhc";
762 reg = <0x30b50000 0x10000>;
763 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
764 clocks = <&clk IMX8MQ_CLK_DUMMY>,
765 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
766 <&clk IMX8MQ_CLK_USDHC2_ROOT>;
767 clock-names = "ipg", "ahb", "per";
768 fsl,tuning-start-tap = <20>;
769 fsl,tuning-step = <2>;
770 bus-width = <4>;
771 status = "disabled";
772 };
773
39f1622b
CC		 774 qspi0: spi@30bb0000 {
775 #address-cells = <1>;
776 #size-cells = <0>;
777 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
778 reg = <0x30bb0000 0x10000>,
779 <0x08000000 0x10000000>;
780 reg-names = "QuadSPI", "QuadSPI-memory";
781 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>,
783 <&clk IMX8MQ_CLK_QSPI_ROOT>;
784 clock-names = "qspi_en", "qspi";
785 status = "disabled";
786 };
787
1474d48b 788 sdma1: sdma@30bd0000 {
b6c846b9 789 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
1474d48b
DB		 790 reg = <0x30bd0000 0x10000>;
791 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>,
7240d7d4 793 <&clk IMX8MQ_CLK_AHB>;
1474d48b
DB		 794 clock-names = "ipg", "ahb";
795 #dma-cells = <3>;
796 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
797 };
798
748f908c
LS		 799 fec1: ethernet@30be0000 {
800 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
801 reg = <0x30be0000 0x10000>;
802 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
803 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
804 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
805 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
806 <&clk IMX8MQ_CLK_ENET1_ROOT>,
807 <&clk IMX8MQ_CLK_ENET_TIMER>,
808 <&clk IMX8MQ_CLK_ENET_REF>,
809 <&clk IMX8MQ_CLK_ENET_PHY_REF>;
810 clock-names = "ipg", "ahb", "ptp",
811 "enet_clk_ref", "enet_out";
812 fsl,num-tx-queues = <3>;
813 fsl,num-rx-queues = <3>;
814 status = "disabled";
815 };
816 };
817
45d2c84e
LS		 818 gpu: gpu@38000000 {
819 compatible = "vivante,gc";
820 reg = <0x38000000 0x40000>;
821 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
822 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>,
823 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>,
824 <&clk IMX8MQ_CLK_GPU_AXI>,
825 <&clk IMX8MQ_CLK_GPU_AHB>;
826 clock-names = "core", "shader", "bus", "reg";
827 assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
828 <&clk IMX8MQ_CLK_GPU_SHADER_SRC>,
829 <&clk IMX8MQ_CLK_GPU_AXI>,
ade5a57e
LS		 830 <&clk IMX8MQ_CLK_GPU_AHB>,
831 <&clk IMX8MQ_GPU_PLL_BYPASS>;
45d2c84e
LS		 832 assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
833 <&clk IMX8MQ_GPU_PLL_OUT>,
834 <&clk IMX8MQ_GPU_PLL_OUT>,
ade5a57e
LS		 835 <&clk IMX8MQ_GPU_PLL_OUT>,
836 <&clk IMX8MQ_GPU_PLL>;
45d2c84e 837 assigned-clock-rates = <800000000>, <800000000>,
ade5a57e 838 <800000000>, <800000000>, <0>;
45d2c84e
LS		 839 power-domains = <&pgc_gpu>;
840 };
841
ad37549c
LS		 842 usb_dwc3_0: usb@38100000 {
843 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
844 reg = <0x38100000 0x10000>;
845 clocks = <&clk IMX8MQ_CLK_USB_BUS>,
846 <&clk IMX8MQ_CLK_USB_CORE_REF>,
847 <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>;
848 clock-names = "bus_early", "ref", "suspend";
849 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
850 <&clk IMX8MQ_CLK_USB_CORE_REF>;
851 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
852 <&clk IMX8MQ_SYS1_PLL_100M>;
853 assigned-clock-rates = <500000000>, <100000000>;
854 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
855 phys = <&usb3_phy0>, <&usb3_phy0>;
856 phy-names = "usb2-phy", "usb3-phy";
857 power-domains = <&pgc_otg1>;
858 usb3-resume-missing-cas;
859 status = "disabled";
860 };
861
862 usb3_phy0: usb-phy@381f0040 {
863 compatible = "fsl,imx8mq-usb-phy";
864 reg = <0x381f0040 0x40>;
865 clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
866 clock-names = "phy";
867 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
868 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
869 assigned-clock-rates = <100000000>;
870 #phy-cells = <0>;
871 status = "disabled";
872 };
873
874 usb_dwc3_1: usb@38200000 {
875 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
876 reg = <0x38200000 0x10000>;
877 clocks = <&clk IMX8MQ_CLK_USB_BUS>,
878 <&clk IMX8MQ_CLK_USB_CORE_REF>,
879 <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>;
880 clock-names = "bus_early", "ref", "suspend";
881 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
882 <&clk IMX8MQ_CLK_USB_CORE_REF>;
883 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
884 <&clk IMX8MQ_SYS1_PLL_100M>;
885 assigned-clock-rates = <500000000>, <100000000>;
886 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
887 phys = <&usb3_phy1>, <&usb3_phy1>;
888 phy-names = "usb2-phy", "usb3-phy";
889 power-domains = <&pgc_otg2>;
890 usb3-resume-missing-cas;
891 status = "disabled";
892 };
893
894 usb3_phy1: usb-phy@382f0040 {
895 compatible = "fsl,imx8mq-usb-phy";
896 reg = <0x382f0040 0x40>;
897 clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
898 clock-names = "phy";
899 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
900 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
901 assigned-clock-rates = <100000000>;
902 #phy-cells = <0>;
903 status = "disabled";
904 };
905
fc26e600
AS		 906
907 pcie0: pcie@33800000 {
908 compatible = "fsl,imx8mq-pcie";
909 reg = <0x33800000 0x400000>,
910 <0x1ff00000 0x80000>;
911 reg-names = "dbi", "config";
912 #address-cells = <3>;
913 #size-cells = <2>;
914 device_type = "pci";
915 bus-range = <0x00 0xff>;
916 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
917 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
918 num-lanes = <1>;
919 num-viewport = <4>;
920 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
921 interrupt-names = "msi";
922 #interrupt-cells = <1>;
923 interrupt-map-mask = <0 0 0 0x7>;
924 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
925 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
926 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
927 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
928 fsl,max-link-speed = <2>;
929 power-domains = <&pgc_pcie>;
930 resets = <&src IMX8MQ_RESET_PCIEPHY>,
931 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
932 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
933 reset-names = "pciephy", "apps", "turnoff";
934 status = "disabled";
935 };
936
937 pcie1: pcie@33c00000 {
938 compatible = "fsl,imx8mq-pcie";
939 reg = <0x33c00000 0x400000>,
940 <0x27f00000 0x80000>;
941 reg-names = "dbi", "config";
942 #address-cells = <3>;
943 #size-cells = <2>;
944 device_type = "pci";
945 ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
946 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
947 num-lanes = <1>;
948 num-viewport = <4>;
949 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
950 interrupt-names = "msi";
951 #interrupt-cells = <1>;
952 interrupt-map-mask = <0 0 0 0x7>;
953 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
954 <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
955 <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
956 <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
957 fsl,max-link-speed = <2>;
958 power-domains = <&pgc_pcie>;
959 resets = <&src IMX8MQ_RESET_PCIEPHY2>,
960 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
961 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
962 reset-names = "pciephy", "apps", "turnoff";
963 status = "disabled";
964 };
965
748f908c
LS		 966 gic: interrupt-controller@38800000 {
967 compatible = "arm,gic-v3";
968 reg = <0x38800000 0x10000>, /* GIC Dist */
969 <0x38880000 0xc0000>, /* GICR */
970 <0x31000000 0x2000>, /* GICC */
971 <0x31010000 0x2000>, /* GICV */
972 <0x31020000 0x2000>; /* GICH */
973 #interrupt-cells = <3>;
974 interrupt-controller;
975 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
976 interrupt-parent = <&gic>;
977 };
978 };
979};
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