[mirror_ubuntu-eoan-kernel.git] / arch / arm64 / boot / dts / hisilicon / hi3660.dtsi

/*
 * dts file for Hisilicon Hi3660 SoC
 *
 * Copyright (C) 2016, Hisilicon Ltd.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/hi3660-clock.h>

/ {
	compatible = "hisilicon,hi3660";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};
			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};
				core1 {
					cpu = <&cpu5>;
				};
				core2 {
					cpu = <&cpu6>;
				};
				core3 {
					cpu = <&cpu7>;
				};
			};
		};

		cpu0: cpu@0 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			reg = <0x0 0x0>;
			enable-method = "psci";
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			reg = <0x0 0x1>;
			enable-method = "psci";
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			reg = <0x0 0x2>;
			enable-method = "psci";
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			reg = <0x0 0x3>;
			enable-method = "psci";
		};

		cpu4: cpu@100 {
			compatible = "arm,cortex-a73", "arm,armv8";
			device_type = "cpu";
			reg = <0x0 0x100>;
			enable-method = "psci";
		};

		cpu5: cpu@101 {
			compatible = "arm,cortex-a73", "arm,armv8";
			device_type = "cpu";
			reg = <0x0 0x101>;
			enable-method = "psci";
		};

		cpu6: cpu@102 {
			compatible = "arm,cortex-a73", "arm,armv8";
			device_type = "cpu";
			reg = <0x0 0x102>;
			enable-method = "psci";
		};

		cpu7: cpu@103 {
			compatible = "arm,cortex-a73", "arm,armv8";
			device_type = "cpu";
			reg = <0x0 0x103>;
			enable-method = "psci";
		};
	};

	gic: interrupt-controller@e82b0000 {
		compatible = "arm,gic-400";
		reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
		      <0x0 0xe82b2000 0 0x2000>, /* GICC */
		      <0x0 0xe82b4000 0 0x2000>, /* GICH */
		      <0x0 0xe82b6000 0 0x2000>; /* GICV */
		#address-cells = <0>;
		#interrupt-cells = <3>;
		interrupt-controller;
		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
					 IRQ_TYPE_LEVEL_HIGH)>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) |
					  IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) |
					  IRQ_TYPE_LEVEL_LOW)>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		crg_ctrl: crg_ctrl@fff35000 {
			compatible = "hisilicon,hi3660-crgctrl", "syscon";
			reg = <0x0 0xfff35000 0x0 0x1000>;
			#clock-cells = <1>;
		};

		crg_rst: crg_rst_controller {
			compatible = "hisilicon,hi3660-reset";
			#reset-cells = <2>;
			hisi,rst-syscon = <&crg_ctrl>;
		};


		pctrl: pctrl@e8a09000 {
			compatible = "hisilicon,hi3660-pctrl", "syscon";
			reg = <0x0 0xe8a09000 0x0 0x2000>;
			#clock-cells = <1>;
		};

		pmuctrl: crg_ctrl@fff34000 {
			compatible = "hisilicon,hi3660-pmuctrl", "syscon";
			reg = <0x0 0xfff34000 0x0 0x1000>;
			#clock-cells = <1>;
		};

		sctrl: sctrl@fff0a000 {
			compatible = "hisilicon,hi3660-sctrl", "syscon";
			reg = <0x0 0xfff0a000 0x0 0x1000>;
			#clock-cells = <1>;
		};

		iomcu: iomcu@ffd7e000 {
			compatible = "hisilicon,hi3660-iomcu", "syscon";
			reg = <0x0 0xffd7e000 0x0 0x1000>;
			#clock-cells = <1>;

		};

		iomcu_rst: reset {
			compatible = "hisilicon,hi3660-reset";
			hisi,rst-syscon = <&iomcu>;
			#reset-cells = <2>;
		};

		dual_timer0: timer@fff14000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x0 0xfff14000 0x0 0x1000>;
			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3660_OSC32K>,
				 <&crg_ctrl HI3660_OSC32K>,
				 <&crg_ctrl HI3660_OSC32K>;
			clock-names = "timer1", "timer2", "apb_pclk";
		};

		i2c0: i2c@ffd71000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0xffd71000 0x0 0x1000>;
			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-frequency = <400000>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
			resets = <&iomcu_rst 0x20 3>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
			status = "disabled";
		};

		i2c1: i2c@ffd72000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0xffd72000 0x0 0x1000>;
			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-frequency = <400000>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>;
			resets = <&iomcu_rst 0x20 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
			status = "disabled";
		};

		i2c3: i2c@fdf0c000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0xfdf0c000 0x0 0x1000>;
			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-frequency = <400000>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>;
			resets = <&crg_rst 0x78 7>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
			status = "disabled";
		};

		i2c7: i2c@fdf0b000 {
			compatible = "snps,designware-i2c";
			reg = <0x0 0xfdf0b000 0x0 0x1000>;
			interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-frequency = <400000>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>;
			resets = <&crg_rst 0x60 14>;
			pinctrl-names = "default";
			pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
			status = "disabled";
		};

		uart0: serial@fdf02000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xfdf02000 0x0 0x1000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
				 <&crg_ctrl HI3660_PCLK>;
			clock-names = "uartclk", "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
			status = "disabled";
		};

		uart1: serial@fdf00000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xfdf00000 0x0 0x1000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
				 <&crg_ctrl HI3660_CLK_GATE_UART1>;
			clock-names = "uartclk", "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
			status = "disabled";
		};

		uart2: serial@fdf03000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xfdf03000 0x0 0x1000>;
			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
				 <&crg_ctrl HI3660_PCLK>;
			clock-names = "uartclk", "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
			status = "disabled";
		};

		uart3: serial@ffd74000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xffd74000 0x0 0x1000>;
			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3660_FACTOR_UART3>,
				 <&crg_ctrl HI3660_PCLK>;
			clock-names = "uartclk", "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
			status = "disabled";
		};

		uart4: serial@fdf01000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xfdf01000 0x0 0x1000>;
			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
				 <&crg_ctrl HI3660_CLK_GATE_UART4>;
			clock-names = "uartclk", "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
			status = "disabled";
		};

		uart5: serial@fdf05000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xfdf05000 0x0 0x1000>;
			interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
				 <&crg_ctrl HI3660_CLK_GATE_UART5>;
			clock-names = "uartclk", "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>;
			status = "disabled";
		};

		uart6: serial@fff32000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x0 0xfff32000 0x0 0x1000>;
			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3660_CLK_UART6>,
				 <&crg_ctrl HI3660_PCLK>;
			clock-names = "uartclk", "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
			status = "disabled";
		};

		rtc0: rtc@fff04000 {
			compatible = "arm,pl031", "arm,primecell";
			reg = <0x0 0Xfff04000 0x0 0x1000>;
			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3660_PCLK>;
			clock-names = "apb_pclk";
		};

		gpio0: gpio@e8a0b000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a0b000 0 0x1000>;
			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 1 0 7>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
			clock-names = "apb_pclk";
		};

		gpio1: gpio@e8a0c000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a0c000 0 0x1000>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 1 7 7>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
			clock-names = "apb_pclk";
		};

		gpio2: gpio@e8a0d000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a0d000 0 0x1000>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 14 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
			clock-names = "apb_pclk";
		};

		gpio3: gpio@e8a0e000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a0e000 0 0x1000>;
			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 22 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
			clock-names = "apb_pclk";
		};

		gpio4: gpio@e8a0f000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a0f000 0 0x1000>;
			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 30 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
			clock-names = "apb_pclk";
		};

		gpio5: gpio@e8a10000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a10000 0 0x1000>;
			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 38 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
			clock-names = "apb_pclk";
		};

		gpio6: gpio@e8a11000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a11000 0 0x1000>;
			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 46 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
			clock-names = "apb_pclk";
		};

		gpio7: gpio@e8a12000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a12000 0 0x1000>;
			interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 54 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
			clock-names = "apb_pclk";
		};

		gpio8: gpio@e8a13000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a13000 0 0x1000>;
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 62 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
			clock-names = "apb_pclk";
		};

		gpio9: gpio@e8a14000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a14000 0 0x1000>;
			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 70 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
			clock-names = "apb_pclk";
		};

		gpio10: gpio@e8a15000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a15000 0 0x1000>;
			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 78 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
			clock-names = "apb_pclk";
		};

		gpio11: gpio@e8a16000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a16000 0 0x1000>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 86 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
			clock-names = "apb_pclk";
		};

		gpio12: gpio@e8a17000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a17000 0 0x1000>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
			clock-names = "apb_pclk";
		};

		gpio13: gpio@e8a18000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a18000 0 0x1000>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 102 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
			clock-names = "apb_pclk";
		};

		gpio14: gpio@e8a19000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a19000 0 0x1000>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 110 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
			clock-names = "apb_pclk";
		};

		gpio15: gpio@e8a1a000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a1a000 0 0x1000>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx0 0 118 6>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
			clock-names = "apb_pclk";
		};

		gpio16: gpio@e8a1b000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a1b000 0 0x1000>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
			clock-names = "apb_pclk";
		};

		gpio17: gpio@e8a1c000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a1c000 0 0x1000>;
			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
			clock-names = "apb_pclk";
		};

		gpio18: gpio@ff3b4000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xff3b4000 0 0x1000>;
			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx2 0 0 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
			clock-names = "apb_pclk";
		};

		gpio19: gpio@ff3b5000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xff3b5000 0 0x1000>;
			interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx2 0 8 4>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
			clock-names = "apb_pclk";
		};

		gpio20: gpio@e8a1f000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a1f000 0 0x1000>;
			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pmx1 0 0 6>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
			clock-names = "apb_pclk";
		};

		gpio21: gpio@e8a20000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xe8a20000 0 0x1000>;
			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			gpio-ranges = <&pmx3 0 0 6>;
			clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
			clock-names = "apb_pclk";
		};

		gpio22: gpio@fff0b000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xfff0b000 0 0x1000>;
			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			/* GPIO176 */
			gpio-ranges = <&pmx4 2 0 6>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
			clock-names = "apb_pclk";
		};

		gpio23: gpio@fff0c000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xfff0c000 0 0x1000>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			/* GPIO184 */
			gpio-ranges = <&pmx4 0 6 7>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
			clock-names = "apb_pclk";
		};

		gpio24: gpio@fff0d000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xfff0d000 0 0x1000>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			/* GPIO192 */
			gpio-ranges = <&pmx4 0 13 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3660_PCLK_AO_GPIO2>;
			clock-names = "apb_pclk";
		};

		gpio25: gpio@fff0e000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xfff0e000 0 0x1000>;
			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			/* GPIO200 */
			gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3660_PCLK_AO_GPIO3>;
			clock-names = "apb_pclk";
		};

		gpio26: gpio@fff0f000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xfff0f000 0 0x1000>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			/* GPIO208 */
			gpio-ranges = <&pmx4 0 28 8>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3660_PCLK_AO_GPIO4>;
			clock-names = "apb_pclk";
		};

		gpio27: gpio@fff10000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xfff10000 0 0x1000>;
			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			/* GPIO216 */
			gpio-ranges = <&pmx4 0 36 6>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3660_PCLK_AO_GPIO5>;
			clock-names = "apb_pclk";
		};

		gpio28: gpio@fff1d000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0 0xfff1d000 0 0x1000>;
			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&sctrl HI3660_PCLK_AO_GPIO6>;
			clock-names = "apb_pclk";
		};

		spi2: spi@ffd68000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x0 0xffd68000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>;
			clock-names = "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&spi2_pmx_func>;
			num-cs = <1>;
			cs-gpios = <&gpio27 2 0>;
			status = "disabled";
		};

		spi3: spi@ff3b3000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x0 0xff3b3000 0x0 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>;
			clock-names = "apb_pclk";
			pinctrl-names = "default";
			pinctrl-0 = <&spi3_pmx_func>;
			num-cs = <1>;
			cs-gpios = <&gpio18 5 0>;
			status = "disabled";
		};
	};
};
Commit	Line	Data
35ca8168 CF	1	/*
	2	* dts file for Hisilicon Hi3660 SoC
	3	*
	4	* Copyright (C) 2016, Hisilicon Ltd.
	5	*/
	6
	7	#include <dt-bindings/interrupt-controller/arm-gic.h>
a4e36ae0	8	#include <dt-bindings/clock/hi3660-clock.h>
35ca8168 CF	9
	10	/ {
	11	compatible = "hisilicon,hi3660";
	12	interrupt-parent = <&gic>;
	13	#address-cells = <2>;
	14	#size-cells = <2>;
	15
	16	psci {
	17	compatible = "arm,psci-0.2";
	18	method = "smc";
	19	};
	20
	21	cpus {
	22	#address-cells = <2>;
	23	#size-cells = <0>;
	24
	25	cpu-map {
	26	cluster0 {
	27	core0 {
	28	cpu = <&cpu0>;
	29	};
	30	core1 {
	31	cpu = <&cpu1>;
	32	};
	33	core2 {
	34	cpu = <&cpu2>;
	35	};
	36	core3 {
	37	cpu = <&cpu3>;
	38	};
	39	};
	40	cluster1 {
	41	core0 {
	42	cpu = <&cpu4>;
	43	};
	44	core1 {
	45	cpu = <&cpu5>;
	46	};
	47	core2 {
	48	cpu = <&cpu6>;
	49	};
	50	core3 {
	51	cpu = <&cpu7>;
	52	};
	53	};
	54	};
	55
	56	cpu0: cpu@0 {
	57	compatible = "arm,cortex-a53", "arm,armv8";
	58	device_type = "cpu";
	59	reg = <0x0 0x0>;
	60	enable-method = "psci";
	61	};
	62
	63	cpu1: cpu@1 {
	64	compatible = "arm,cortex-a53", "arm,armv8";
	65	device_type = "cpu";
	66	reg = <0x0 0x1>;
	67	enable-method = "psci";
	68	};
	69
	70	cpu2: cpu@2 {
	71	compatible = "arm,cortex-a53", "arm,armv8";
	72	device_type = "cpu";
73	reg = <0x0 0x2>;
74	enable-method = "psci";
75	};
76
77	cpu3: cpu@3 {
78	compatible = "arm,cortex-a53", "arm,armv8";
79	device_type = "cpu";
80	reg = <0x0 0x3>;
81	enable-method = "psci";
82	};
83
84	cpu4: cpu@100 {
85	compatible = "arm,cortex-a73", "arm,armv8";
86	device_type = "cpu";
87	reg = <0x0 0x100>;
88	enable-method = "psci";
89	};
90
91	cpu5: cpu@101 {
92	compatible = "arm,cortex-a73", "arm,armv8";
93	device_type = "cpu";
94	reg = <0x0 0x101>;
95	enable-method = "psci";
96	};
97
98	cpu6: cpu@102 {
99	compatible = "arm,cortex-a73", "arm,armv8";
100	device_type = "cpu";
101	reg = <0x0 0x102>;
102	enable-method = "psci";
103	};
104
105	cpu7: cpu@103 {
106	compatible = "arm,cortex-a73", "arm,armv8";
107	device_type = "cpu";
108	reg = <0x0 0x103>;
109	enable-method = "psci";
110	};
111	};
112
113	gic: interrupt-controller@e82b0000 {
114	compatible = "arm,gic-400";
115	reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */
116	<0x0 0xe82b2000 0 0x2000>, /* GICC */
117	<0x0 0xe82b4000 0 0x2000>, /* GICH */
118	<0x0 0xe82b6000 0 0x2000>; /* GICV */
119	#address-cells = <0>;
120	#interrupt-cells = <3>;
121	interrupt-controller;
122	interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) \|
123	IRQ_TYPE_LEVEL_HIGH)>;
124	};
125
126	timer {
127	compatible = "arm,armv8-timer";
128	interrupt-parent = <&gic>;
129	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) \|
130	IRQ_TYPE_LEVEL_LOW)>,
131	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) \|
132	IRQ_TYPE_LEVEL_LOW)>,
133	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) \|
134	IRQ_TYPE_LEVEL_LOW)>,
135	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) \|
136	IRQ_TYPE_LEVEL_LOW)>;
137	};
138
139	soc {
140	compatible = "simple-bus";
141	#address-cells = <2>;
142	#size-cells = <2>;
143	ranges;
144
a4e36ae0 ZG	145	crg_ctrl: crg_ctrl@fff35000 {
	146	compatible = "hisilicon,hi3660-crgctrl", "syscon";
	147	reg = <0x0 0xfff35000 0x0 0x1000>;
	148	#clock-cells = <1>;
35ca8168 CF	149	};
35ca8168 CF	150
a4e36ae0 ZG	151	crg_rst: crg_rst_controller {
	152	compatible = "hisilicon,hi3660-reset";
	153	#reset-cells = <2>;
	154	hisi,rst-syscon = <&crg_ctrl>;
	155	};
	156
	157
	158	pctrl: pctrl@e8a09000 {
	159	compatible = "hisilicon,hi3660-pctrl", "syscon";
	160	reg = <0x0 0xe8a09000 0x0 0x2000>;
	161	#clock-cells = <1>;
	162	};
	163
	164	pmuctrl: crg_ctrl@fff34000 {
	165	compatible = "hisilicon,hi3660-pmuctrl", "syscon";
	166	reg = <0x0 0xfff34000 0x0 0x1000>;
	167	#clock-cells = <1>;
	168	};
	169
	170	sctrl: sctrl@fff0a000 {
	171	compatible = "hisilicon,hi3660-sctrl", "syscon";
	172	reg = <0x0 0xfff0a000 0x0 0x1000>;
	173	#clock-cells = <1>;
	174	};
	175
	176	iomcu: iomcu@ffd7e000 {
	177	compatible = "hisilicon,hi3660-iomcu", "syscon";
	178	reg = <0x0 0xffd7e000 0x0 0x1000>;
	179	#clock-cells = <1>;
	180
	181	};
	182
	183	iomcu_rst: reset {
	184	compatible = "hisilicon,hi3660-reset";
	185	hisi,rst-syscon = <&iomcu>;
	186	#reset-cells = <2>;
	187	};
	188
75196330 LY	189	dual_timer0: timer@fff14000 {
	190	compatible = "arm,sp804", "arm,primecell";
	191	reg = <0x0 0xfff14000 0x0 0x1000>;
	192	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
	193	<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
	194	clocks = <&crg_ctrl HI3660_OSC32K>,
	195	<&crg_ctrl HI3660_OSC32K>,
	196	<&crg_ctrl HI3660_OSC32K>;
	197	clock-names = "timer1", "timer2", "apb_pclk";
	198	};
	199
5f8a3b77 ZG	200	i2c0: i2c@ffd71000 {
	201	compatible = "snps,designware-i2c";
	202	reg = <0x0 0xffd71000 0x0 0x1000>;
	203	interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
	204	#address-cells = <1>;
	205	#size-cells = <0>;
	206	clock-frequency = <400000>;
	207	clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>;
	208	resets = <&iomcu_rst 0x20 3>;
	209	pinctrl-names = "default";
	210	pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>;
	211	status = "disabled";
	212	};
	213
	214	i2c1: i2c@ffd72000 {
	215	compatible = "snps,designware-i2c";
	216	reg = <0x0 0xffd72000 0x0 0x1000>;
	217	interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
	218	#address-cells = <1>;
	219	#size-cells = <0>;
	220	clock-frequency = <400000>;
	221	clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>;
	222	resets = <&iomcu_rst 0x20 4>;
	223	pinctrl-names = "default";
	224	pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>;
	225	status = "disabled";
	226	};
	227
	228	i2c3: i2c@fdf0c000 {
	229	compatible = "snps,designware-i2c";
	230	reg = <0x0 0xfdf0c000 0x0 0x1000>;
	231	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
	232	#address-cells = <1>;
	233	#size-cells = <0>;
	234	clock-frequency = <400000>;
	235	clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>;
	236	resets = <&crg_rst 0x78 7>;
	237	pinctrl-names = "default";
	238	pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>;
	239	status = "disabled";
	240	};
	241
	242	i2c7: i2c@fdf0b000 {
	243	compatible = "snps,designware-i2c";
	244	reg = <0x0 0xfdf0b000 0x0 0x1000>;
	245	interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
	246	#address-cells = <1>;
	247	#size-cells = <0>;
	248	clock-frequency = <400000>;
	249	clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>;
	250	resets = <&crg_rst 0x60 14>;
	251	pinctrl-names = "default";
	252	pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>;
	253	status = "disabled";
	254	};
	255
254b07b2 CF	256	uart0: serial@fdf02000 {
	257	compatible = "arm,pl011", "arm,primecell";
	258	reg = <0x0 0xfdf02000 0x0 0x1000>;
	259	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
	260	clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>,
	261	<&crg_ctrl HI3660_PCLK>;
	262	clock-names = "uartclk", "apb_pclk";
	263	pinctrl-names = "default";
	264	pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>;
	265	status = "disabled";
	266	};
	267
	268	uart1: serial@fdf00000 {
	269	compatible = "arm,pl011", "arm,primecell";
	270	reg = <0x0 0xfdf00000 0x0 0x1000>;
	271	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
	272	clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>,
	273	<&crg_ctrl HI3660_CLK_GATE_UART1>;
	274	clock-names = "uartclk", "apb_pclk";
	275	pinctrl-names = "default";
	276	pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>;
	277	status = "disabled";
	278	};
	279
	280	uart2: serial@fdf03000 {
	281	compatible = "arm,pl011", "arm,primecell";
	282	reg = <0x0 0xfdf03000 0x0 0x1000>;
	283	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
	284	clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>,
	285	<&crg_ctrl HI3660_PCLK>;
	286	clock-names = "uartclk", "apb_pclk";
	287	pinctrl-names = "default";
	288	pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>;
	289	status = "disabled";
	290	};
	291
	292	uart3: serial@ffd74000 {
	293	compatible = "arm,pl011", "arm,primecell";
	294	reg = <0x0 0xffd74000 0x0 0x1000>;
	295	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	296	clocks = <&crg_ctrl HI3660_FACTOR_UART3>,
	297	<&crg_ctrl HI3660_PCLK>;
	298	clock-names = "uartclk", "apb_pclk";
	299	pinctrl-names = "default";
	300	pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>;
	301	status = "disabled";
	302	};
	303
	304	uart4: serial@fdf01000 {
	305	compatible = "arm,pl011", "arm,primecell";
	306	reg = <0x0 0xfdf01000 0x0 0x1000>;
	307	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
	308	clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>,
	309	<&crg_ctrl HI3660_CLK_GATE_UART4>;
	310	clock-names = "uartclk", "apb_pclk";
	311	pinctrl-names = "default";
	312	pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>;
	313	status = "disabled";
	314	};
	315
a4e36ae0	316	uart5: serial@fdf05000 {
35ca8168 CF	317	compatible = "arm,pl011", "arm,primecell";
	318	reg = <0x0 0xfdf05000 0x0 0x1000>;
	319	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
a4e36ae0 ZG	320	clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>,
a4e36ae0 ZG	321	<&crg_ctrl HI3660_CLK_GATE_UART5>;
35ca8168	322	clock-names = "uartclk", "apb_pclk";
254b07b2 CF	323	pinctrl-names = "default";
	324	pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>;
	325	status = "disabled";
	326	};
	327
	328	uart6: serial@fff32000 {
	329	compatible = "arm,pl011", "arm,primecell";
	330	reg = <0x0 0xfff32000 0x0 0x1000>;
	331	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
	332	clocks = <&crg_ctrl HI3660_CLK_UART6>,
	333	<&crg_ctrl HI3660_PCLK>;
	334	clock-names = "uartclk", "apb_pclk";
	335	pinctrl-names = "default";
	336	pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>;
35ca8168 CF	337	status = "disabled";
35ca8168 CF	338	};
d94eab86	339
0a0698f6 CF	340	rtc0: rtc@fff04000 {
	341	compatible = "arm,pl031", "arm,primecell";
	342	reg = <0x0 0Xfff04000 0x0 0x1000>;
	343	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
	344	clocks = <&crg_ctrl HI3660_PCLK>;
	345	clock-names = "apb_pclk";
	346	};
	347
d94eab86 WX	348	gpio0: gpio@e8a0b000 {
	349	compatible = "arm,pl061", "arm,primecell";
	350	reg = <0 0xe8a0b000 0 0x1000>;
	351	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	352	gpio-controller;
	353	#gpio-cells = <2>;
	354	gpio-ranges = <&pmx0 1 0 7>;
	355	interrupt-controller;
	356	#interrupt-cells = <2>;
	357	clocks = <&crg_ctrl HI3660_PCLK_GPIO0>;
	358	clock-names = "apb_pclk";
	359	};
	360
	361	gpio1: gpio@e8a0c000 {
	362	compatible = "arm,pl061", "arm,primecell";
	363	reg = <0 0xe8a0c000 0 0x1000>;
	364	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
	365	gpio-controller;
	366	#gpio-cells = <2>;
	367	gpio-ranges = <&pmx0 1 7 7>;
	368	interrupt-controller;
	369	#interrupt-cells = <2>;
	370	clocks = <&crg_ctrl HI3660_PCLK_GPIO1>;
	371	clock-names = "apb_pclk";
	372	};
	373
	374	gpio2: gpio@e8a0d000 {
	375	compatible = "arm,pl061", "arm,primecell";
	376	reg = <0 0xe8a0d000 0 0x1000>;
	377	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
	378	gpio-controller;
	379	#gpio-cells = <2>;
	380	gpio-ranges = <&pmx0 0 14 8>;
	381	interrupt-controller;
	382	#interrupt-cells = <2>;
	383	clocks = <&crg_ctrl HI3660_PCLK_GPIO2>;
	384	clock-names = "apb_pclk";
	385	};
	386
	387	gpio3: gpio@e8a0e000 {
	388	compatible = "arm,pl061", "arm,primecell";
	389	reg = <0 0xe8a0e000 0 0x1000>;
	390	interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
	391	gpio-controller;
	392	#gpio-cells = <2>;
	393	gpio-ranges = <&pmx0 0 22 8>;
	394	interrupt-controller;
	395	#interrupt-cells = <2>;
	396	clocks = <&crg_ctrl HI3660_PCLK_GPIO3>;
	397	clock-names = "apb_pclk";
	398	};
	399
	400	gpio4: gpio@e8a0f000 {
	401	compatible = "arm,pl061", "arm,primecell";
	402	reg = <0 0xe8a0f000 0 0x1000>;
	403	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
	404	gpio-controller;
	405	#gpio-cells = <2>;
	406	gpio-ranges = <&pmx0 0 30 8>;
	407	interrupt-controller;
	408	#interrupt-cells = <2>;
	409	clocks = <&crg_ctrl HI3660_PCLK_GPIO4>;
	410	clock-names = "apb_pclk";
	411	};
412
413	gpio5: gpio@e8a10000 {
414	compatible = "arm,pl061", "arm,primecell";
415	reg = <0 0xe8a10000 0 0x1000>;
416	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
417	gpio-controller;
418	#gpio-cells = <2>;
419	gpio-ranges = <&pmx0 0 38 8>;
420	interrupt-controller;
421	#interrupt-cells = <2>;
422	clocks = <&crg_ctrl HI3660_PCLK_GPIO5>;
423	clock-names = "apb_pclk";
424	};
425
426	gpio6: gpio@e8a11000 {
427	compatible = "arm,pl061", "arm,primecell";
428	reg = <0 0xe8a11000 0 0x1000>;
429	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
430	gpio-controller;
431	#gpio-cells = <2>;
432	gpio-ranges = <&pmx0 0 46 8>;
433	interrupt-controller;
434	#interrupt-cells = <2>;
435	clocks = <&crg_ctrl HI3660_PCLK_GPIO6>;
436	clock-names = "apb_pclk";
437	};
438
439	gpio7: gpio@e8a12000 {
440	compatible = "arm,pl061", "arm,primecell";
441	reg = <0 0xe8a12000 0 0x1000>;
442	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
443	gpio-controller;
444	#gpio-cells = <2>;
445	gpio-ranges = <&pmx0 0 54 8>;
446	interrupt-controller;
447	#interrupt-cells = <2>;
448	clocks = <&crg_ctrl HI3660_PCLK_GPIO7>;
449	clock-names = "apb_pclk";
450	};
451
452	gpio8: gpio@e8a13000 {
453	compatible = "arm,pl061", "arm,primecell";
454	reg = <0 0xe8a13000 0 0x1000>;
455	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
456	gpio-controller;
457	#gpio-cells = <2>;
458	gpio-ranges = <&pmx0 0 62 8>;
459	interrupt-controller;
460	#interrupt-cells = <2>;
461	clocks = <&crg_ctrl HI3660_PCLK_GPIO8>;
462	clock-names = "apb_pclk";
463	};
464
465	gpio9: gpio@e8a14000 {
466	compatible = "arm,pl061", "arm,primecell";
467	reg = <0 0xe8a14000 0 0x1000>;
468	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
469	gpio-controller;
470	#gpio-cells = <2>;
471	gpio-ranges = <&pmx0 0 70 8>;
472	interrupt-controller;
473	#interrupt-cells = <2>;
474	clocks = <&crg_ctrl HI3660_PCLK_GPIO9>;
475	clock-names = "apb_pclk";
476	};
477
478	gpio10: gpio@e8a15000 {
479	compatible = "arm,pl061", "arm,primecell";
480	reg = <0 0xe8a15000 0 0x1000>;
481	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
482	gpio-controller;
483	#gpio-cells = <2>;
484	gpio-ranges = <&pmx0 0 78 8>;
485	interrupt-controller;
486	#interrupt-cells = <2>;
487	clocks = <&crg_ctrl HI3660_PCLK_GPIO10>;
488	clock-names = "apb_pclk";
489	};
490
491	gpio11: gpio@e8a16000 {
492	compatible = "arm,pl061", "arm,primecell";
493	reg = <0 0xe8a16000 0 0x1000>;
494	interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
495	gpio-controller;
496	#gpio-cells = <2>;
497	gpio-ranges = <&pmx0 0 86 8>;
498	interrupt-controller;
499	#interrupt-cells = <2>;
500	clocks = <&crg_ctrl HI3660_PCLK_GPIO11>;
501	clock-names = "apb_pclk";
502	};
503
504	gpio12: gpio@e8a17000 {
505	compatible = "arm,pl061", "arm,primecell";
506	reg = <0 0xe8a17000 0 0x1000>;
507	interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
508	gpio-controller;
509	#gpio-cells = <2>;
510	gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>;
511	interrupt-controller;
512	#interrupt-cells = <2>;
513	clocks = <&crg_ctrl HI3660_PCLK_GPIO12>;
514	clock-names = "apb_pclk";
515	};
516
517	gpio13: gpio@e8a18000 {
518	compatible = "arm,pl061", "arm,primecell";
519	reg = <0 0xe8a18000 0 0x1000>;
520	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
521	gpio-controller;
522	#gpio-cells = <2>;
523	gpio-ranges = <&pmx0 0 102 8>;
524	interrupt-controller;
525	#interrupt-cells = <2>;
526	clocks = <&crg_ctrl HI3660_PCLK_GPIO13>;
527	clock-names = "apb_pclk";
528	};
529
530	gpio14: gpio@e8a19000 {
531	compatible = "arm,pl061", "arm,primecell";
532	reg = <0 0xe8a19000 0 0x1000>;
533	interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
534	gpio-controller;
535	#gpio-cells = <2>;
536	gpio-ranges = <&pmx0 0 110 8>;
537	interrupt-controller;
538	#interrupt-cells = <2>;
539	clocks = <&crg_ctrl HI3660_PCLK_GPIO14>;
540	clock-names = "apb_pclk";
541	};
542
543	gpio15: gpio@e8a1a000 {
544	compatible = "arm,pl061", "arm,primecell";
545	reg = <0 0xe8a1a000 0 0x1000>;
546	interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
547	gpio-controller;
548	#gpio-cells = <2>;
549	gpio-ranges = <&pmx0 0 118 6>;
550	interrupt-controller;
551	#interrupt-cells = <2>;
552	clocks = <&crg_ctrl HI3660_PCLK_GPIO15>;
553	clock-names = "apb_pclk";
554	};
555
556	gpio16: gpio@e8a1b000 {
557	compatible = "arm,pl061", "arm,primecell";
558	reg = <0 0xe8a1b000 0 0x1000>;
559	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
560	gpio-controller;
561	#gpio-cells = <2>;
562	interrupt-controller;
563	#interrupt-cells = <2>;
564	clocks = <&crg_ctrl HI3660_PCLK_GPIO16>;
565	clock-names = "apb_pclk";
566	};
567
568	gpio17: gpio@e8a1c000 {
569	compatible = "arm,pl061", "arm,primecell";
570	reg = <0 0xe8a1c000 0 0x1000>;
571	interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
572	gpio-controller;
573	#gpio-cells = <2>;
574	interrupt-controller;
575	#interrupt-cells = <2>;
576	clocks = <&crg_ctrl HI3660_PCLK_GPIO17>;
577	clock-names = "apb_pclk";
578	};
579
580	gpio18: gpio@ff3b4000 {
581	compatible = "arm,pl061", "arm,primecell";
582	reg = <0 0xff3b4000 0 0x1000>;
583	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
584	gpio-controller;
585	#gpio-cells = <2>;
586	gpio-ranges = <&pmx2 0 0 8>;
587	interrupt-controller;
588	#interrupt-cells = <2>;
589	clocks = <&crg_ctrl HI3660_PCLK_GPIO18>;
590	clock-names = "apb_pclk";
591	};
592
593	gpio19: gpio@ff3b5000 {
594	compatible = "arm,pl061", "arm,primecell";
595	reg = <0 0xff3b5000 0 0x1000>;
596	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
597	gpio-controller;
598	#gpio-cells = <2>;
599	gpio-ranges = <&pmx2 0 8 4>;
600	interrupt-controller;
601	#interrupt-cells = <2>;
602	clocks = <&crg_ctrl HI3660_PCLK_GPIO19>;
603	clock-names = "apb_pclk";
604	};
605
606	gpio20: gpio@e8a1f000 {
607	compatible = "arm,pl061", "arm,primecell";
608	reg = <0 0xe8a1f000 0 0x1000>;
609	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
610	gpio-controller;
611	#gpio-cells = <2>;
612	gpio-ranges = <&pmx1 0 0 6>;
613	interrupt-controller;
614	#interrupt-cells = <2>;
615	clocks = <&crg_ctrl HI3660_PCLK_GPIO20>;
616	clock-names = "apb_pclk";
617	};
618
619	gpio21: gpio@e8a20000 {
620	compatible = "arm,pl061", "arm,primecell";
621	reg = <0 0xe8a20000 0 0x1000>;
622	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
623	gpio-controller;
624	#gpio-cells = <2>;
625	interrupt-controller;
626	#interrupt-cells = <2>;
627	gpio-ranges = <&pmx3 0 0 6>;
628	clocks = <&crg_ctrl HI3660_PCLK_GPIO21>;
629	clock-names = "apb_pclk";
630	};
631
632	gpio22: gpio@fff0b000 {
633	compatible = "arm,pl061", "arm,primecell";
634	reg = <0 0xfff0b000 0 0x1000>;
635	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
636	gpio-controller;
637	#gpio-cells = <2>;
638	/* GPIO176 */
639	gpio-ranges = <&pmx4 2 0 6>;
640	interrupt-controller;
641	#interrupt-cells = <2>;
642	clocks = <&sctrl HI3660_PCLK_AO_GPIO0>;
643	clock-names = "apb_pclk";
644	};
645
646	gpio23: gpio@fff0c000 {
647	compatible = "arm,pl061", "arm,primecell";
648	reg = <0 0xfff0c000 0 0x1000>;
649	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
650	gpio-controller;
651	#gpio-cells = <2>;
652	/* GPIO184 */
653	gpio-ranges = <&pmx4 0 6 7>;
654	interrupt-controller;
655	#interrupt-cells = <2>;
656	clocks = <&sctrl HI3660_PCLK_AO_GPIO1>;
657	clock-names = "apb_pclk";
658	};
659
660	gpio24: gpio@fff0d000 {
661	compatible = "arm,pl061", "arm,primecell";
662	reg = <0 0xfff0d000 0 0x1000>;
663	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
664	gpio-controller;
665	#gpio-cells = <2>;
666	/* GPIO192 */
667	gpio-ranges = <&pmx4 0 13 8>;
668	interrupt-controller;
669	#interrupt-cells = <2>;
670	clocks = <&sctrl HI3660_PCLK_AO_GPIO2>;
671	clock-names = "apb_pclk";
672	};
673
674	gpio25: gpio@fff0e000 {
675	compatible = "arm,pl061", "arm,primecell";
676	reg = <0 0xfff0e000 0 0x1000>;
677	interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
678	gpio-controller;
679	#gpio-cells = <2>;
680	/* GPIO200 */
681	gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>;
682	interrupt-controller;
683	#interrupt-cells = <2>;
684	clocks = <&sctrl HI3660_PCLK_AO_GPIO3>;
685	clock-names = "apb_pclk";
686	};
687
688	gpio26: gpio@fff0f000 {
689	compatible = "arm,pl061", "arm,primecell";
690	reg = <0 0xfff0f000 0 0x1000>;
691	interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
692	gpio-controller;
693	#gpio-cells = <2>;
694	/* GPIO208 */
695	gpio-ranges = <&pmx4 0 28 8>;
696	interrupt-controller;
697	#interrupt-cells = <2>;
698	clocks = <&sctrl HI3660_PCLK_AO_GPIO4>;
699	clock-names = "apb_pclk";
700	};
701
702	gpio27: gpio@fff10000 {
703	compatible = "arm,pl061", "arm,primecell";
704	reg = <0 0xfff10000 0 0x1000>;
705	interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
706	gpio-controller;
707	#gpio-cells = <2>;
708	/* GPIO216 */
709	gpio-ranges = <&pmx4 0 36 6>;
710	interrupt-controller;
711	#interrupt-cells = <2>;
712	clocks = <&sctrl HI3660_PCLK_AO_GPIO5>;
713	clock-names = "apb_pclk";
714	};
715
716	gpio28: gpio@fff1d000 {
717	compatible = "arm,pl061", "arm,primecell";
718	reg = <0 0xfff1d000 0 0x1000>;
719	interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
720	gpio-controller;
721	#gpio-cells = <2>;
722	interrupt-controller;
723	#interrupt-cells = <2>;
724	clocks = <&sctrl HI3660_PCLK_AO_GPIO6>;
725	clock-names = "apb_pclk";
726	};
38810497 WX	727
	728	spi2: spi@ffd68000 {
	729	compatible = "arm,pl022", "arm,primecell";
	730	reg = <0x0 0xffd68000 0x0 0x1000>;
	731	#address-cells = <1>;
	732	#size-cells = <0>;
	733	interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
	734	clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>;
	735	clock-names = "apb_pclk";
	736	pinctrl-names = "default";
	737	pinctrl-0 = <&spi2_pmx_func>;
	738	num-cs = <1>;
	739	cs-gpios = <&gpio27 2 0>;
	740	status = "disabled";
	741	};
	742
	743	spi3: spi@ff3b3000 {
	744	compatible = "arm,pl022", "arm,primecell";
	745	reg = <0x0 0xff3b3000 0x0 0x1000>;
	746	#address-cells = <1>;
	747	#size-cells = <0>;
	748	interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
	749	clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>;
	750	clock-names = "apb_pclk";
	751	pinctrl-names = "default";
	752	pinctrl-0 = <&spi3_pmx_func>;
	753	num-cs = <1>;
	754	cs-gpios = <&gpio18 5 0>;
	755	status = "disabled";
	756	};
35ca8168 CF	757	};
35ca8168 CF	758	};