[mirror_ubuntu-jammy-kernel.git] / arch / arm64 / boot / dts / hisilicon / hip05.dtsi

// SPDX-License-Identifier: GPL-2.0-only
/**
 * dts file for Hisilicon D02 Development Board
 *
 * Copyright (C) 2014,2015 Hisilicon Ltd.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "hisilicon,hip05-d02";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
			};
			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};
				core1 {
					cpu = <&cpu5>;
				};
				core2 {
					cpu = <&cpu6>;
				};
				core3 {
					cpu = <&cpu7>;
				};
			};
			cluster2 {
				core0 {
					cpu = <&cpu8>;
				};
				core1 {
					cpu = <&cpu9>;
				};
				core2 {
					cpu = <&cpu10>;
				};
				core3 {
					cpu = <&cpu11>;
				};
			};
			cluster3 {
				core0 {
					cpu = <&cpu12>;
				};
				core1 {
					cpu = <&cpu13>;
				};
				core2 {
					cpu = <&cpu14>;
				};
				core3 {
					cpu = <&cpu15>;
				};
			};
		};

		cpu0: cpu@20000 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20000>;
			enable-method = "psci";
			next-level-cache = <&cluster0_l2>;
		};

		cpu1: cpu@20001 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20001>;
			enable-method = "psci";
			next-level-cache = <&cluster0_l2>;
		};

		cpu2: cpu@20002 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20002>;
			enable-method = "psci";
			next-level-cache = <&cluster0_l2>;
		};

		cpu3: cpu@20003 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20003>;
			enable-method = "psci";
			next-level-cache = <&cluster0_l2>;
		};

		cpu4: cpu@20100 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20100>;
			enable-method = "psci";
			next-level-cache = <&cluster1_l2>;
		};

		cpu5: cpu@20101 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20101>;
			enable-method = "psci";
			next-level-cache = <&cluster1_l2>;
		};

		cpu6: cpu@20102 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20102>;
			enable-method = "psci";
			next-level-cache = <&cluster1_l2>;
		};

		cpu7: cpu@20103 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20103>;
			enable-method = "psci";
			next-level-cache = <&cluster1_l2>;
		};

		cpu8: cpu@20200 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20200>;
			enable-method = "psci";
			next-level-cache = <&cluster2_l2>;
		};

		cpu9: cpu@20201 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20201>;
			enable-method = "psci";
			next-level-cache = <&cluster2_l2>;
		};

		cpu10: cpu@20202 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20202>;
			enable-method = "psci";
			next-level-cache = <&cluster2_l2>;
		};

		cpu11: cpu@20203 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20203>;
			enable-method = "psci";
			next-level-cache = <&cluster2_l2>;
		};

		cpu12: cpu@20300 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20300>;
			enable-method = "psci";
			next-level-cache = <&cluster3_l2>;
		};

		cpu13: cpu@20301 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20301>;
			enable-method = "psci";
			next-level-cache = <&cluster3_l2>;
		};

		cpu14: cpu@20302 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20302>;
			enable-method = "psci";
			next-level-cache = <&cluster3_l2>;
		};

		cpu15: cpu@20303 {
			device_type = "cpu";
			compatible = "arm,cortex-a57";
			reg = <0x20303>;
			enable-method = "psci";
			next-level-cache = <&cluster3_l2>;
		};

		cluster0_l2: l2-cache0 {
			compatible = "cache";
		};

		cluster1_l2: l2-cache1 {
			compatible = "cache";
		};

		cluster2_l2: l2-cache2 {
			compatible = "cache";
		};

		cluster3_l2: l2-cache3 {
			compatible = "cache";
		};
	};

	gic: interrupt-controller@8d000000 {
		compatible = "arm,gic-v3";
                #interrupt-cells = <3>;
                #address-cells = <2>;
                #size-cells = <2>;
                ranges;
                interrupt-controller;
                #redistributor-regions = <1>;
                redistributor-stride = <0x0 0x30000>;
		reg = <0x0 0x8d000000 0 0x10000>,	/* GICD */
		      <0x0 0x8d100000 0 0x300000>,	/* GICR */
		      <0x0 0xfe000000 0 0x10000>,	/* GICC */
		      <0x0 0xfe010000 0 0x10000>,       /* GICH */
		      <0x0 0xfe020000 0 0x10000>;       /* GICV */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		its_peri: interrupt-controller@8c000000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			#msi-cells = <1>;
			reg = <0x0 0x8c000000 0x0 0x40000>;
		};

		its_m3: interrupt-controller@a3000000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			#msi-cells = <1>;
			reg = <0x0 0xa3000000 0x0 0x40000>;
		};

		its_pcie: interrupt-controller@b7000000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			#msi-cells = <1>;
			reg = <0x0 0xb7000000 0x0 0x40000>;
		};

		its_dsa: interrupt-controller@c6000000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			#msi-cells = <1>;
			reg = <0x0 0xc6000000 0x0 0x40000>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};

	pmu {
		compatible = "arm,cortex-a57-pmu";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		refclk200mhz: refclk200mhz {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <200000000>;
		};

		uart0: uart@80300000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x0 0x80300000 0x0 0x10000>;
			interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&refclk200mhz>;
			clock-names = "apb_pclk";
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		uart1: uart@80310000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x0 0x80310000 0x0 0x10000>;
			interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&refclk200mhz>;
			clock-names = "apb_pclk";
			reg-shift = <2>;
			reg-io-width = <4>;
			status = "disabled";
		};

		lbc: localbus@80380000 {
			compatible = "hisilicon,hisi-localbus", "simple-bus";
			reg = <0x0 0x80380000 0x0 0x10000>;
			status = "disabled";
		};

		peri_gpio0: gpio@802e0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0x0 0x802e0000 0x0 0x10000>;
			status = "disabled";

			porta: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		peri_gpio1: gpio@802f0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,dw-apb-gpio";
			reg = <0x0 0x802f0000 0x0 0x10000>;
			status = "disabled";

			portb: gpio-controller@0 {
				compatible = "snps,dw-apb-gpio-port";
				gpio-controller;
				#gpio-cells = <2>;
				snps,nr-gpios = <32>;
				reg = <0>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>;
			};
		};
	};
};
Commit	Line	Data
1d0ea069	1	// SPDX-License-Identifier: GPL-2.0-only
fcab303c DT	2	/**
	3	* dts file for Hisilicon D02 Development Board
	4	*
	5	* Copyright (C) 2014,2015 Hisilicon Ltd.
fcab303c DT	6	*/
	7
	8	#include <dt-bindings/interrupt-controller/arm-gic.h>
	9
	10	/ {
	11	compatible = "hisilicon,hip05-d02";
	12	interrupt-parent = <&gic>;
	13	#address-cells = <2>;
	14	#size-cells = <2>;
	15
	16	psci {
	17	compatible = "arm,psci-0.2";
	18	method = "smc";
	19	};
	20
	21	cpus {
	22	#address-cells = <1>;
	23	#size-cells = <0>;
	24
	25	cpu-map {
	26	cluster0 {
	27	core0 {
	28	cpu = <&cpu0>;
	29	};
	30	core1 {
	31	cpu = <&cpu1>;
	32	};
	33	core2 {
	34	cpu = <&cpu2>;
	35	};
	36	core3 {
	37	cpu = <&cpu3>;
	38	};
	39	};
	40	cluster1 {
	41	core0 {
	42	cpu = <&cpu4>;
	43	};
	44	core1 {
	45	cpu = <&cpu5>;
	46	};
	47	core2 {
	48	cpu = <&cpu6>;
	49	};
	50	core3 {
	51	cpu = <&cpu7>;
	52	};
	53	};
	54	cluster2 {
	55	core0 {
	56	cpu = <&cpu8>;
	57	};
	58	core1 {
	59	cpu = <&cpu9>;
	60	};
	61	core2 {
	62	cpu = <&cpu10>;
	63	};
	64	core3 {
	65	cpu = <&cpu11>;
	66	};
	67	};
	68	cluster3 {
	69	core0 {
70	cpu = <&cpu12>;
71	};
72	core1 {
73	cpu = <&cpu13>;
74	};
75	core2 {
76	cpu = <&cpu14>;
77	};
78	core3 {
79	cpu = <&cpu15>;
80	};
81	};
82	};
83
84	cpu0: cpu@20000 {
85	device_type = "cpu";
31af04cd	86	compatible = "arm,cortex-a57";
fcab303c DT	87	reg = <0x20000>;
fcab303c DT	88	enable-method = "psci";
dbb58d0f	89	next-level-cache = <&cluster0_l2>;
fcab303c DT	90	};
	91
	92	cpu1: cpu@20001 {
	93	device_type = "cpu";
31af04cd	94	compatible = "arm,cortex-a57";
fcab303c DT	95	reg = <0x20001>;
fcab303c DT	96	enable-method = "psci";
dbb58d0f	97	next-level-cache = <&cluster0_l2>;
fcab303c DT	98	};
	99
	100	cpu2: cpu@20002 {
	101	device_type = "cpu";
31af04cd	102	compatible = "arm,cortex-a57";
fcab303c DT	103	reg = <0x20002>;
fcab303c DT	104	enable-method = "psci";
dbb58d0f	105	next-level-cache = <&cluster0_l2>;
fcab303c DT	106	};
	107
	108	cpu3: cpu@20003 {
	109	device_type = "cpu";
31af04cd	110	compatible = "arm,cortex-a57";
fcab303c DT	111	reg = <0x20003>;
fcab303c DT	112	enable-method = "psci";
dbb58d0f	113	next-level-cache = <&cluster0_l2>;
fcab303c DT	114	};
	115
	116	cpu4: cpu@20100 {
	117	device_type = "cpu";
31af04cd	118	compatible = "arm,cortex-a57";
fcab303c DT	119	reg = <0x20100>;
fcab303c DT	120	enable-method = "psci";
dbb58d0f	121	next-level-cache = <&cluster1_l2>;
fcab303c DT	122	};
	123
	124	cpu5: cpu@20101 {
	125	device_type = "cpu";
31af04cd	126	compatible = "arm,cortex-a57";
fcab303c DT	127	reg = <0x20101>;
fcab303c DT	128	enable-method = "psci";
dbb58d0f	129	next-level-cache = <&cluster1_l2>;
fcab303c DT	130	};
	131
	132	cpu6: cpu@20102 {
	133	device_type = "cpu";
31af04cd	134	compatible = "arm,cortex-a57";
fcab303c DT	135	reg = <0x20102>;
fcab303c DT	136	enable-method = "psci";
dbb58d0f	137	next-level-cache = <&cluster1_l2>;
fcab303c DT	138	};
	139
	140	cpu7: cpu@20103 {
	141	device_type = "cpu";
31af04cd	142	compatible = "arm,cortex-a57";
fcab303c DT	143	reg = <0x20103>;
fcab303c DT	144	enable-method = "psci";
dbb58d0f	145	next-level-cache = <&cluster1_l2>;
fcab303c DT	146	};
	147
	148	cpu8: cpu@20200 {
	149	device_type = "cpu";
31af04cd	150	compatible = "arm,cortex-a57";
fcab303c DT	151	reg = <0x20200>;
fcab303c DT	152	enable-method = "psci";
dbb58d0f	153	next-level-cache = <&cluster2_l2>;
fcab303c DT	154	};
	155
	156	cpu9: cpu@20201 {
	157	device_type = "cpu";
31af04cd	158	compatible = "arm,cortex-a57";
fcab303c DT	159	reg = <0x20201>;
fcab303c DT	160	enable-method = "psci";
dbb58d0f	161	next-level-cache = <&cluster2_l2>;
fcab303c DT	162	};
	163
	164	cpu10: cpu@20202 {
	165	device_type = "cpu";
31af04cd	166	compatible = "arm,cortex-a57";
fcab303c DT	167	reg = <0x20202>;
fcab303c DT	168	enable-method = "psci";
dbb58d0f	169	next-level-cache = <&cluster2_l2>;
fcab303c DT	170	};
	171
	172	cpu11: cpu@20203 {
	173	device_type = "cpu";
31af04cd	174	compatible = "arm,cortex-a57";
fcab303c DT	175	reg = <0x20203>;
fcab303c DT	176	enable-method = "psci";
dbb58d0f	177	next-level-cache = <&cluster2_l2>;
fcab303c DT	178	};
	179
	180	cpu12: cpu@20300 {
	181	device_type = "cpu";
31af04cd	182	compatible = "arm,cortex-a57";
fcab303c DT	183	reg = <0x20300>;
fcab303c DT	184	enable-method = "psci";
dbb58d0f	185	next-level-cache = <&cluster3_l2>;
fcab303c DT	186	};
	187
	188	cpu13: cpu@20301 {
	189	device_type = "cpu";
31af04cd	190	compatible = "arm,cortex-a57";
fcab303c DT	191	reg = <0x20301>;
fcab303c DT	192	enable-method = "psci";
dbb58d0f	193	next-level-cache = <&cluster3_l2>;
fcab303c DT	194	};
	195
	196	cpu14: cpu@20302 {
	197	device_type = "cpu";
31af04cd	198	compatible = "arm,cortex-a57";
fcab303c DT	199	reg = <0x20302>;
fcab303c DT	200	enable-method = "psci";
dbb58d0f	201	next-level-cache = <&cluster3_l2>;
fcab303c DT	202	};
	203
	204	cpu15: cpu@20303 {
	205	device_type = "cpu";
31af04cd	206	compatible = "arm,cortex-a57";
fcab303c DT	207	reg = <0x20303>;
fcab303c DT	208	enable-method = "psci";
dbb58d0f KW	209	next-level-cache = <&cluster3_l2>;
	210	};
	211
	212	cluster0_l2: l2-cache0 {
	213	compatible = "cache";
	214	};
	215
	216	cluster1_l2: l2-cache1 {
	217	compatible = "cache";
	218	};
	219
	220	cluster2_l2: l2-cache2 {
	221	compatible = "cache";
	222	};
	223
	224	cluster3_l2: l2-cache3 {
	225	compatible = "cache";
fcab303c DT	226	};
	227	};
	228
	229	gic: interrupt-controller@8d000000 {
	230	compatible = "arm,gic-v3";
	231	#interrupt-cells = <3>;
	232	#address-cells = <2>;
	233	#size-cells = <2>;
	234	ranges;
	235	interrupt-controller;
	236	#redistributor-regions = <1>;
	237	redistributor-stride = <0x0 0x30000>;
	238	reg = <0x0 0x8d000000 0 0x10000>, /* GICD */
	239	<0x0 0x8d100000 0 0x300000>, /* GICR */
	240	<0x0 0xfe000000 0 0x10000>, /* GICC */
	241	<0x0 0xfe010000 0 0x10000>, /* GICH */
	242	<0x0 0xfe020000 0 0x10000>; /* GICV */
	243	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	244
abf9c25d	245	its_peri: interrupt-controller@8c000000 {
fcab303c DT	246	compatible = "arm,gic-v3-its";
fcab303c DT	247	msi-controller;
70896650	248	#msi-cells = <1>;
fcab303c DT	249	reg = <0x0 0x8c000000 0x0 0x40000>;
fcab303c DT	250	};
abf9c25d KW	251
	252	its_m3: interrupt-controller@a3000000 {
	253	compatible = "arm,gic-v3-its";
	254	msi-controller;
70896650	255	#msi-cells = <1>;
abf9c25d KW	256	reg = <0x0 0xa3000000 0x0 0x40000>;
	257	};
	258
	259	its_pcie: interrupt-controller@b7000000 {
	260	compatible = "arm,gic-v3-its";
	261	msi-controller;
70896650	262	#msi-cells = <1>;
abf9c25d KW	263	reg = <0x0 0xb7000000 0x0 0x40000>;
	264	};
	265
	266	its_dsa: interrupt-controller@c6000000 {
	267	compatible = "arm,gic-v3-its";
	268	msi-controller;
70896650	269	#msi-cells = <1>;
abf9c25d KW	270	reg = <0x0 0xc6000000 0x0 0x40000>;
abf9c25d KW	271	};
fcab303c DT	272	};
	273
	274	timer {
	275	compatible = "arm,armv8-timer";
	276	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
	277	<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
	278	<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
	279	<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	280	};
	281
	282	pmu {
6897db62	283	compatible = "arm,cortex-a57-pmu";
fcab303c DT	284	interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	285	};
	286
	287	soc {
	288	compatible = "simple-bus";
	289	#address-cells = <2>;
	290	#size-cells = <2>;
	291	ranges;
	292
	293	refclk200mhz: refclk200mhz {
	294	compatible = "fixed-clock";
	295	#clock-cells = <0>;
	296	clock-frequency = <200000000>;
	297	};
	298
	299	uart0: uart@80300000 {
	300	compatible = "snps,dw-apb-uart";
	301	reg = <0x0 0x80300000 0x0 0x10000>;
	302	interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
	303	clocks = <&refclk200mhz>;
	304	clock-names = "apb_pclk";
	305	reg-shift = <2>;
	306	reg-io-width = <4>;
	307	status = "disabled";
	308	};
	309
	310	uart1: uart@80310000 {
	311	compatible = "snps,dw-apb-uart";
	312	reg = <0x0 0x80310000 0x0 0x10000>;
	313	interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
	314	clocks = <&refclk200mhz>;
	315	clock-names = "apb_pclk";
	316	reg-shift = <2>;
	317	reg-io-width = <4>;
	318	status = "disabled";
	319	};
8f41d122	320
162d23bf KW	321	lbc: localbus@80380000 {
	322	compatible = "hisilicon,hisi-localbus", "simple-bus";
	323	reg = <0x0 0x80380000 0x0 0x10000>;
	324	status = "disabled";
	325	};
	326
8f41d122 KW	327	peri_gpio0: gpio@802e0000 {
	328	#address-cells = <1>;
	329	#size-cells = <0>;
	330	compatible = "snps,dw-apb-gpio";
	331	reg = <0x0 0x802e0000 0x0 0x10000>;
	332	status = "disabled";
	333
	334	porta: gpio-controller@0 {
	335	compatible = "snps,dw-apb-gpio-port";
	336	gpio-controller;
	337	#gpio-cells = <2>;
	338	snps,nr-gpios = <32>;
	339	reg = <0>;
	340	interrupt-controller;
	341	#interrupt-cells = <2>;
	342	interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
	343	};
	344	};
	345
	346	peri_gpio1: gpio@802f0000 {
	347	#address-cells = <1>;
	348	#size-cells = <0>;
	349	compatible = "snps,dw-apb-gpio";
	350	reg = <0x0 0x802f0000 0x0 0x10000>;
	351	status = "disabled";
	352
	353	portb: gpio-controller@0 {
	354	compatible = "snps,dw-apb-gpio-port";
	355	gpio-controller;
	356	#gpio-cells = <2>;
	357	snps,nr-gpios = <32>;
	358	reg = <0>;
	359	interrupt-controller;
	360	#interrupt-cells = <2>;
	361	interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>;
	362	};
	363	};
fcab303c DT	364	};
fcab303c DT	365	};