[mirror_ubuntu-focal-kernel.git] / arch / arm64 / boot / dts / marvell / armada-37xx.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
 *
 * Copyright (C) 2016 Marvell
 *
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 *
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "Marvell Armada 37xx SoC";
	compatible = "marvell,armada3700";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/*
		 * The PSCI firmware region depicted below is the default one
		 * and should be updated by the bootloader.
		 */
		psci-area@4000000 {
			reg = <0 0x4000000 0 0x200000>;
			no-map;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0>;
			clocks = <&nb_periph_clk 16>;
			enable-method = "psci";
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
	};

	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		internal-regs@d0000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			/* 32M internal register @ 0xd000_0000 */
			ranges = <0x0 0x0 0xd0000000 0x2000000>;

			wdt: watchdog@8300 {
				compatible = "marvell,armada-3700-wdt";
				reg = <0x8300 0x40>;
				marvell,system-controller = <&cpu_misc>;
				clocks = <&xtalclk>;
			};

			cpu_misc: system-controller@d000 {
				compatible = "marvell,armada-3700-cpu-misc",
					     "syscon";
				reg = <0xd000 0x1000>;
			};

			spi0: spi@10600 {
				compatible = "marvell,armada-3700-spi";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x10600 0xA00>;
				clocks = <&nb_periph_clk 7>;
				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
				num-cs = <4>;
				status = "disabled";
			};

			i2c0: i2c@11000 {
				compatible = "marvell,armada-3700-i2c";
				reg = <0x11000 0x24>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&nb_periph_clk 10>;
				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
				mrvl,i2c-fast-mode;
				status = "disabled";
			};

			i2c1: i2c@11080 {
				compatible = "marvell,armada-3700-i2c";
				reg = <0x11080 0x24>;
				#address-cells = <1>;
				#size-cells = <0>;
				clocks = <&nb_periph_clk 9>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				mrvl,i2c-fast-mode;
				status = "disabled";
			};

			avs: avs@11500 {
				compatible = "marvell,armada-3700-avs",
					     "syscon";
				reg = <0x11500 0x40>;
			};

			uart0: serial@12000 {
				compatible = "marvell,armada-3700-uart";
				reg = <0x12000 0x200>;
				clocks = <&xtalclk>;
				interrupts =
				<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "uart-sum", "uart-tx", "uart-rx";
				status = "disabled";
			};

			uart1: serial@12200 {
				compatible = "marvell,armada-3700-uart-ext";
				reg = <0x12200 0x30>;
				clocks = <&xtalclk>;
				interrupts =
				<GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
				interrupt-names = "uart-tx", "uart-rx";
				status = "disabled";
			};

			nb_periph_clk: nb-periph-clk@13000 {
				compatible = "marvell,armada-3700-periph-clock-nb";
				reg = <0x13000 0x100>;
				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
				<&tbg 3>, <&xtalclk>;
				#clock-cells = <1>;
			};

			sb_periph_clk: sb-periph-clk@18000 {
				compatible = "marvell,armada-3700-periph-clock-sb";
				reg = <0x18000 0x100>;
				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
				<&tbg 3>, <&xtalclk>;
				#clock-cells = <1>;
			};

			tbg: tbg@13200 {
				compatible = "marvell,armada-3700-tbg-clock";
				reg = <0x13200 0x100>;
				clocks = <&xtalclk>;
				#clock-cells = <1>;
			};

			pinctrl_nb: pinctrl@13800 {
				compatible = "marvell,armada3710-nb-pinctrl",
					     "syscon", "simple-mfd";
				reg = <0x13800 0x100>, <0x13C00 0x20>;
				/* MPP1[19:0] */
				gpionb: gpio {
					#gpio-cells = <2>;
					gpio-ranges = <&pinctrl_nb 0 0 36>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts =
					<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
				};

				xtalclk: xtal-clk {
					compatible = "marvell,armada-3700-xtal-clock";
					clock-output-names = "xtal";
					#clock-cells = <0>;
				};

				spi_quad_pins: spi-quad-pins {
					groups = "spi_quad";
					function = "spi";
				};

				i2c1_pins: i2c1-pins {
					groups = "i2c1";
					function = "i2c";
				};

				i2c2_pins: i2c2-pins {
					groups = "i2c2";
					function = "i2c";
				};

				uart1_pins: uart1-pins {
					groups = "uart1";
					function = "uart";
				};

				uart2_pins: uart2-pins {
					groups = "uart2";
					function = "uart";
				};
			};

			nb_pm: syscon@14000 {
				compatible = "marvell,armada-3700-nb-pm",
					     "syscon";
				reg = <0x14000 0x60>;
			};

			pinctrl_sb: pinctrl@18800 {
				compatible = "marvell,armada3710-sb-pinctrl",
					     "syscon", "simple-mfd";
				reg = <0x18800 0x100>, <0x18C00 0x20>;
				/* MPP2[23:0] */
				gpiosb: gpio {
					#gpio-cells = <2>;
					gpio-ranges = <&pinctrl_sb 0 0 30>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts =
					<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
				};

				rgmii_pins: mii-pins {
					groups = "rgmii";
					function = "mii";
				};

			};

			eth0: ethernet@30000 {
				   compatible = "marvell,armada-3700-neta";
				   reg = <0x30000 0x4000>;
				   interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
				   clocks = <&sb_periph_clk 8>;
				   status = "disabled";
			};

			mdio: mdio@32004 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "marvell,orion-mdio";
				reg = <0x32004 0x4>;
			};

			eth1: ethernet@40000 {
				compatible = "marvell,armada-3700-neta";
				reg = <0x40000 0x4000>;
				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&sb_periph_clk 7>;
				status = "disabled";
			};

			usb3: usb@58000 {
				compatible = "marvell,armada3700-xhci",
				"generic-xhci";
				reg = <0x58000 0x4000>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&sb_periph_clk 12>;
				status = "disabled";
			};

			usb2: usb@5e000 {
				compatible = "marvell,armada-3700-ehci";
				reg = <0x5e000 0x2000>;
				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			xor@60900 {
				compatible = "marvell,armada-3700-xor";
				reg = <0x60900 0x100>,
				      <0x60b00 0x100>;

				xor10 {
					interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
				};
				xor11 {
					interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
				};
			};

			crypto: crypto@90000 {
				compatible = "inside-secure,safexcel-eip97ies";
				reg = <0x90000 0x20000>;
				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "mem", "ring0", "ring1",
						  "ring2", "ring3", "eip";
				clocks = <&nb_periph_clk 15>;
			};

			sdhci1: sdhci@d0000 {
				compatible = "marvell,armada-3700-sdhci",
					     "marvell,sdhci-xenon";
				reg = <0xd0000 0x300>,
				      <0x1e808 0x4>;
				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&nb_periph_clk 0>;
				clock-names = "core";
				status = "disabled";
			};

			sdhci0: sdhci@d8000 {
				compatible = "marvell,armada-3700-sdhci",
					     "marvell,sdhci-xenon";
				reg = <0xd8000 0x300>,
				      <0x17808 0x4>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&nb_periph_clk 0>;
				clock-names = "core";
				status = "disabled";
			};

			sata: sata@e0000 {
				compatible = "marvell,armada-3700-ahci";
				reg = <0xe0000 0x2000>;
				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};

			gic: interrupt-controller@1d00000 {
				compatible = "arm,gic-v3";
				#interrupt-cells = <3>;
				interrupt-controller;
				reg = <0x1d00000 0x10000>, /* GICD */
				      <0x1d40000 0x40000>, /* GICR */
				      <0x1d80000 0x2000>,  /* GICC */
				      <0x1d90000 0x2000>,  /* GICH */
				      <0x1da0000 0x20000>; /* GICV */
				interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		pcie0: pcie@d0070000 {
			compatible = "marvell,armada-3700-pcie";
			device_type = "pci";
			status = "disabled";
			reg = <0 0xd0070000 0 0x20000>;
			#address-cells = <3>;
			#size-cells = <2>;
			bus-range = <0x00 0xff>;
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
			#interrupt-cells = <1>;
			msi-parent = <&pcie0>;
			msi-controller;
			ranges = <0x82000000 0 0xe8000000   0 0xe8000000 0 0x1000000 /* Port 0 MEM */
				  0x81000000 0 0xe9000000   0 0xe9000000 0 0x10000>; /* Port 0 IO*/
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0 0 0 1 &pcie_intc 0>,
					<0 0 0 2 &pcie_intc 1>,
					<0 0 0 3 &pcie_intc 2>,
					<0 0 0 4 &pcie_intc 3>;
			pcie_intc: interrupt-controller {
				interrupt-controller;
				#interrupt-cells = <1>;
			};
		};
	};
};
Commit	Line	Data
292816a6	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
adbc3695 GC	2	/*
	3	* Device Tree Include file for Marvell Armada 37xx family of SoCs.
	4	*
	5	* Copyright (C) 2016 Marvell
	6	*
	7	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	8	*
adbc3695 GC	9	*/
	10
	11	#include <dt-bindings/interrupt-controller/arm-gic.h>
	12
	13	/ {
	14	model = "Marvell Armada 37xx SoC";
	15	compatible = "marvell,armada3700";
	16	interrupt-parent = <&gic>;
	17	#address-cells = <2>;
	18	#size-cells = <2>;
	19
	20	aliases {
	21	serial0 = &uart0;
7c48dc20	22	serial1 = &uart1;
adbc3695 GC	23	};
adbc3695 GC	24
4436a371 VG	25	reserved-memory {
	26	#address-cells = <2>;
	27	#size-cells = <2>;
	28	ranges;
	29
	30	/*
	31	* The PSCI firmware region depicted below is the default one
	32	* and should be updated by the bootloader.
	33	*/
	34	psci-area@4000000 {
	35	reg = <0 0x4000000 0 0x200000>;
	36	no-map;
	37	};
	38	};
	39
adbc3695 GC	40	cpus {
	41	#address-cells = <1>;
	42	#size-cells = <0>;
92e5d4e9	43	cpu0: cpu@0 {
adbc3695 GC	44	device_type = "cpu";
	45	compatible = "arm,cortex-a53", "arm,armv8";
	46	reg = <0>;
e8d66e79	47	clocks = <&nb_periph_clk 16>;
adbc3695 GC	48	enable-method = "psci";
	49	};
	50	};
	51
	52	psci {
	53	compatible = "arm,psci-0.2";
	54	method = "smc";
	55	};
	56
	57	timer {
	58	compatible = "arm,armv8-timer";
88cda007 MZ	59	interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
	60	<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
	61	<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
	62	<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
adbc3695 GC	63	};
adbc3695 GC	64
395e66ba MZ	65	pmu {
	66	compatible = "arm,armv8-pmuv3";
	67	interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	68	};
	69
adbc3695 GC	70	soc {
	71	compatible = "simple-bus";
	72	#address-cells = <2>;
	73	#size-cells = <2>;
	74	ranges;
	75
ee5d5619	76	internal-regs@d0000000 {
adbc3695 GC	77	#address-cells = <1>;
	78	#size-cells = <1>;
	79	compatible = "simple-bus";
	80	/* 32M internal register @ 0xd000_0000 */
	81	ranges = <0x0 0x0 0xd0000000 0x2000000>;
	82
620cfb31 MB	83	wdt: watchdog@8300 {
	84	compatible = "marvell,armada-3700-wdt";
	85	reg = <0x8300 0x40>;
	86	marvell,system-controller = <&cpu_misc>;
	87	clocks = <&xtalclk>;
	88	};
	89
	90	cpu_misc: system-controller@d000 {
	91	compatible = "marvell,armada-3700-cpu-misc",
	92	"syscon";
	93	reg = <0xd000 0x1000>;
	94	};
	95
e09dfa8f RP	96	spi0: spi@10600 {
	97	compatible = "marvell,armada-3700-spi";
	98	#address-cells = <1>;
	99	#size-cells = <0>;
	100	reg = <0x10600 0xA00>;
	101	clocks = <&nb_periph_clk 7>;
	102	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
	103	num-cs = <4>;
	104	status = "disabled";
	105	};
	106
c7d7ea67 RP	107	i2c0: i2c@11000 {
	108	compatible = "marvell,armada-3700-i2c";
	109	reg = <0x11000 0x24>;
0ddd48de GC	110	#address-cells = <1>;
0ddd48de GC	111	#size-cells = <0>;
c7d7ea67 RP	112	clocks = <&nb_periph_clk 10>;
	113	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
	114	mrvl,i2c-fast-mode;
	115	status = "disabled";
	116	};
	117
	118	i2c1: i2c@11080 {
	119	compatible = "marvell,armada-3700-i2c";
	120	reg = <0x11080 0x24>;
0ddd48de GC	121	#address-cells = <1>;
0ddd48de GC	122	#size-cells = <0>;
c7d7ea67 RP	123	clocks = <&nb_periph_clk 9>;
	124	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
	125	mrvl,i2c-fast-mode;
	126	status = "disabled";
	127	};
	128
d970737f GC	129	avs: avs@11500 {
	130	compatible = "marvell,armada-3700-avs",
	131	"syscon";
	132	reg = <0x11500 0x40>;
	133	};
	134
adbc3695 GC	135	uart0: serial@12000 {
adbc3695 GC	136	compatible = "marvell,armada-3700-uart";
c737abc1	137	reg = <0x12000 0x200>;
2ff0d0b5	138	clocks = <&xtalclk>;
7c48dc20 MR	139	interrupts =
	140	<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
	141	<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
	142	<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
	143	interrupt-names = "uart-sum", "uart-tx", "uart-rx";
	144	status = "disabled";
	145	};
	146
	147	uart1: serial@12200 {
	148	compatible = "marvell,armada-3700-uart-ext";
	149	reg = <0x12200 0x30>;
	150	clocks = <&xtalclk>;
	151	interrupts =
	152	<GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
	153	<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
	154	interrupt-names = "uart-tx", "uart-rx";
adbc3695 GC	155	status = "disabled";
	156	};
	157
29f0c9ed	158	nb_periph_clk: nb-periph-clk@13000 {
5f4beef6 GC	159	compatible = "marvell,armada-3700-periph-clock-nb";
	160	reg = <0x13000 0x100>;
	161	clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
	162	<&tbg 3>, <&xtalclk>;
	163	#clock-cells = <1>;
	164	};
	165
29f0c9ed	166	sb_periph_clk: sb-periph-clk@18000 {
5f4beef6 GC	167	compatible = "marvell,armada-3700-periph-clock-sb";
	168	reg = <0x18000 0x100>;
	169	clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
	170	<&tbg 3>, <&xtalclk>;
	171	#clock-cells = <1>;
	172	};
	173
e3e1a55e GC	174	tbg: tbg@13200 {
	175	compatible = "marvell,armada-3700-tbg-clock";
	176	reg = <0x13200 0x100>;
	177	clocks = <&xtalclk>;
	178	#clock-cells = <1>;
	179	};
	180
afda007f GC	181	pinctrl_nb: pinctrl@13800 {
afda007f GC	182	compatible = "marvell,armada3710-nb-pinctrl",
55ad5b1a	183	"syscon", "simple-mfd";
afda007f	184	reg = <0x13800 0x100>, <0x13C00 0x20>;
bd473ecd	185	/* MPP1[19:0] */
afda007f GC	186	gpionb: gpio {
	187	#gpio-cells = <2>;
	188	gpio-ranges = <&pinctrl_nb 0 0 36>;
	189	gpio-controller;
bd473ecd UKK	190	interrupt-controller;
bd473ecd UKK	191	#interrupt-cells = <2>;
afda007f GC	192	interrupts =
	193	<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
	194	<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
	195	<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	196	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	197	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	198	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	199	<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
	200	<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	201	<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
	202	<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
	203	<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
	204	<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
afda007f	205	};
ddeba40b GC	206
	207	xtalclk: xtal-clk {
	208	compatible = "marvell,armada-3700-xtal-clock";
	209	clock-output-names = "xtal";
	210	#clock-cells = <0>;
	211	};
6a680783 GC	212
	213	spi_quad_pins: spi-quad-pins {
	214	groups = "spi_quad";
	215	function = "spi";
	216	};
	217
	218	i2c1_pins: i2c1-pins {
	219	groups = "i2c1";
	220	function = "i2c";
	221	};
	222
	223	i2c2_pins: i2c2-pins {
	224	groups = "i2c2";
	225	function = "i2c";
	226	};
	227
	228	uart1_pins: uart1-pins {
	229	groups = "uart1";
	230	function = "uart";
	231	};
	232
	233	uart2_pins: uart2-pins {
	234	groups = "uart2";
	235	function = "uart";
	236	};
ddeba40b GC	237	};
ddeba40b GC	238
e8d66e79 GC	239	nb_pm: syscon@14000 {
	240	compatible = "marvell,armada-3700-nb-pm",
	241	"syscon";
	242	reg = <0x14000 0x60>;
	243	};
	244
afda007f GC	245	pinctrl_sb: pinctrl@18800 {
afda007f GC	246	compatible = "marvell,armada3710-sb-pinctrl",
55ad5b1a	247	"syscon", "simple-mfd";
afda007f	248	reg = <0x18800 0x100>, <0x18C00 0x20>;
bd473ecd	249	/* MPP2[23:0] */
afda007f GC	250	gpiosb: gpio {
afda007f GC	251	#gpio-cells = <2>;
d7a65c49	252	gpio-ranges = <&pinctrl_sb 0 0 30>;
afda007f	253	gpio-controller;
bd473ecd UKK	254	interrupt-controller;
bd473ecd UKK	255	#interrupt-cells = <2>;
afda007f GC	256	interrupts =
	257	<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
	258	<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
	259	<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
	260	<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
	261	<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
	262	};
6a680783 GC	263
	264	rgmii_pins: mii-pins {
	265	groups = "rgmii";
	266	function = "mii";
	267	};
	268
ddeba40b GC	269	};
ddeba40b GC	270
ea7ae885 GC	271	eth0: ethernet@30000 {
	272	compatible = "marvell,armada-3700-neta";
	273	reg = <0x30000 0x4000>;
	274	interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	275	clocks = <&sb_periph_clk 8>;
	276	status = "disabled";
	277	};
	278
	279	mdio: mdio@32004 {
	280	#address-cells = <1>;
	281	#size-cells = <0>;
	282	compatible = "marvell,orion-mdio";
	283	reg = <0x32004 0x4>;
	284	};
	285
	286	eth1: ethernet@40000 {
	287	compatible = "marvell,armada-3700-neta";
	288	reg = <0x40000 0x4000>;
	289	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
	290	clocks = <&sb_periph_clk 7>;
	291	status = "disabled";
	292	};
	293
cc2684c4	294	usb3: usb@58000 {
150fa112 GC	295	compatible = "marvell,armada3700-xhci",
150fa112 GC	296	"generic-xhci";
adbc3695	297	reg = <0x58000 0x4000>;
86fcb2bc	298	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
e4afb480	299	clocks = <&sb_periph_clk 12>;
adbc3695 GC	300	status = "disabled";
	301	};
	302
4fc056ed GC	303	usb2: usb@5e000 {
	304	compatible = "marvell,armada-3700-ehci";
	305	reg = <0x5e000 0x2000>;
	306	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	307	status = "disabled";
	308	};
	309
19b67d5c GC	310	xor@60900 {
19b67d5c GC	311	compatible = "marvell,armada-3700-xor";
e9bfac54 GC	312	reg = <0x60900 0x100>,
e9bfac54 GC	313	<0x60b00 0x100>;
19b67d5c GC	314
	315	xor10 {
	316	interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
	317	};
	318	xor11 {
	319	interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
	320	};
	321	};
	322
e2707a28	323	crypto: crypto@90000 {
c462f6c7	324	compatible = "inside-secure,safexcel-eip97ies";
e2707a28 AT	325	reg = <0x90000 0x20000>;
	326	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
	327	<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
	328	<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
	329	<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
	330	<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
	331	<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	332	interrupt-names = "mem", "ring0", "ring1",
	333	"ring2", "ring3", "eip";
	334	clocks = <&nb_periph_clk 15>;
	335	};
	336
1208d2f0 KP	337	sdhci1: sdhci@d0000 {
	338	compatible = "marvell,armada-3700-sdhci",
	339	"marvell,sdhci-xenon";
	340	reg = <0xd0000 0x300>,
	341	<0x1e808 0x4>;
	342	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
	343	clocks = <&nb_periph_clk 0>;
	344	clock-names = "core";
	345	status = "disabled";
	346	};
	347
53e74778 GC	348	sdhci0: sdhci@d8000 {
53e74778 GC	349	compatible = "marvell,armada-3700-sdhci",
55ad5b1a	350	"marvell,sdhci-xenon";
e9bfac54 GC	351	reg = <0xd8000 0x300>,
e9bfac54 GC	352	<0x17808 0x4>;
53e74778 GC	353	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	354	clocks = <&nb_periph_clk 0>;
	355	clock-names = "core";
	356	status = "disabled";
	357	};
	358
7b01cff5	359	sata: sata@e0000 {
adbc3695 GC	360	compatible = "marvell,armada-3700-ahci";
	361	reg = <0xe0000 0x2000>;
	362	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
	363	status = "disabled";
	364	};
	365
	366	gic: interrupt-controller@1d00000 {
	367	compatible = "arm,gic-v3";
	368	#interrupt-cells = <3>;
	369	interrupt-controller;
	370	reg = <0x1d00000 0x10000>, /* GICD */
5f926e88 MZ	371	<0x1d40000 0x40000>, /* GICR */
	372	<0x1d80000 0x2000>, /* GICC */
	373	<0x1d90000 0x2000>, /* GICH */
	374	<0x1da0000 0x20000>; /* GICV */
95696d29	375	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
adbc3695 GC	376	};
adbc3695 GC	377	};
76f6386b TP	378
	379	pcie0: pcie@d0070000 {
	380	compatible = "marvell,armada-3700-pcie";
	381	device_type = "pci";
	382	status = "disabled";
	383	reg = <0 0xd0070000 0 0x20000>;
	384	#address-cells = <3>;
	385	#size-cells = <2>;
	386	bus-range = <0x00 0xff>;
	387	interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	388	#interrupt-cells = <1>;
	389	msi-parent = <&pcie0>;
	390	msi-controller;
	391	ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
	392	0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
	393	interrupt-map-mask = <0 0 0 7>;
	394	interrupt-map = <0 0 0 1 &pcie_intc 0>,
	395	<0 0 0 2 &pcie_intc 1>,
	396	<0 0 0 3 &pcie_intc 2>,
	397	<0 0 0 4 &pcie_intc 3>;
	398	pcie_intc: interrupt-controller {
	399	interrupt-controller;
	400	#interrupt-cells = <1>;
	401	};
	402	};
adbc3695 GC	403	};
adbc3695 GC	404	};