[mirror_ubuntu-eoan-kernel.git] / arch / arm64 / boot / dts / marvell / armada-8040-mcbin.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * Device Tree file for MACCHIATOBin Armada 8040 community board platform
 */

#include "armada-8040.dtsi"

#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Marvell 8040 MACCHIATOBin";
	compatible = "marvell,armada8040-mcbin", "marvell,armada8040",
			"marvell,armada-ap806-quad", "marvell,armada-ap806";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>;
	};

	aliases {
		ethernet0 = &cp0_eth0;
		ethernet1 = &cp1_eth0;
		ethernet2 = &cp1_eth1;
		ethernet3 = &cp1_eth2;
	};

	/* Regulator labels correspond with schematics */
	v_3_3: regulator-3-3v {
		compatible = "regulator-fixed";
		regulator-name = "v_3_3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		status = "okay";
	};

	v_vddo_h: regulator-1-8v {
		compatible = "regulator-fixed";
		regulator-name = "v_vddo_h";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-always-on;
		status = "okay";
	};

	v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
		compatible = "regulator-fixed";
		enable-active-high;
		gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&cp0_xhci_vbus_pins>;
		regulator-name = "v_5v0_usb3_hst_vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		status = "okay";
	};

	usb3h0_phy: usb3_phy0 {
		compatible = "usb-nop-xceiv";
		vcc-supply = <&v_5v0_usb3_hst_vbus>;
	};

	sfp_eth0: sfp-eth0 {
		/* CON15,16 - CPM lane 4 */
		compatible = "sff,sfp";
		i2c-bus = <&sfpp0_i2c>;
		los-gpio = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>;
		mod-def0-gpio = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>;
		tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
		tx-fault-gpio  = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&cp1_sfpp0_pins>;
	};

	sfp_eth1: sfp-eth1 {
		/* CON17,18 - CPS lane 4 */
		compatible = "sff,sfp";
		i2c-bus = <&sfpp1_i2c>;
		los-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
		mod-def0-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
		tx-disable-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>;
		tx-fault-gpio = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>;
	};

	sfp_eth3: sfp-eth3 {
		/* CON13,14 - CPS lane 5 */
		compatible = "sff,sfp";
		i2c-bus = <&sfp_1g_i2c>;
		los-gpio = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>;
		mod-def0-gpio = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>;
		tx-disable-gpio = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>;
		tx-fault-gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>;
	};
};

&uart0 {
	status = "okay";
	pinctrl-0 = <&uart0_pins>;
	pinctrl-names = "default";
};

&ap_sdhci0 {
	bus-width = <8>;
	/*
	 * Not stable in HS modes - phy needs "more calibration", so add
	 * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
	 */
	marvell,xenon-phy-slow-mode;
	no-1-8-v;
	no-sd;
	no-sdio;
	non-removable;
	status = "okay";
	vqmmc-supply = <&v_vddo_h>;
};

&cp0_i2c0 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_i2c0_pins>;
	status = "okay";
};

&cp0_i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_i2c1_pins>;
	status = "okay";

	i2c-switch@70 {
		compatible = "nxp,pca9548";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x70>;

		sfpp0_i2c: i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
		};
		sfpp1_i2c: i2c@1 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <1>;
		};
		sfp_1g_i2c: i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
		};
	};
};

/* J25 UART header */
&cp0_uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_uart1_pins>;
	status = "okay";
};

&cp0_mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_ge_mdio_pins>;
	status = "okay";

	ge_phy: ethernet-phy@0 {
		reg = <0>;
	};
};

&cp0_pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_pcie_pins>;
	num-lanes = <4>;
	num-viewport = <8>;
	reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&cp0_pinctrl {
	cp0_ge_mdio_pins: ge-mdio-pins {
		marvell,pins = "mpp32", "mpp34";
		marvell,function = "ge";
	};
	cp0_i2c1_pins: i2c1-pins {
		marvell,pins = "mpp35", "mpp36";
		marvell,function = "i2c1";
	};
	cp0_i2c0_pins: i2c0-pins {
		marvell,pins = "mpp37", "mpp38";
		marvell,function = "i2c0";
	};
	cp0_uart1_pins: uart1-pins {
		marvell,pins = "mpp40", "mpp41";
		marvell,function = "uart1";
	};
	cp0_xhci_vbus_pins: xhci0-vbus-pins {
		marvell,pins = "mpp47";
		marvell,function = "gpio";
	};
	cp0_sfp_1g_pins: sfp-1g-pins {
		marvell,pins = "mpp51", "mpp53", "mpp54";
		marvell,function = "gpio";
	};
	cp0_pcie_pins: pcie-pins {
		marvell,pins = "mpp52";
		marvell,function = "gpio";
	};
	cp0_sdhci_pins: sdhci-pins {
		marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
			       "mpp60", "mpp61";
		marvell,function = "sdio";
	};
	cp0_sfpp1_pins: sfpp1-pins {
		marvell,pins = "mpp62";
		marvell,function = "gpio";
	};
};

&cp0_ethernet {
	status = "okay";
};

&cp0_eth0 {
	/* Generic PHY, providing serdes lanes */
	phys = <&cp0_comphy4 0>;
};

&cp0_sata0 {
	/* CPM Lane 0 - U29 */
	status = "okay";
};

&cp0_sdhci0 {
	/* U6 */
	broken-cd;
	bus-width = <4>;
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_sdhci_pins>;
	status = "okay";
	vqmmc-supply = <&v_3_3>;
};

&cp0_usb3_0 {
	/* J38? - USB2.0 only */
	status = "okay";
};

&cp0_usb3_1 {
	/* J38? - USB2.0 only */
	status = "okay";
};

&cp1_ethernet {
	status = "okay";
};

&cp1_eth0 {
	/* Generic PHY, providing serdes lanes */
	phys = <&cp1_comphy4 0>;
};

&cp1_eth1 {
	/* CPS Lane 0 - J5 (Gigabit RJ45) */
	status = "okay";
	/* Network PHY */
	phy = <&ge_phy>;
	phy-mode = "sgmii";
	/* Generic PHY, providing serdes lanes */
	phys = <&cp1_comphy0 1>;
};

&cp1_eth2 {
	/* CPS Lane 5 */
	status = "okay";
	/* Network PHY */
	phy-mode = "2500base-x";
	managed = "in-band-status";
	/* Generic PHY, providing serdes lanes */
	phys = <&cp1_comphy5 2>;
	sfp = <&sfp_eth3>;
};

&cp1_pinctrl {
	cp1_sfpp1_pins: sfpp1-pins {
		marvell,pins = "mpp8", "mpp10", "mpp11";
		marvell,function = "gpio";
	};
	cp1_spi1_pins: spi1-pins {
		marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
		marvell,function = "spi1";
	};
	cp1_uart0_pins: uart0-pins {
		marvell,pins = "mpp6", "mpp7";
		marvell,function = "uart0";
	};
	cp1_sfp_1g_pins: sfp-1g-pins {
		marvell,pins = "mpp24";
		marvell,function = "gpio";
	};
	cp1_sfpp0_pins: sfpp0-pins {
		marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29";
		marvell,function = "gpio";
	};
};

/* J27 UART header */
&cp1_uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp1_uart0_pins>;
	status = "okay";
};

&cp1_sata0 {
	/* CPS Lane 1 - U32 */
	/* CPS Lane 3 - U31 */
	status = "okay";
};

&cp1_spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp1_spi1_pins>;
	status = "okay";

	spi-flash@0 {
		compatible = "st,w25q32";
		spi-max-frequency = <50000000>;
		reg = <0>;
	};
};

&cp1_usb3_0 {
	/* CPS Lane 2 - CON7 */
	usb-phy = <&usb3h0_phy>;
	status = "okay";
};
Commit	Line	Data
b1f0bbe2 RK	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright (C) 2016 Marvell Technology Group Ltd.
	4	*
	5	* Device Tree file for MACCHIATOBin Armada 8040 community board platform
	6	*/
	7
	8	#include "armada-8040.dtsi"
	9
	10	#include <dt-bindings/gpio/gpio.h>
	11
	12	/ {
	13	model = "Marvell 8040 MACCHIATOBin";
	14	compatible = "marvell,armada8040-mcbin", "marvell,armada8040",
	15	"marvell,armada-ap806-quad", "marvell,armada-ap806";
	16
	17	chosen {
	18	stdout-path = "serial0:115200n8";
	19	};
	20
	21	memory@0 {
	22	device_type = "memory";
	23	reg = <0x0 0x0 0x0 0x80000000>;
	24	};
	25
	26	aliases {
	27	ethernet0 = &cp0_eth0;
	28	ethernet1 = &cp1_eth0;
	29	ethernet2 = &cp1_eth1;
	30	ethernet3 = &cp1_eth2;
	31	};
	32
	33	/* Regulator labels correspond with schematics */
	34	v_3_3: regulator-3-3v {
	35	compatible = "regulator-fixed";
	36	regulator-name = "v_3_3";
	37	regulator-min-microvolt = <3300000>;
	38	regulator-max-microvolt = <3300000>;
	39	regulator-always-on;
	40	status = "okay";
	41	};
	42
	43	v_vddo_h: regulator-1-8v {
	44	compatible = "regulator-fixed";
	45	regulator-name = "v_vddo_h";
	46	regulator-min-microvolt = <1800000>;
	47	regulator-max-microvolt = <1800000>;
	48	regulator-always-on;
	49	status = "okay";
	50	};
	51
	52	v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
	53	compatible = "regulator-fixed";
	54	enable-active-high;
	55	gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
	56	pinctrl-names = "default";
	57	pinctrl-0 = <&cp0_xhci_vbus_pins>;
	58	regulator-name = "v_5v0_usb3_hst_vbus";
	59	regulator-min-microvolt = <5000000>;
	60	regulator-max-microvolt = <5000000>;
	61	status = "okay";
	62	};
	63
	64	usb3h0_phy: usb3_phy0 {
65	compatible = "usb-nop-xceiv";
66	vcc-supply = <&v_5v0_usb3_hst_vbus>;
67	};
68
69	sfp_eth0: sfp-eth0 {
70	/* CON15,16 - CPM lane 4 */
71	compatible = "sff,sfp";
72	i2c-bus = <&sfpp0_i2c>;
73	los-gpio = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>;
74	mod-def0-gpio = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>;
75	tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
76	tx-fault-gpio = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>;
77	pinctrl-names = "default";
78	pinctrl-0 = <&cp1_sfpp0_pins>;
79	};
80
81	sfp_eth1: sfp-eth1 {
82	/* CON17,18 - CPS lane 4 */
83	compatible = "sff,sfp";
84	i2c-bus = <&sfpp1_i2c>;
85	los-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
86	mod-def0-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
87	tx-disable-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>;
88	tx-fault-gpio = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>;
89	pinctrl-names = "default";
90	pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>;
91	};
92
93	sfp_eth3: sfp-eth3 {
94	/* CON13,14 - CPS lane 5 */
95	compatible = "sff,sfp";
96	i2c-bus = <&sfp_1g_i2c>;
97	los-gpio = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>;
98	mod-def0-gpio = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>;
99	tx-disable-gpio = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>;
100	tx-fault-gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
101	pinctrl-names = "default";
102	pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>;
103	};
104	};
105
106	&uart0 {
107	status = "okay";
108	pinctrl-0 = <&uart0_pins>;
109	pinctrl-names = "default";
110	};
111
112	&ap_sdhci0 {
113	bus-width = <8>;
114	/*
115	* Not stable in HS modes - phy needs "more calibration", so add
116	* the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
117	*/
118	marvell,xenon-phy-slow-mode;
119	no-1-8-v;
120	no-sd;
121	no-sdio;
122	non-removable;
123	status = "okay";
124	vqmmc-supply = <&v_vddo_h>;
125	};
126
127	&cp0_i2c0 {
128	clock-frequency = <100000>;
129	pinctrl-names = "default";
130	pinctrl-0 = <&cp0_i2c0_pins>;
131	status = "okay";
132	};
133
134	&cp0_i2c1 {
135	clock-frequency = <100000>;
136	pinctrl-names = "default";
137	pinctrl-0 = <&cp0_i2c1_pins>;
138	status = "okay";
139
140	i2c-switch@70 {
141	compatible = "nxp,pca9548";
142	#address-cells = <1>;
143	#size-cells = <0>;
144	reg = <0x70>;
145
146	sfpp0_i2c: i2c@0 {
147	#address-cells = <1>;
148	#size-cells = <0>;
149	reg = <0>;
150	};
151	sfpp1_i2c: i2c@1 {
152	#address-cells = <1>;
153	#size-cells = <0>;
154	reg = <1>;
155	};
156	sfp_1g_i2c: i2c@2 {
157	#address-cells = <1>;
158	#size-cells = <0>;
159	reg = <2>;
160	};
161	};
162	};
163
164	/* J25 UART header */
165	&cp0_uart1 {
166	pinctrl-names = "default";
167	pinctrl-0 = <&cp0_uart1_pins>;
168	status = "okay";
169	};
170
171	&cp0_mdio {
172	pinctrl-names = "default";
173	pinctrl-0 = <&cp0_ge_mdio_pins>;
174	status = "okay";
175
176	ge_phy: ethernet-phy@0 {
177	reg = <0>;
178	};
179	};
180
181	&cp0_pcie0 {
182	pinctrl-names = "default";
183	pinctrl-0 = <&cp0_pcie_pins>;
184	num-lanes = <4>;
185	num-viewport = <8>;
59c4dccb	186	reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
b1f0bbe2 RK	187	status = "okay";
	188	};
	189
	190	&cp0_pinctrl {
	191	cp0_ge_mdio_pins: ge-mdio-pins {
	192	marvell,pins = "mpp32", "mpp34";
	193	marvell,function = "ge";
	194	};
	195	cp0_i2c1_pins: i2c1-pins {
	196	marvell,pins = "mpp35", "mpp36";
	197	marvell,function = "i2c1";
	198	};
	199	cp0_i2c0_pins: i2c0-pins {
	200	marvell,pins = "mpp37", "mpp38";
	201	marvell,function = "i2c0";
	202	};
	203	cp0_uart1_pins: uart1-pins {
	204	marvell,pins = "mpp40", "mpp41";
	205	marvell,function = "uart1";
	206	};
	207	cp0_xhci_vbus_pins: xhci0-vbus-pins {
	208	marvell,pins = "mpp47";
	209	marvell,function = "gpio";
	210	};
	211	cp0_sfp_1g_pins: sfp-1g-pins {
	212	marvell,pins = "mpp51", "mpp53", "mpp54";
	213	marvell,function = "gpio";
	214	};
	215	cp0_pcie_pins: pcie-pins {
	216	marvell,pins = "mpp52";
	217	marvell,function = "gpio";
	218	};
	219	cp0_sdhci_pins: sdhci-pins {
	220	marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
	221	"mpp60", "mpp61";
	222	marvell,function = "sdio";
	223	};
	224	cp0_sfpp1_pins: sfpp1-pins {
	225	marvell,pins = "mpp62";
	226	marvell,function = "gpio";
	227	};
	228	};
	229
	230	&cp0_ethernet {
	231	status = "okay";
	232	};
	233
	234	&cp0_eth0 {
	235	/* Generic PHY, providing serdes lanes */
	236	phys = <&cp0_comphy4 0>;
	237	};
	238
	239	&cp0_sata0 {
	240	/* CPM Lane 0 - U29 */
	241	status = "okay";
	242	};
	243
	244	&cp0_sdhci0 {
	245	/* U6 */
	246	broken-cd;
	247	bus-width = <4>;
	248	pinctrl-names = "default";
	249	pinctrl-0 = <&cp0_sdhci_pins>;
	250	status = "okay";
251	vqmmc-supply = <&v_3_3>;
252	};
253
254	&cp0_usb3_0 {
255	/* J38? - USB2.0 only */
256	status = "okay";
257	};
258
259	&cp0_usb3_1 {
260	/* J38? - USB2.0 only */
261	status = "okay";
262	};
263
264	&cp1_ethernet {
265	status = "okay";
266	};
267
268	&cp1_eth0 {
269	/* Generic PHY, providing serdes lanes */
270	phys = <&cp1_comphy4 0>;
271	};
272
273	&cp1_eth1 {
274	/* CPS Lane 0 - J5 (Gigabit RJ45) */
275	status = "okay";
276	/* Network PHY */
277	phy = <&ge_phy>;
278	phy-mode = "sgmii";
279	/* Generic PHY, providing serdes lanes */
280	phys = <&cp1_comphy0 1>;
281	};
282
283	&cp1_eth2 {
284	/* CPS Lane 5 */
285	status = "okay";
286	/* Network PHY */
287	phy-mode = "2500base-x";
288	managed = "in-band-status";
289	/* Generic PHY, providing serdes lanes */
290	phys = <&cp1_comphy5 2>;
291	sfp = <&sfp_eth3>;
292	};
293
294	&cp1_pinctrl {
295	cp1_sfpp1_pins: sfpp1-pins {
296	marvell,pins = "mpp8", "mpp10", "mpp11";
297	marvell,function = "gpio";
298	};
299	cp1_spi1_pins: spi1-pins {
300	marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
301	marvell,function = "spi1";
302	};
303	cp1_uart0_pins: uart0-pins {
304	marvell,pins = "mpp6", "mpp7";
305	marvell,function = "uart0";
306	};
307	cp1_sfp_1g_pins: sfp-1g-pins {
308	marvell,pins = "mpp24";
309	marvell,function = "gpio";
310	};
311	cp1_sfpp0_pins: sfpp0-pins {
312	marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29";
313	marvell,function = "gpio";
314	};
315	};
316
317	/* J27 UART header */
318	&cp1_uart0 {
319	pinctrl-names = "default";
320	pinctrl-0 = <&cp1_uart0_pins>;
321	status = "okay";
322	};
323
324	&cp1_sata0 {
325	/* CPS Lane 1 - U32 */
326	/* CPS Lane 3 - U31 */
327	status = "okay";
328	};
329
330	&cp1_spi1 {
331	pinctrl-names = "default";
332	pinctrl-0 = <&cp1_spi1_pins>;
333	status = "okay";
334
335	spi-flash@0 {
336	compatible = "st,w25q32";
337	spi-max-frequency = <50000000>;
338	reg = <0>;
339	};
340	};
341
342	&cp1_usb3_0 {
343	/* CPS Lane 2 - CON7 */
344	usb-phy = <&usb3h0_phy>;
345	status = "okay";
346	};