[mirror_ubuntu-artful-kernel.git] / arch / arm64 / boot / dts / marvell / armada-cp110-slave.dtsi

/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPLv2 or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/*
 * Device Tree file for Marvell Armada CP110 Slave.
 */

/ {
	cp110-slave {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		ranges;

		config-space@f4000000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "simple-bus";
			interrupt-parent = <&gic>;
			ranges = <0x0 0x0 0xf4000000 0x2000000>;

			cps_rtc: rtc@284000 {
				compatible = "marvell,armada-8k-rtc";
				reg = <0x284000 0x20>, <0x284080 0x24>;
				reg-names = "rtc", "rtc-soc";
				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			};

			cps_ethernet: ethernet@0 {
				compatible = "marvell,armada-7k-pp22";
				reg = <0x0 0x100000>, <0x129000 0xb000>;
				clocks = <&cps_syscon0 1 3>, <&cps_syscon0 1 9>, <&cps_syscon0 1 5>;
				clock-names = "pp_clk", "gop_clk", "mg_clk";
				status = "disabled";
				dma-coherent;

				cps_eth0: eth0 {
					interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
					port-id = <0>;
					gop-port-id = <0>;
					status = "disabled";
				};

				cps_eth1: eth1 {
					interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
					port-id = <1>;
					gop-port-id = <2>;
					status = "disabled";
				};

				cps_eth2: eth2 {
					interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
					port-id = <2>;
					gop-port-id = <3>;
					status = "disabled";
				};
			};

			cps_mdio: mdio@12a200 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "marvell,orion-mdio";
				reg = <0x12a200 0x10>;
				clocks = <&cps_syscon0 1 9>, <&cps_syscon0 1 5>;
			};

			cps_syscon0: system-controller@440000 {
				compatible = "marvell,cp110-system-controller0",
					     "syscon";
				reg = <0x440000 0x1000>;
				#clock-cells = <2>;
				core-clock-output-names =
					"cps-apll", "cps-ppv2-core", "cps-eip",
					"cps-core", "cps-nand-core";
				gate-clock-output-names =
					"cps-audio", "cps-communit", "cps-nand",
					"cps-ppv2", "cps-sdio", "cps-mg-domain",
					"cps-mg-core", "cps-xor1", "cps-xor0",
					"cps-gop-dp", "none", "cps-pcie_x10",
					"cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
					"cps-sata", "cps-sata-usb", "cps-main",
					"cps-sd-mmc-gop", "none", "none",
					"cps-slow-io", "cps-usb3h0", "cps-usb3h1",
					"cps-usb3dev", "cps-eip150", "cps-eip197";
			};

			cps_sata0: sata@540000 {
				compatible = "marvell,armada-8k-ahci",
					     "generic-ahci";
				reg = <0x540000 0x30000>;
				interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&cps_syscon0 1 15>;
				status = "disabled";
			};

			cps_usb3_0: usb3@500000 {
				compatible = "marvell,armada-8k-xhci",
					     "generic-xhci";
				reg = <0x500000 0x4000>;
				dma-coherent;
				interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&cps_syscon0 1 22>;
				status = "disabled";
			};

			cps_usb3_1: usb3@510000 {
				compatible = "marvell,armada-8k-xhci",
					     "generic-xhci";
				reg = <0x510000 0x4000>;
				dma-coherent;
				interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&cps_syscon0 1 23>;
				status = "disabled";
			};

			cps_xor0: xor@6a0000 {
				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
				reg = <0x6a0000 0x1000>,
				      <0x6b0000 0x1000>;
				dma-coherent;
				msi-parent = <&gic_v2m0>;
				clocks = <&cps_syscon0 1 8>;
			};

			cps_xor1: xor@6c0000 {
				compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
				reg = <0x6c0000 0x1000>,
				      <0x6d0000 0x1000>;
				dma-coherent;
				msi-parent = <&gic_v2m0>;
				clocks = <&cps_syscon0 1 7>;
			};

			cps_spi0: spi@700600 {
				compatible = "marvell,armada-380-spi";
				reg = <0x700600 0x50>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				cell-index = <3>;
				clocks = <&cps_syscon0 1 21>;
				status = "disabled";
			};

			cps_spi1: spi@700680 {
				compatible = "marvell,armada-380-spi";
				reg = <0x700680 0x50>;
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <4>;
				clocks = <&cps_syscon0 1 21>;
				status = "disabled";
			};

			cps_i2c0: i2c@701000 {
				compatible = "marvell,mv78230-i2c";
				reg = <0x701000 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&cps_syscon0 1 21>;
				status = "disabled";
			};

			cps_i2c1: i2c@701100 {
				compatible = "marvell,mv78230-i2c";
				reg = <0x701100 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&cps_syscon0 1 21>;
				status = "disabled";
			};

			cps_trng: trng@760000 {
				compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
				reg = <0x760000 0x7d>;
				interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&cps_syscon0 1 25>;
				status = "okay";
			};

			cps_crypto: crypto@800000 {
				compatible = "inside-secure,safexcel-eip197";
				reg = <0x800000 0x200000>;
				interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
				| IRQ_TYPE_LEVEL_HIGH)>,
					     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "mem", "ring0", "ring1",
						  "ring2", "ring3", "eip";
				clocks = <&cps_syscon0 1 26>;
				dma-mask = <0xff 0xffffffff>;
				status = "disabled";
			};
		};

		cps_pcie0: pcie@f4600000 {
			compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
			reg = <0 0xf4600000 0 0x10000>,
			      <0 0xfaf00000 0 0x80000>;
			reg-names = "ctrl", "config";
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			device_type = "pci";
			dma-coherent;
			msi-parent = <&gic_v2m0>;

			bus-range = <0 0xff>;
			ranges =
				/* downstream I/O */
				<0x81000000 0 0xfd000000 0  0xfd000000 0 0x10000
				/* non-prefetchable memory */
				0x82000000 0 0xfa000000 0  0xfa000000 0 0xf00000>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
			num-lanes = <1>;
			clocks = <&cps_syscon0 1 13>;
			status = "disabled";
		};

		cps_pcie1: pcie@f4620000 {
			compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
			reg = <0 0xf4620000 0 0x10000>,
			      <0 0xfbf00000 0 0x80000>;
			reg-names = "ctrl", "config";
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			device_type = "pci";
			dma-coherent;
			msi-parent = <&gic_v2m0>;

			bus-range = <0 0xff>;
			ranges =
				/* downstream I/O */
				<0x81000000 0 0xfd010000 0  0xfd010000 0 0x10000
				/* non-prefetchable memory */
				0x82000000 0 0xfb000000 0  0xfb000000 0 0xf00000>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
			interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;

			num-lanes = <1>;
			clocks = <&cps_syscon0 1 11>;
			status = "disabled";
		};

		cps_pcie2: pcie@f4640000 {
			compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
			reg = <0 0xf4640000 0 0x10000>,
			      <0 0xfcf00000 0 0x80000>;
			reg-names = "ctrl", "config";
			#address-cells = <3>;
			#size-cells = <2>;
			#interrupt-cells = <1>;
			device_type = "pci";
			dma-coherent;
			msi-parent = <&gic_v2m0>;

			bus-range = <0 0xff>;
			ranges =
				/* downstream I/O */
				<0x81000000 0 0xfd020000 0  0xfd020000 0 0x10000
				/* non-prefetchable memory */
				0x82000000 0 0xfc000000 0  0xfc000000 0 0xf00000>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
			interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;

			num-lanes = <1>;
			clocks = <&cps_syscon0 1 12>;
			status = "disabled";
		};
	};
};
Commit	Line	Data
4eef78a0 TP	1	/*
	2	* Copyright (C) 2016 Marvell Technology Group Ltd.
	3	*
	4	* This file is dual-licensed: you can use it either under the terms
	5	* of the GPLv2 or the X11 license, at your option. Note that this dual
	6	* licensing only applies to this file, and not this project as a
	7	* whole.
	8	*
	9	* a) This library is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of the
	12	* License, or (at your option) any later version.
	13	*
	14	* This library is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* Or, alternatively,
	20	*
	21	* b) Permission is hereby granted, free of charge, to any person
	22	* obtaining a copy of this software and associated documentation
	23	* files (the "Software"), to deal in the Software without
	24	* restriction, including without limitation the rights to use,
	25	* copy, modify, merge, publish, distribute, sublicense, and/or
	26	* sell copies of the Software, and to permit persons to whom the
	27	* Software is furnished to do so, subject to the following
	28	* conditions:
	29	*
	30	* The above copyright notice and this permission notice shall be
	31	* included in all copies or substantial portions of the Software.
	32	*
	33	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	34	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	35	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	36	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	37	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	38	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	39	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	40	* OTHER DEALINGS IN THE SOFTWARE.
	41	*/
	42
	43	/*
	44	* Device Tree file for Marvell Armada CP110 Slave.
	45	*/
	46
	47	/ {
	48	cp110-slave {
	49	#address-cells = <2>;
	50	#size-cells = <2>;
	51	compatible = "simple-bus";
	52	interrupt-parent = <&gic>;
	53	ranges;
	54
70347888	55	config-space@f4000000 {
4eef78a0 TP	56	#address-cells = <1>;
	57	#size-cells = <1>;
	58	compatible = "simple-bus";
	59	interrupt-parent = <&gic>;
	60	ranges = <0x0 0x0 0xf4000000 0x2000000>;
	61
bbedcf58 GC	62	cps_rtc: rtc@284000 {
	63	compatible = "marvell,armada-8k-rtc";
	64	reg = <0x284000 0x20>, <0x284080 0x24>;
	65	reg-names = "rtc", "rtc-soc";
	66	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
	67	};
	68
60894719 TP	69	cps_ethernet: ethernet@0 {
	70	compatible = "marvell,armada-7k-pp22";
	71	reg = <0x0 0x100000>, <0x129000 0xb000>;
	72	clocks = <&cps_syscon0 1 3>, <&cps_syscon0 1 9>, <&cps_syscon0 1 5>;
	73	clock-names = "pp_clk", "gop_clk", "mg_clk";
	74	status = "disabled";
	75	dma-coherent;
	76
	77	cps_eth0: eth0 {
	78	interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
	79	port-id = <0>;
	80	gop-port-id = <0>;
	81	status = "disabled";
	82	};
	83
	84	cps_eth1: eth1 {
	85	interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
	86	port-id = <1>;
	87	gop-port-id = <2>;
	88	status = "disabled";
	89	};
	90
	91	cps_eth2: eth2 {
	92	interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
	93	port-id = <2>;
	94	gop-port-id = <3>;
	95	status = "disabled";
	96	};
	97	};
	98
	99	cps_mdio: mdio@12a200 {
	100	#address-cells = <1>;
	101	#size-cells = <0>;
	102	compatible = "marvell,orion-mdio";
	103	reg = <0x12a200 0x10>;
e21a3b54	104	clocks = <&cps_syscon0 1 9>, <&cps_syscon0 1 5>;
60894719 TP	105	};
60894719 TP	106
4eef78a0 TP	107	cps_syscon0: system-controller@440000 {
	108	compatible = "marvell,cp110-system-controller0",
	109	"syscon";
	110	reg = <0x440000 0x1000>;
	111	#clock-cells = <2>;
	112	core-clock-output-names =
	113	"cps-apll", "cps-ppv2-core", "cps-eip",
	114	"cps-core", "cps-nand-core";
	115	gate-clock-output-names =
	116	"cps-audio", "cps-communit", "cps-nand",
	117	"cps-ppv2", "cps-sdio", "cps-mg-domain",
	118	"cps-mg-core", "cps-xor1", "cps-xor0",
	119	"cps-gop-dp", "none", "cps-pcie_x10",
	120	"cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
	121	"cps-sata", "cps-sata-usb", "cps-main",
d0979c07	122	"cps-sd-mmc-gop", "none", "none",
4eef78a0 TP	123	"cps-slow-io", "cps-usb3h0", "cps-usb3h1",
	124	"cps-usb3dev", "cps-eip150", "cps-eip197";
	125	};
	126
	127	cps_sata0: sata@540000 {
7292ff67 RK	128	compatible = "marvell,armada-8k-ahci",
7292ff67 RK	129	"generic-ahci";
4eef78a0 TP	130	reg = <0x540000 0x30000>;
	131	interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
	132	clocks = <&cps_syscon0 1 15>;
	133	status = "disabled";
	134	};
	135
	136	cps_usb3_0: usb3@500000 {
	137	compatible = "marvell,armada-8k-xhci",
	138	"generic-xhci";
	139	reg = <0x500000 0x4000>;
	140	dma-coherent;
	141	interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
	142	clocks = <&cps_syscon0 1 22>;
	143	status = "disabled";
	144	};
	145
	146	cps_usb3_1: usb3@510000 {
	147	compatible = "marvell,armada-8k-xhci",
	148	"generic-xhci";
	149	reg = <0x510000 0x4000>;
	150	dma-coherent;
	151	interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
	152	clocks = <&cps_syscon0 1 23>;
	153	status = "disabled";
	154	};
	155
	156	cps_xor0: xor@6a0000 {
	157	compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
	158	reg = <0x6a0000 0x1000>,
	159	<0x6b0000 0x1000>;
	160	dma-coherent;
	161	msi-parent = <&gic_v2m0>;
	162	clocks = <&cps_syscon0 1 8>;
	163	};
	164
	165	cps_xor1: xor@6c0000 {
	166	compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
	167	reg = <0x6c0000 0x1000>,
	168	<0x6d0000 0x1000>;
	169	dma-coherent;
	170	msi-parent = <&gic_v2m0>;
	171	clocks = <&cps_syscon0 1 7>;
	172	};
	173
	174	cps_spi0: spi@700600 {
	175	compatible = "marvell,armada-380-spi";
	176	reg = <0x700600 0x50>;
	177	#address-cells = <0x1>;
	178	#size-cells = <0x0>;
8d897006	179	cell-index = <3>;
2ec27be3	180	clocks = <&cps_syscon0 1 21>;
4eef78a0 TP	181	status = "disabled";
	182	};
	183
	184	cps_spi1: spi@700680 {
	185	compatible = "marvell,armada-380-spi";
	186	reg = <0x700680 0x50>;
	187	#address-cells = <1>;
	188	#size-cells = <0>;
8d897006	189	cell-index = <4>;
4eef78a0 TP	190	clocks = <&cps_syscon0 1 21>;
	191	status = "disabled";
	192	};
	193
	194	cps_i2c0: i2c@701000 {
	195	compatible = "marvell,mv78230-i2c";
	196	reg = <0x701000 0x20>;
	197	#address-cells = <1>;
	198	#size-cells = <0>;
	199	interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
	200	clocks = <&cps_syscon0 1 21>;
	201	status = "disabled";
	202	};
	203
	204	cps_i2c1: i2c@701100 {
	205	compatible = "marvell,mv78230-i2c";
	206	reg = <0x701100 0x20>;
	207	#address-cells = <1>;
	208	#size-cells = <0>;
	209	interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
	210	clocks = <&cps_syscon0 1 21>;
	211	status = "disabled";
	212	};
a0743c15 RP	213
	214	cps_trng: trng@760000 {
	215	compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
	216	reg = <0x760000 0x7d>;
	217	interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
	218	clocks = <&cps_syscon0 1 25>;
	219	status = "okay";
	220	};
973020fd AT	221
	222	cps_crypto: crypto@800000 {
	223	compatible = "inside-secure,safexcel-eip197";
	224	reg = <0x800000 0x200000>;
	225	interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
	226	\| IRQ_TYPE_LEVEL_HIGH)>,
	227	<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
	228	<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
	229	<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
	230	<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
	231	<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>;
	232	interrupt-names = "mem", "ring0", "ring1",
	233	"ring2", "ring3", "eip";
	234	clocks = <&cps_syscon0 1 26>;
b1a97f86	235	dma-mask = <0xff 0xffffffff>;
973020fd AT	236	status = "disabled";
973020fd AT	237	};
4eef78a0 TP	238	};
	239
	240	cps_pcie0: pcie@f4600000 {
	241	compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
	242	reg = <0 0xf4600000 0 0x10000>,
	243	<0 0xfaf00000 0 0x80000>;
	244	reg-names = "ctrl", "config";
	245	#address-cells = <3>;
	246	#size-cells = <2>;
	247	#interrupt-cells = <1>;
	248	device_type = "pci";
	249	dma-coherent;
93970e67	250	msi-parent = <&gic_v2m0>;
4eef78a0 TP	251
	252	bus-range = <0 0xff>;
	253	ranges =
	254	/* downstream I/O */
	255	<0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000
	256	/* non-prefetchable memory */
	257	0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
	258	interrupt-map-mask = <0 0 0 0>;
	259	interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
	260	interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
	261	num-lanes = <1>;
	262	clocks = <&cps_syscon0 1 13>;
	263	status = "disabled";
	264	};
	265
	266	cps_pcie1: pcie@f4620000 {
	267	compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
	268	reg = <0 0xf4620000 0 0x10000>,
	269	<0 0xfbf00000 0 0x80000>;
	270	reg-names = "ctrl", "config";
	271	#address-cells = <3>;
	272	#size-cells = <2>;
	273	#interrupt-cells = <1>;
	274	device_type = "pci";
	275	dma-coherent;
93970e67	276	msi-parent = <&gic_v2m0>;
4eef78a0 TP	277
	278	bus-range = <0 0xff>;
	279	ranges =
	280	/* downstream I/O */
	281	<0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000
	282	/* non-prefetchable memory */
	283	0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
	284	interrupt-map-mask = <0 0 0 0>;
	285	interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
	286	interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
	287
	288	num-lanes = <1>;
	289	clocks = <&cps_syscon0 1 11>;
	290	status = "disabled";
	291	};
	292
	293	cps_pcie2: pcie@f4640000 {
	294	compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
	295	reg = <0 0xf4640000 0 0x10000>,
	296	<0 0xfcf00000 0 0x80000>;
	297	reg-names = "ctrl", "config";
	298	#address-cells = <3>;
	299	#size-cells = <2>;
	300	#interrupt-cells = <1>;
	301	device_type = "pci";
	302	dma-coherent;
93970e67	303	msi-parent = <&gic_v2m0>;
4eef78a0 TP	304
	305	bus-range = <0 0xff>;
	306	ranges =
	307	/* downstream I/O */
	308	<0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000
	309	/* non-prefetchable memory */
	310	0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
	311	interrupt-map-mask = <0 0 0 0>;
	312	interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
	313	interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
	314
	315	num-lanes = <1>;
	316	clocks = <&cps_syscon0 1 12>;
	317	status = "disabled";
	318	};
	319	};
	320	};