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Merge tag 'pci-v4.10-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaa...
[mirror_ubuntu-focal-kernel.git] / arch / arm64 / boot / dts / nvidia / tegra210.dtsi
CommitLineData
742af7e7
TR		 1#include <dt-bindings/clock/tegra210-car.h>
2#include <dt-bindings/gpio/tegra-gpio.h>
3#include <dt-bindings/memory/tegra210-mc.h>
4#include <dt-bindings/pinctrl/pinctrl-tegra.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
e2bed1eb 6#include <dt-bindings/thermal/tegra124-soctherm.h>
742af7e7
TR		 7
8/ {
9 compatible = "nvidia,tegra210";
10 interrupt-parent = <&lic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
13
589a2d3f
TR		 14 pcie-controller@01003000 {
15 compatible = "nvidia,tegra210-pcie";
16 device_type = "pci";
17 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
18 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
19 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
20 reg-names = "pads", "afi", "cs";
21 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
22 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
23 interrupt-names = "intr", "msi";
24
25 #interrupt-cells = <1>;
26 interrupt-map-mask = <0 0 0 0>;
27 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
28
29 bus-range = <0x00 0xff>;
30 #address-cells = <3>;
31 #size-cells = <2>;
32
33 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
34 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
35 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
36 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
37 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
38
39 clocks = <&tegra_car TEGRA210_CLK_PCIE>,
40 <&tegra_car TEGRA210_CLK_AFI>,
41 <&tegra_car TEGRA210_CLK_PLL_E>,
42 <&tegra_car TEGRA210_CLK_CML0>;
43 clock-names = "pex", "afi", "pll_e", "cml";
44 resets = <&tegra_car 70>,
45 <&tegra_car 72>,
46 <&tegra_car 74>;
47 reset-names = "pex", "afi", "pcie_x";
48 status = "disabled";
49
50 pci@1,0 {
51 device_type = "pci";
52 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
53 reg = <0x000800 0 0 0 0>;
54 status = "disabled";
55
56 #address-cells = <3>;
57 #size-cells = <2>;
58 ranges;
59
60 nvidia,num-lanes = <4>;
61 };
62
63 pci@2,0 {
64 device_type = "pci";
65 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
66 reg = <0x001000 0 0 0 0>;
67 status = "disabled";
68
69 #address-cells = <3>;
70 #size-cells = <2>;
71 ranges;
72
73 nvidia,num-lanes = <1>;
74 };
75 };
76
be70771d 77 host1x@50000000 {
742af7e7
TR		 78 compatible = "nvidia,tegra210-host1x", "simple-bus";
79 reg = <0x0 0x50000000 0x0 0x00034000>;
80 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
81 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
82 clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
83 clock-names = "host1x";
84 resets = <&tegra_car 28>;
85 reset-names = "host1x";
86
87 #address-cells = <2>;
88 #size-cells = <2>;
89
90 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
91
be70771d 92 dpaux1: dpaux@54040000 {
742af7e7
TR		 93 compatible = "nvidia,tegra210-dpaux";
94 reg = <0x0 0x54040000 0x0 0x00040000>;
95 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
96 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
97 <&tegra_car TEGRA210_CLK_PLL_DP>;
98 clock-names = "dpaux", "parent";
99 resets = <&tegra_car 207>;
100 reset-names = "dpaux";
96d1f078 101 power-domains = <&pd_sor>;
742af7e7 102 status = "disabled";
66b2d6e9
JH		 103
104 state_dpaux1_aux: pinmux-aux {
105 groups = "dpaux-io";
106 function = "aux";
107 };
108
109 state_dpaux1_i2c: pinmux-i2c {
110 groups = "dpaux-io";
111 function = "i2c";
112 };
113
114 state_dpaux1_off: pinmux-off {
115 groups = "dpaux-io";
116 function = "off";
117 };
118
119 i2c-bus {
120 #address-cells = <1>;
121 #size-cells = <0>;
122 };
742af7e7
TR		 123 };
124
be70771d 125 vi@54080000 {
742af7e7
TR		 126 compatible = "nvidia,tegra210-vi";
127 reg = <0x0 0x54080000 0x0 0x00040000>;
128 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
129 status = "disabled";
130 };
131
be70771d 132 tsec@54100000 {
742af7e7
TR		 133 compatible = "nvidia,tegra210-tsec";
134 reg = <0x0 0x54100000 0x0 0x00040000>;
135 };
136
be70771d 137 dc@54200000 {
742af7e7
TR		 138 compatible = "nvidia,tegra210-dc";
139 reg = <0x0 0x54200000 0x0 0x00040000>;
140 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
141 clocks = <&tegra_car TEGRA210_CLK_DISP1>,
142 <&tegra_car TEGRA210_CLK_PLL_P>;
143 clock-names = "dc", "parent";
144 resets = <&tegra_car 27>;
145 reset-names = "dc";
146
147 iommus = <&mc TEGRA_SWGROUP_DC>;
148
149 nvidia,head = <0>;
150 };
151
be70771d 152 dc@54240000 {
742af7e7
TR		 153 compatible = "nvidia,tegra210-dc";
154 reg = <0x0 0x54240000 0x0 0x00040000>;
155 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&tegra_car TEGRA210_CLK_DISP2>,
157 <&tegra_car TEGRA210_CLK_PLL_P>;
158 clock-names = "dc", "parent";
159 resets = <&tegra_car 26>;
160 reset-names = "dc";
161
162 iommus = <&mc TEGRA_SWGROUP_DCB>;
163
164 nvidia,head = <1>;
165 };
166
be70771d 167 dsi@54300000 {
742af7e7
TR		 168 compatible = "nvidia,tegra210-dsi";
169 reg = <0x0 0x54300000 0x0 0x00040000>;
170 clocks = <&tegra_car TEGRA210_CLK_DSIA>,
171 <&tegra_car TEGRA210_CLK_DSIALP>,
172 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
173 clock-names = "dsi", "lp", "parent";
174 resets = <&tegra_car 48>;
175 reset-names = "dsi";
96d1f078 176 power-domains = <&pd_sor>;
742af7e7
TR		 177 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
178
179 status = "disabled";
180
181 #address-cells = <1>;
182 #size-cells = <0>;
183 };
184
be70771d 185 vic@54340000 {
742af7e7
TR		 186 compatible = "nvidia,tegra210-vic";
187 reg = <0x0 0x54340000 0x0 0x00040000>;
188 status = "disabled";
189 };
190
be70771d 191 nvjpg@54380000 {
742af7e7
TR		 192 compatible = "nvidia,tegra210-nvjpg";
193 reg = <0x0 0x54380000 0x0 0x00040000>;
194 status = "disabled";
195 };
196
be70771d 197 dsi@54400000 {
742af7e7
TR		 198 compatible = "nvidia,tegra210-dsi";
199 reg = <0x0 0x54400000 0x0 0x00040000>;
200 clocks = <&tegra_car TEGRA210_CLK_DSIB>,
201 <&tegra_car TEGRA210_CLK_DSIBLP>,
202 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
203 clock-names = "dsi", "lp", "parent";
204 resets = <&tegra_car 82>;
205 reset-names = "dsi";
96d1f078 206 power-domains = <&pd_sor>;
742af7e7
TR		 207 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
208
209 status = "disabled";
210
211 #address-cells = <1>;
212 #size-cells = <0>;
213 };
214
be70771d 215 nvdec@54480000 {
742af7e7
TR		 216 compatible = "nvidia,tegra210-nvdec";
217 reg = <0x0 0x54480000 0x0 0x00040000>;
218 status = "disabled";
219 };
220
be70771d 221 nvenc@544c0000 {
742af7e7
TR		 222 compatible = "nvidia,tegra210-nvenc";
223 reg = <0x0 0x544c0000 0x0 0x00040000>;
224 status = "disabled";
225 };
226
be70771d 227 tsec@54500000 {
742af7e7
TR		 228 compatible = "nvidia,tegra210-tsec";
229 reg = <0x0 0x54500000 0x0 0x00040000>;
230 status = "disabled";
231 };
232
be70771d 233 sor@54540000 {
742af7e7
TR		 234 compatible = "nvidia,tegra210-sor";
235 reg = <0x0 0x54540000 0x0 0x00040000>;
236 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
238 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
239 <&tegra_car TEGRA210_CLK_PLL_DP>,
240 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
241 clock-names = "sor", "parent", "dp", "safe";
242 resets = <&tegra_car 182>;
243 reset-names = "sor";
66b2d6e9
JH		 244 pinctrl-0 = <&state_dpaux_aux>;
245 pinctrl-1 = <&state_dpaux_i2c>;
246 pinctrl-2 = <&state_dpaux_off>;
247 pinctrl-names = "aux", "i2c", "off";
96d1f078 248 power-domains = <&pd_sor>;
742af7e7
TR		 249 status = "disabled";
250 };
251
be70771d 252 sor@54580000 {
742af7e7
TR		 253 compatible = "nvidia,tegra210-sor1";
254 reg = <0x0 0x54580000 0x0 0x00040000>;
255 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&tegra_car TEGRA210_CLK_SOR1>,
237d5cc7 257 <&tegra_car TEGRA210_CLK_SOR1_SRC>,
742af7e7
TR		 258 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
259 <&tegra_car TEGRA210_CLK_PLL_DP>,
260 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
237d5cc7 261 clock-names = "sor", "source", "parent", "dp", "safe";
742af7e7
TR		 262 resets = <&tegra_car 183>;
263 reset-names = "sor";
66b2d6e9
JH		 264 pinctrl-0 = <&state_dpaux1_aux>;
265 pinctrl-1 = <&state_dpaux1_i2c>;
266 pinctrl-2 = <&state_dpaux1_off>;
267 pinctrl-names = "aux", "i2c", "off";
96d1f078 268 power-domains = <&pd_sor>;
742af7e7
TR		 269 status = "disabled";
270 };
271
be70771d 272 dpaux: dpaux@545c0000 {
742af7e7
TR		 273 compatible = "nvidia,tegra124-dpaux";
274 reg = <0x0 0x545c0000 0x0 0x00040000>;
275 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
277 <&tegra_car TEGRA210_CLK_PLL_DP>;
278 clock-names = "dpaux", "parent";
279 resets = <&tegra_car 181>;
280 reset-names = "dpaux";
96d1f078 281 power-domains = <&pd_sor>;
742af7e7 282 status = "disabled";
66b2d6e9
JH		 283
284 state_dpaux_aux: pinmux-aux {
285 groups = "dpaux-io";
286 function = "aux";
287 };
288
289 state_dpaux_i2c: pinmux-i2c {
290 groups = "dpaux-io";
291 function = "i2c";
292 };
293
294 state_dpaux_off: pinmux-off {
295 groups = "dpaux-io";
296 function = "off";
297 };
298
299 i2c-bus {
300 #address-cells = <1>;
301 #size-cells = <0>;
302 };
742af7e7
TR		 303 };
304
be70771d 305 isp@54600000 {
742af7e7
TR		 306 compatible = "nvidia,tegra210-isp";
307 reg = <0x0 0x54600000 0x0 0x00040000>;
308 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
309 status = "disabled";
310 };
311
be70771d 312 isp@54680000 {
742af7e7
TR		 313 compatible = "nvidia,tegra210-isp";
314 reg = <0x0 0x54680000 0x0 0x00040000>;
315 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
316 status = "disabled";
317 };
318
be70771d 319 i2c@546c0000 {
742af7e7
TR		 320 compatible = "nvidia,tegra210-i2c-vi";
321 reg = <0x0 0x546c0000 0x0 0x00040000>;
322 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
323 status = "disabled";
324 };
325 };
326
be70771d 327 gic: interrupt-controller@50041000 {
742af7e7
TR		 328 compatible = "arm,gic-400";
329 #interrupt-cells = <3>;
330 interrupt-controller;
331 reg = <0x0 0x50041000 0x0 0x1000>,
332 <0x0 0x50042000 0x0 0x2000>,
333 <0x0 0x50044000 0x0 0x2000>,
334 <0x0 0x50046000 0x0 0x2000>;
335 interrupts = <GIC_PPI 9
336 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
337 interrupt-parent = <&gic>;
338 };
339
be70771d 340 gpu@57000000 {
742af7e7
TR		 341 compatible = "nvidia,gm20b";
342 reg = <0x0 0x57000000 0x0 0x01000000>,
343 <0x0 0x58000000 0x0 0x01000000>;
344 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
346 interrupt-names = "stall", "nonstall";
347 clocks = <&tegra_car TEGRA210_CLK_GPU>,
4a0778e9
AC		 348 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
349 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
350 clock-names = "gpu", "pwr", "ref";
742af7e7
TR		 351 resets = <&tegra_car 184>;
352 reset-names = "gpu";
30f949bc
AC		 353
354 iommus = <&mc TEGRA_SWGROUP_GPU>;
355
742af7e7
TR		 356 status = "disabled";
357 };
358
be70771d 359 lic: interrupt-controller@60004000 {
742af7e7
TR		 360 compatible = "nvidia,tegra210-ictlr";
361 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
362 <0x0 0x60004100 0x0 0x40>, /* secondary controller */
363 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
364 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
365 <0x0 0x60004400 0x0 0x40>, /* quinary controller */
366 <0x0 0x60004500 0x0 0x40>; /* senary controller */
367 interrupt-controller;
368 #interrupt-cells = <3>;
369 interrupt-parent = <&gic>;
370 };
371
be70771d 372 timer@60005000 {
742af7e7
TR		 373 compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer";
374 reg = <0x0 0x60005000 0x0 0x400>;
375 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
376 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
377 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
378 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
379 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
380 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&tegra_car TEGRA210_CLK_TIMER>;
382 clock-names = "timer";
383 };
384
be70771d 385 tegra_car: clock@60006000 {
742af7e7
TR		 386 compatible = "nvidia,tegra210-car";
387 reg = <0x0 0x60006000 0x0 0x1000>;
388 #clock-cells = <1>;
389 #reset-cells = <1>;
390 };
391
be70771d 392 flow-controller@60007000 {
742af7e7
TR		 393 compatible = "nvidia,tegra210-flowctrl";
394 reg = <0x0 0x60007000 0x0 0x1000>;
395 };
396
be70771d 397 gpio: gpio@6000d000 {
01665512 398 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
742af7e7
TR		 399 reg = <0x0 0x6000d000 0x0 0x1000>;
400 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
407 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
408 #gpio-cells = <2>;
409 gpio-controller;
410 #interrupt-cells = <2>;
411 interrupt-controller;
412 };
413
be70771d 414 apbdma: dma@60020000 {
742af7e7
TR		 415 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
416 reg = <0x0 0x60020000 0x0 0x1400>;
417 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
425 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
431 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
433 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
435 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
436 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
445 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
447 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
448 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
450 clock-names = "dma";
451 resets = <&tegra_car 34>;
452 reset-names = "dma";
453 #dma-cells = <1>;
454 };
455
be70771d 456 apbmisc@70000800 {
742af7e7
TR		 457 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
458 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
459 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
460 };
461
be70771d 462 pinmux: pinmux@700008d4 {
742af7e7
TR		 463 compatible = "nvidia,tegra210-pinmux";
464 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
465 <0x0 0x70003000 0x0 0x294>; /* Mux registers */
466 };
467
468 /*
469 * There are two serial driver i.e. 8250 based simple serial
470 * driver and APB DMA based serial driver for higher baudrate
ef769e32 471 * and performance. To enable the 8250 based driver, the compatible
742af7e7 472 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
68cd8b2e 473 * the APB DMA based serial driver, the compatible is
742af7e7
TR		 474 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
475 */
be70771d 476 uarta: serial@70006000 {
742af7e7
TR		 477 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
478 reg = <0x0 0x70006000 0x0 0x40>;
479 reg-shift = <2>;
480 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&tegra_car TEGRA210_CLK_UARTA>;
482 clock-names = "serial";
483 resets = <&tegra_car 6>;
484 reset-names = "serial";
485 dmas = <&apbdma 8>, <&apbdma 8>;
486 dma-names = "rx", "tx";
487 status = "disabled";
488 };
489
be70771d 490 uartb: serial@70006040 {
742af7e7
TR		 491 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
492 reg = <0x0 0x70006040 0x0 0x40>;
493 reg-shift = <2>;
494 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&tegra_car TEGRA210_CLK_UARTB>;
496 clock-names = "serial";
497 resets = <&tegra_car 7>;
498 reset-names = "serial";
499 dmas = <&apbdma 9>, <&apbdma 9>;
500 dma-names = "rx", "tx";
501 status = "disabled";
502 };
503
be70771d 504 uartc: serial@70006200 {
742af7e7
TR		 505 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
506 reg = <0x0 0x70006200 0x0 0x40>;
507 reg-shift = <2>;
508 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&tegra_car TEGRA210_CLK_UARTC>;
510 clock-names = "serial";
511 resets = <&tegra_car 55>;
512 reset-names = "serial";
513 dmas = <&apbdma 10>, <&apbdma 10>;
514 dma-names = "rx", "tx";
515 status = "disabled";
516 };
517
be70771d 518 uartd: serial@70006300 {
742af7e7
TR		 519 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
520 reg = <0x0 0x70006300 0x0 0x40>;
521 reg-shift = <2>;
522 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&tegra_car TEGRA210_CLK_UARTD>;
524 clock-names = "serial";
525 resets = <&tegra_car 65>;
526 reset-names = "serial";
527 dmas = <&apbdma 19>, <&apbdma 19>;
528 dma-names = "rx", "tx";
529 status = "disabled";
530 };
531
be70771d 532 pwm: pwm@7000a000 {
742af7e7
TR		 533 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
534 reg = <0x0 0x7000a000 0x0 0x100>;
535 #pwm-cells = <2>;
536 clocks = <&tegra_car TEGRA210_CLK_PWM>;
537 clock-names = "pwm";
538 resets = <&tegra_car 17>;
539 reset-names = "pwm";
540 status = "disabled";
541 };
542
be70771d 543 i2c@7000c000 {
742af7e7
TR		 544 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
545 reg = <0x0 0x7000c000 0x0 0x100>;
546 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
547 #address-cells = <1>;
548 #size-cells = <0>;
549 clocks = <&tegra_car TEGRA210_CLK_I2C1>;
550 clock-names = "div-clk";
551 resets = <&tegra_car 12>;
552 reset-names = "i2c";
553 dmas = <&apbdma 21>, <&apbdma 21>;
554 dma-names = "rx", "tx";
555 status = "disabled";
556 };
557
be70771d 558 i2c@7000c400 {
742af7e7
TR		 559 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
560 reg = <0x0 0x7000c400 0x0 0x100>;
561 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
562 #address-cells = <1>;
563 #size-cells = <0>;
564 clocks = <&tegra_car TEGRA210_CLK_I2C2>;
565 clock-names = "div-clk";
566 resets = <&tegra_car 54>;
567 reset-names = "i2c";
568 dmas = <&apbdma 22>, <&apbdma 22>;
569 dma-names = "rx", "tx";
570 status = "disabled";
571 };
572
be70771d 573 i2c@7000c500 {
742af7e7
TR		 574 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
575 reg = <0x0 0x7000c500 0x0 0x100>;
576 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
577 #address-cells = <1>;
578 #size-cells = <0>;
579 clocks = <&tegra_car TEGRA210_CLK_I2C3>;
580 clock-names = "div-clk";
581 resets = <&tegra_car 67>;
582 reset-names = "i2c";
583 dmas = <&apbdma 23>, <&apbdma 23>;
584 dma-names = "rx", "tx";
585 status = "disabled";
586 };
587
be70771d 588 i2c@7000c700 {
742af7e7
TR		 589 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
590 reg = <0x0 0x7000c700 0x0 0x100>;
591 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
592 #address-cells = <1>;
593 #size-cells = <0>;
594 clocks = <&tegra_car TEGRA210_CLK_I2C4>;
595 clock-names = "div-clk";
596 resets = <&tegra_car 103>;
597 reset-names = "i2c";
598 dmas = <&apbdma 26>, <&apbdma 26>;
599 dma-names = "rx", "tx";
66b2d6e9
JH		 600 pinctrl-0 = <&state_dpaux1_i2c>;
601 pinctrl-1 = <&state_dpaux1_off>;
602 pinctrl-names = "default", "idle";
742af7e7
TR		 603 status = "disabled";
604 };
605
be70771d 606 i2c@7000d000 {
742af7e7
TR		 607 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
608 reg = <0x0 0x7000d000 0x0 0x100>;
609 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
610 #address-cells = <1>;
611 #size-cells = <0>;
612 clocks = <&tegra_car TEGRA210_CLK_I2C5>;
613 clock-names = "div-clk";
614 resets = <&tegra_car 47>;
615 reset-names = "i2c";
616 dmas = <&apbdma 24>, <&apbdma 24>;
617 dma-names = "rx", "tx";
618 status = "disabled";
619 };
620
be70771d 621 i2c@7000d100 {
742af7e7
TR		 622 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
623 reg = <0x0 0x7000d100 0x0 0x100>;
624 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
625 #address-cells = <1>;
626 #size-cells = <0>;
627 clocks = <&tegra_car TEGRA210_CLK_I2C6>;
628 clock-names = "div-clk";
629 resets = <&tegra_car 166>;
630 reset-names = "i2c";
631 dmas = <&apbdma 30>, <&apbdma 30>;
632 dma-names = "rx", "tx";
66b2d6e9
JH		 633 pinctrl-0 = <&state_dpaux_i2c>;
634 pinctrl-1 = <&state_dpaux_off>;
635 pinctrl-names = "default", "idle";
742af7e7
TR		 636 status = "disabled";
637 };
638
be70771d 639 spi@7000d400 {
742af7e7
TR		 640 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
641 reg = <0x0 0x7000d400 0x0 0x200>;
642 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
643 #address-cells = <1>;
644 #size-cells = <0>;
645 clocks = <&tegra_car TEGRA210_CLK_SBC1>;
646 clock-names = "spi";
647 resets = <&tegra_car 41>;
648 reset-names = "spi";
649 dmas = <&apbdma 15>, <&apbdma 15>;
650 dma-names = "rx", "tx";
651 status = "disabled";
652 };
653
be70771d 654 spi@7000d600 {
742af7e7
TR		 655 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
656 reg = <0x0 0x7000d600 0x0 0x200>;
657 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
658 #address-cells = <1>;
659 #size-cells = <0>;
660 clocks = <&tegra_car TEGRA210_CLK_SBC2>;
661 clock-names = "spi";
662 resets = <&tegra_car 44>;
663 reset-names = "spi";
664 dmas = <&apbdma 16>, <&apbdma 16>;
665 dma-names = "rx", "tx";
666 status = "disabled";
667 };
668
be70771d 669 spi@7000d800 {
742af7e7
TR		 670 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
671 reg = <0x0 0x7000d800 0x0 0x200>;
672 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
673 #address-cells = <1>;
674 #size-cells = <0>;
675 clocks = <&tegra_car TEGRA210_CLK_SBC3>;
676 clock-names = "spi";
677 resets = <&tegra_car 46>;
678 reset-names = "spi";
679 dmas = <&apbdma 17>, <&apbdma 17>;
680 dma-names = "rx", "tx";
681 status = "disabled";
682 };
683
be70771d 684 spi@7000da00 {
742af7e7
TR		 685 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
686 reg = <0x0 0x7000da00 0x0 0x200>;
687 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
688 #address-cells = <1>;
689 #size-cells = <0>;
690 clocks = <&tegra_car TEGRA210_CLK_SBC4>;
691 clock-names = "spi";
692 resets = <&tegra_car 68>;
693 reset-names = "spi";
694 dmas = <&apbdma 18>, <&apbdma 18>;
695 dma-names = "rx", "tx";
696 status = "disabled";
697 };
698
be70771d 699 rtc@7000e000 {
742af7e7
TR		 700 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
701 reg = <0x0 0x7000e000 0x0 0x100>;
702 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
703 clocks = <&tegra_car TEGRA210_CLK_RTC>;
704 clock-names = "rtc";
705 };
706
be70771d 707 pmc: pmc@7000e400 {
742af7e7
TR		 708 compatible = "nvidia,tegra210-pmc";
709 reg = <0x0 0x7000e400 0x0 0x400>;
710 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
711 clock-names = "pclk", "clk32k_in";
c2b82445
JH		 712
713 powergates {
714 pd_audio: aud {
715 clocks = <&tegra_car TEGRA210_CLK_APE>,
716 <&tegra_car TEGRA210_CLK_APB2APE>;
717 resets = <&tegra_car 198>;
718 #power-domain-cells = <0>;
719 };
241f02ba 720
96d1f078
JH		 721 pd_sor: sor {
722 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
723 <&tegra_car TEGRA210_CLK_SOR1>,
724 <&tegra_car TEGRA210_CLK_CSI>,
725 <&tegra_car TEGRA210_CLK_DSIA>,
726 <&tegra_car TEGRA210_CLK_DSIB>,
727 <&tegra_car TEGRA210_CLK_DPAUX>,
728 <&tegra_car TEGRA210_CLK_DPAUX1>,
729 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
730 resets = <&tegra_car TEGRA210_CLK_SOR0>,
731 <&tegra_car TEGRA210_CLK_SOR1>,
732 <&tegra_car TEGRA210_CLK_CSI>,
733 <&tegra_car TEGRA210_CLK_DSIA>,
734 <&tegra_car TEGRA210_CLK_DSIB>,
735 <&tegra_car TEGRA210_CLK_DPAUX>,
736 <&tegra_car TEGRA210_CLK_DPAUX1>,
737 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
738 #power-domain-cells = <0>;
739 };
740
241f02ba
JH		 741 pd_xusbss: xusba {
742 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
241f02ba 743 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
241f02ba
JH		 744 #power-domain-cells = <0>;
745 };
746
747 pd_xusbdev: xusbb {
748 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
241f02ba 749 resets = <&tegra_car 95>;
241f02ba
JH		 750 #power-domain-cells = <0>;
751 };
752
753 pd_xusbhost: xusbc {
754 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
241f02ba 755 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
241f02ba
JH		 756 #power-domain-cells = <0>;
757 };
c2b82445 758 };
742af7e7
TR		 759 };
760
be70771d 761 fuse@7000f800 {
742af7e7
TR		 762 compatible = "nvidia,tegra210-efuse";
763 reg = <0x0 0x7000f800 0x0 0x400>;
764 clocks = <&tegra_car TEGRA210_CLK_FUSE>;
765 clock-names = "fuse";
766 resets = <&tegra_car 39>;
767 reset-names = "fuse";
768 };
769
be70771d 770 mc: memory-controller@70019000 {
742af7e7
TR		 771 compatible = "nvidia,tegra210-mc";
772 reg = <0x0 0x70019000 0x0 0x1000>;
773 clocks = <&tegra_car TEGRA210_CLK_MC>;
774 clock-names = "mc";
775
776 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
777
778 #iommu-cells = <1>;
779 };
780
be70771d 781 hda@70030000 {
742af7e7
TR		 782 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
783 reg = <0x0 0x70030000 0x0 0x10000>;
784 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&tegra_car TEGRA210_CLK_HDA>,
786 <&tegra_car TEGRA210_CLK_HDA2HDMI>,
787 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
788 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
789 resets = <&tegra_car 125>, /* hda */
790 <&tegra_car 128>, /* hda2hdmi */
791 <&tegra_car 111>; /* hda2codec_2x */
792 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
793 status = "disabled";
794 };
795
e7a99ac2
TR		 796 usb@70090000 {
797 compatible = "nvidia,tegra210-xusb";
798 reg = <0x0 0x70090000 0x0 0x8000>,
799 <0x0 0x70098000 0x0 0x1000>,
800 <0x0 0x70099000 0x0 0x1000>;
801 reg-names = "hcd", "fpci", "ipfs";
802
803 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
9168e1db 804 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
e7a99ac2
TR		 805
806 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
807 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
808 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
809 <&tegra_car TEGRA210_CLK_XUSB_SS>,
810 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
811 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
812 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
813 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
814 <&tegra_car TEGRA210_CLK_PLL_U_480M>,
815 <&tegra_car TEGRA210_CLK_CLK_M>,
816 <&tegra_car TEGRA210_CLK_PLL_E>;
817 clock-names = "xusb_host", "xusb_host_src",
818 "xusb_falcon_src", "xusb_ss",
819 "xusb_ss_div2", "xusb_ss_src",
820 "xusb_hs_src", "xusb_fs_src",
821 "pll_u_480m", "clk_m", "pll_e";
822 resets = <&tegra_car 89>, <&tegra_car 156>,
823 <&tegra_car 143>;
824 reset-names = "xusb_host", "xusb_ss", "xusb_src";
825
826 nvidia,xusb-padctl = <&padctl>;
827
828 status = "disabled";
829 };
830
4e07ac90
TR		 831 padctl: padctl@7009f000 {
832 compatible = "nvidia,tegra210-xusb-padctl";
833 reg = <0x0 0x7009f000 0x0 0x1000>;
834 resets = <&tegra_car 142>;
835 reset-names = "padctl";
836
837 status = "disabled";
838
839 pads {
840 usb2 {
841 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
842 clock-names = "trk";
843 status = "disabled";
844
845 lanes {
846 usb2-0 {
847 status = "disabled";
848 #phy-cells = <0>;
849 };
850
851 usb2-1 {
852 status = "disabled";
853 #phy-cells = <0>;
854 };
855
856 usb2-2 {
857 status = "disabled";
858 #phy-cells = <0>;
859 };
860
861 usb2-3 {
862 status = "disabled";
863 #phy-cells = <0>;
864 };
865 };
866 };
867
868 hsic {
869 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
870 clock-names = "trk";
871 status = "disabled";
872
873 lanes {
874 hsic-0 {
875 status = "disabled";
876 #phy-cells = <0>;
877 };
878
879 hsic-1 {
880 status = "disabled";
881 #phy-cells = <0>;
882 };
883 };
884 };
885
886 pcie {
887 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
888 clock-names = "pll";
889 resets = <&tegra_car 205>;
890 reset-names = "phy";
891 status = "disabled";
892
893 lanes {
894 pcie-0 {
895 status = "disabled";
896 #phy-cells = <0>;
897 };
898
899 pcie-1 {
900 status = "disabled";
901 #phy-cells = <0>;
902 };
903
904 pcie-2 {
905 status = "disabled";
906 #phy-cells = <0>;
907 };
908
909 pcie-3 {
910 status = "disabled";
911 #phy-cells = <0>;
912 };
913
914 pcie-4 {
915 status = "disabled";
916 #phy-cells = <0>;
917 };
918
919 pcie-5 {
920 status = "disabled";
921 #phy-cells = <0>;
922 };
923
924 pcie-6 {
925 status = "disabled";
926 #phy-cells = <0>;
927 };
928 };
929 };
930
931 sata {
932 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
933 clock-names = "pll";
934 resets = <&tegra_car 204>;
935 reset-names = "phy";
936 status = "disabled";
937
938 lanes {
939 sata-0 {
940 status = "disabled";
941 #phy-cells = <0>;
942 };
943 };
944 };
945 };
946
947 ports {
948 usb2-0 {
949 status = "disabled";
950 };
951
952 usb2-1 {
953 status = "disabled";
954 };
955
956 usb2-2 {
957 status = "disabled";
958 };
959
960 usb2-3 {
961 status = "disabled";
962 };
963
964 hsic-0 {
965 status = "disabled";
966 };
967
968 usb3-0 {
969 status = "disabled";
970 };
971
972 usb3-1 {
973 status = "disabled";
974 };
975
976 usb3-2 {
977 status = "disabled";
978 };
979
980 usb3-3 {
981 status = "disabled";
982 };
983 };
984 };
985
be70771d 986 sdhci@700b0000 {
742af7e7
TR		 987 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
988 reg = <0x0 0x700b0000 0x0 0x200>;
989 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
990 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
991 clock-names = "sdhci";
992 resets = <&tegra_car 14>;
993 reset-names = "sdhci";
994 status = "disabled";
995 };
996
be70771d 997 sdhci@700b0200 {
742af7e7
TR		 998 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
999 reg = <0x0 0x700b0200 0x0 0x200>;
1000 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1001 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
1002 clock-names = "sdhci";
1003 resets = <&tegra_car 9>;
1004 reset-names = "sdhci";
1005 status = "disabled";
1006 };
1007
be70771d 1008 sdhci@700b0400 {
742af7e7
TR		 1009 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1010 reg = <0x0 0x700b0400 0x0 0x200>;
1011 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1012 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
1013 clock-names = "sdhci";
1014 resets = <&tegra_car 69>;
1015 reset-names = "sdhci";
1016 status = "disabled";
1017 };
1018
be70771d 1019 sdhci@700b0600 {
742af7e7
TR		 1020 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1021 reg = <0x0 0x700b0600 0x0 0x200>;
1022 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1023 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
1024 clock-names = "sdhci";
1025 resets = <&tegra_car 15>;
1026 reset-names = "sdhci";
1027 status = "disabled";
1028 };
1029
be70771d 1030 mipi: mipi@700e3000 {
742af7e7
TR		 1031 compatible = "nvidia,tegra210-mipi";
1032 reg = <0x0 0x700e3000 0x0 0x100>;
1033 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
1034 clock-names = "mipi-cal";
96d1f078 1035 power-domains = <&pd_sor>;
742af7e7
TR		 1036 #nvidia,mipi-calibrate-cells = <1>;
1037 };
1038
0f133090
JH		 1039 aconnect@702c0000 {
1040 compatible = "nvidia,tegra210-aconnect";
1041 clocks = <&tegra_car TEGRA210_CLK_APE>,
1042 <&tegra_car TEGRA210_CLK_APB2APE>;
1043 clock-names = "ape", "apb2ape";
1044 power-domains = <&pd_audio>;
1045 #address-cells = <1>;
1046 #size-cells = <1>;
1047 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
1048 status = "disabled";
bcdbde43 1049
19e61213
JH		 1050 adma: dma@702e2000 {
1051 compatible = "nvidia,tegra210-adma";
1052 reg = <0x702e2000 0x2000>;
1053 interrupt-parent = <&agic>;
1054 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1055 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1056 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
1057 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
1058 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
1059 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1060 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
1061 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
1062 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
1063 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
1064 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
1065 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
1066 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
1067 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
1068 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
1069 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1070 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1071 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1072 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1073 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1074 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1075 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1076 #dma-cells = <1>;
1077 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1078 clock-names = "d_audio";
1079 status = "disabled";
1080 };
1081
bcdbde43
JH		 1082 agic: agic@702f9000 {
1083 compatible = "nvidia,tegra210-agic";
1084 #interrupt-cells = <3>;
1085 interrupt-controller;
1086 reg = <0x702f9000 0x2000>,
1087 <0x702fa000 0x2000>;
1088 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1089 clocks = <&tegra_car TEGRA210_CLK_APE>;
1090 clock-names = "clk";
1091 status = "disabled";
1092 };
0f133090
JH		 1093 };
1094
be70771d 1095 spi@70410000 {
742af7e7
TR		 1096 compatible = "nvidia,tegra210-qspi";
1097 reg = <0x0 0x70410000 0x0 0x1000>;
1098 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1099 #address-cells = <1>;
1100 #size-cells = <0>;
1101 clocks = <&tegra_car TEGRA210_CLK_QSPI>;
1102 clock-names = "qspi";
1103 resets = <&tegra_car 211>;
1104 reset-names = "qspi";
1105 dmas = <&apbdma 5>, <&apbdma 5>;
1106 dma-names = "rx", "tx";
1107 status = "disabled";
1108 };
1109
be70771d 1110 usb@7d000000 {
742af7e7
TR		 1111 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1112 reg = <0x0 0x7d000000 0x0 0x4000>;
1113 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1114 phy_type = "utmi";
1115 clocks = <&tegra_car TEGRA210_CLK_USBD>;
1116 clock-names = "usb";
1117 resets = <&tegra_car 22>;
1118 reset-names = "usb";
1119 nvidia,phy = <&phy1>;
1120 status = "disabled";
1121 };
1122
be70771d 1123 phy1: usb-phy@7d000000 {
742af7e7
TR		 1124 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1125 reg = <0x0 0x7d000000 0x0 0x4000>,
1126 <0x0 0x7d000000 0x0 0x4000>;
1127 phy_type = "utmi";
1128 clocks = <&tegra_car TEGRA210_CLK_USBD>,
1129 <&tegra_car TEGRA210_CLK_PLL_U>,
1130 <&tegra_car TEGRA210_CLK_USBD>;
1131 clock-names = "reg", "pll_u", "utmi-pads";
1132 resets = <&tegra_car 22>, <&tegra_car 22>;
1133 reset-names = "usb", "utmi-pads";
1134 nvidia,hssync-start-delay = <0>;
1135 nvidia,idle-wait-delay = <17>;
1136 nvidia,elastic-limit = <16>;
1137 nvidia,term-range-adj = <6>;
1138 nvidia,xcvr-setup = <9>;
1139 nvidia,xcvr-lsfslew = <0>;
1140 nvidia,xcvr-lsrslew = <3>;
1141 nvidia,hssquelch-level = <2>;
1142 nvidia,hsdiscon-level = <5>;
1143 nvidia,xcvr-hsslew = <12>;
1144 nvidia,has-utmi-pad-registers;
1145 status = "disabled";
1146 };
1147
be70771d 1148 usb@7d004000 {
742af7e7
TR		 1149 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1150 reg = <0x0 0x7d004000 0x0 0x4000>;
1151 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1152 phy_type = "utmi";
1153 clocks = <&tegra_car TEGRA210_CLK_USB2>;
1154 clock-names = "usb";
1155 resets = <&tegra_car 58>;
1156 reset-names = "usb";
1157 nvidia,phy = <&phy2>;
1158 status = "disabled";
1159 };
1160
be70771d 1161 phy2: usb-phy@7d004000 {
742af7e7
TR		 1162 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1163 reg = <0x0 0x7d004000 0x0 0x4000>,
1164 <0x0 0x7d000000 0x0 0x4000>;
1165 phy_type = "utmi";
1166 clocks = <&tegra_car TEGRA210_CLK_USB2>,
1167 <&tegra_car TEGRA210_CLK_PLL_U>,
1168 <&tegra_car TEGRA210_CLK_USBD>;
1169 clock-names = "reg", "pll_u", "utmi-pads";
1170 resets = <&tegra_car 58>, <&tegra_car 22>;
1171 reset-names = "usb", "utmi-pads";
1172 nvidia,hssync-start-delay = <0>;
1173 nvidia,idle-wait-delay = <17>;
1174 nvidia,elastic-limit = <16>;
1175 nvidia,term-range-adj = <6>;
1176 nvidia,xcvr-setup = <9>;
1177 nvidia,xcvr-lsfslew = <0>;
1178 nvidia,xcvr-lsrslew = <3>;
1179 nvidia,hssquelch-level = <2>;
1180 nvidia,hsdiscon-level = <5>;
1181 nvidia,xcvr-hsslew = <12>;
1182 status = "disabled";
1183 };
1184
1185 cpus {
1186 #address-cells = <1>;
1187 #size-cells = <0>;
1188
1189 cpu@0 {
1190 device_type = "cpu";
1191 compatible = "arm,cortex-a57";
1192 reg = <0>;
1193 };
1194
1195 cpu@1 {
1196 device_type = "cpu";
1197 compatible = "arm,cortex-a57";
1198 reg = <1>;
1199 };
1200
1201 cpu@2 {
1202 device_type = "cpu";
1203 compatible = "arm,cortex-a57";
1204 reg = <2>;
1205 };
1206
1207 cpu@3 {
1208 device_type = "cpu";
1209 compatible = "arm,cortex-a57";
1210 reg = <3>;
1211 };
1212 };
1213
1214 timer {
1215 compatible = "arm,armv8-timer";
1216 interrupts = <GIC_PPI 13
1217 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1218 <GIC_PPI 14
1219 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1220 <GIC_PPI 11
1221 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1222 <GIC_PPI 10
1223 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1224 interrupt-parent = <&gic>;
1225 };
e2bed1eb
WN		 1226
1227 soctherm: thermal-sensor@700e2000 {
1228 compatible = "nvidia,tegra210-soctherm";
cbd0f000
WN		 1229 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
1230 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
1231 reg-names = "soctherm-reg", "car-reg";
e2bed1eb
WN		 1232 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1233 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
1234 <&tegra_car TEGRA210_CLK_SOC_THERM>;
1235 clock-names = "tsensor", "soctherm";
1236 resets = <&tegra_car 78>;
1237 reset-names = "soctherm";
1238 #thermal-sensor-cells = <1>;
cbd0f000
WN		 1239
1240 throttle-cfgs {
1241 throttle_heavy: heavy {
1242 nvidia,priority = <100>;
1243 nvidia,cpu-throt-percent = <85>;
1244
1245 #cooling-cells = <2>;
1246 };
1247 };
e2bed1eb
WN		 1248 };
1249
1250 thermal-zones {
1251 cpu {
1252 polling-delay-passive = <1000>;
1253 polling-delay = <0>;
1254
1255 thermal-sensors =
1256 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
5e03f663
WN		 1257
1258 trips {
1259 cpu-shutdown-trip {
1260 temperature = <102500>;
1261 hysteresis = <0>;
1262 type = "critical";
1263 };
cbd0f000
WN		 1264
1265 cpu_throttle_trip: throttle-trip {
1266 temperature = <98500>;
1267 hysteresis = <1000>;
1268 type = "hot";
1269 };
5e03f663
WN		 1270 };
1271
1272 cooling-maps {
cbd0f000
WN		 1273 map0 {
1274 trip = <&cpu_throttle_trip>;
1275 cooling-device = <&throttle_heavy 1 1>;
1276 };
5e03f663 1277 };
e2bed1eb
WN		 1278 };
1279 mem {
1280 polling-delay-passive = <0>;
1281 polling-delay = <0>;
1282
1283 thermal-sensors =
1284 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
5e03f663
WN		 1285
1286 trips {
1287 mem-shutdown-trip {
1288 temperature = <103000>;
1289 hysteresis = <0>;
1290 type = "critical";
1291 };
1292 };
1293
1294 cooling-maps {
1295 /*
1296 * There are currently no cooling maps,
1297 * because there are no cooling devices.
1298 */
1299 };
e2bed1eb
WN		 1300 };
1301 gpu {
1302 polling-delay-passive = <1000>;
1303 polling-delay = <0>;
1304
1305 thermal-sensors =
1306 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
5e03f663
WN		 1307
1308 trips {
1309 gpu-shutdown-trip {
1310 temperature = <103000>;
1311 hysteresis = <0>;
1312 type = "critical";
1313 };
cbd0f000
WN		 1314
1315 gpu_throttle_trip: throttle-trip {
1316 temperature = <100000>;
1317 hysteresis = <1000>;
1318 type = "hot";
1319 };
5e03f663
WN		 1320 };
1321
1322 cooling-maps {
cbd0f000
WN		 1323 map0 {
1324 trip = <&gpu_throttle_trip>;
1325 cooling-device = <&throttle_heavy 1 1>;
1326 };
5e03f663 1327 };
e2bed1eb
WN		 1328 };
1329 pllx {
1330 polling-delay-passive = <0>;
1331 polling-delay = <0>;
1332
1333 thermal-sensors =
1334 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
5e03f663
WN		 1335
1336 trips {
1337 pllx-shutdown-trip {
1338 temperature = <103000>;
1339 hysteresis = <0>;
1340 type = "critical";
1341 };
1342 };
1343
1344 cooling-maps {
1345 /*
1346 * There are currently no cooling maps,
1347 * because there are no cooling devices.
1348 */
1349 };
e2bed1eb
WN		 1350 };
1351 };
742af7e7 1352};
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