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97fb5e8d | 1 | // SPDX-License-Identifier: GPL-2.0-only |
feeaf56a | 2 | /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. |
feeaf56a BK |
3 | */ |
4 | ||
5 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
6 | #include <dt-bindings/clock/qcom,gcc-msm8994.h> | |
7 | ||
8 | / { | |
9 | model = "Qualcomm Technologies, Inc. MSM 8994"; | |
10 | compatible = "qcom,msm8994"; | |
11 | // msm-id and pmic-id are required by bootloader for | |
12 | // proper selection of dt blob | |
13 | qcom,msm-id = <207 0x20000>; | |
14 | qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>; | |
15 | interrupt-parent = <&intc>; | |
16 | ||
17 | #address-cells = <2>; | |
18 | #size-cells = <2>; | |
19 | ||
20 | chosen { }; | |
21 | ||
22 | cpus { | |
23 | #address-cells = <1>; | |
24 | #size-cells = <0>; | |
25 | cpu-map { | |
26 | cluster0 { | |
27 | core0 { | |
28 | cpu = <&CPU0>; | |
29 | }; | |
30 | }; | |
31 | }; | |
32 | ||
33 | CPU0: cpu@0 { | |
34 | device_type = "cpu"; | |
31af04cd | 35 | compatible = "arm,cortex-a53"; |
feeaf56a BK |
36 | reg = <0x0>; |
37 | next-level-cache = <&L2_0>; | |
38 | L2_0: l2-cache { | |
39 | compatible = "cache"; | |
40 | cache-level = <2>; | |
41 | }; | |
42 | }; | |
43 | }; | |
44 | ||
45 | timer { | |
46 | compatible = "arm,armv8-timer"; | |
47 | interrupts = <1 2 0xff08>, | |
48 | <1 3 0xff08>, | |
49 | <1 4 0xff08>, | |
50 | <1 1 0xff08>; | |
51 | }; | |
52 | ||
53 | soc: soc { | |
54 | ||
55 | #address-cells = <1>; | |
56 | #size-cells = <1>; | |
57 | ranges = <0 0 0 0xffffffff>; | |
58 | compatible = "simple-bus"; | |
59 | ||
60 | intc: interrupt-controller@f9000000 { | |
61 | compatible = "qcom,msm-qgic2"; | |
62 | interrupt-controller; | |
63 | #interrupt-cells = <3>; | |
64 | reg = <0xf9000000 0x1000>, | |
65 | <0xf9002000 0x1000>; | |
66 | }; | |
67 | ||
68 | timer@f9020000 { | |
69 | #address-cells = <1>; | |
70 | #size-cells = <1>; | |
71 | ranges; | |
72 | compatible = "arm,armv7-timer-mem"; | |
73 | reg = <0xf9020000 0x1000>; | |
74 | ||
75 | frame@f9021000 { | |
76 | frame-number = <0>; | |
77 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, | |
78 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
79 | reg = <0xf9021000 0x1000>, | |
80 | <0xf9022000 0x1000>; | |
81 | }; | |
82 | ||
83 | frame@f9023000 { | |
84 | frame-number = <1>; | |
85 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
86 | reg = <0xf9023000 0x1000>; | |
87 | status = "disabled"; | |
88 | }; | |
89 | ||
90 | frame@f9024000 { | |
91 | frame-number = <2>; | |
92 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
93 | reg = <0xf9024000 0x1000>; | |
94 | status = "disabled"; | |
95 | }; | |
96 | ||
97 | frame@f9025000 { | |
98 | frame-number = <3>; | |
99 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | |
100 | reg = <0xf9025000 0x1000>; | |
101 | status = "disabled"; | |
102 | }; | |
103 | ||
104 | frame@f9026000 { | |
105 | frame-number = <4>; | |
106 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
107 | reg = <0xf9026000 0x1000>; | |
108 | status = "disabled"; | |
109 | }; | |
110 | ||
111 | frame@f9027000 { | |
112 | frame-number = <5>; | |
113 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; | |
114 | reg = <0xf9027000 0x1000>; | |
115 | status = "disabled"; | |
116 | }; | |
117 | ||
118 | frame@f9028000 { | |
119 | frame-number = <6>; | |
120 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
121 | reg = <0xf9028000 0x1000>; | |
122 | status = "disabled"; | |
123 | }; | |
124 | }; | |
125 | ||
126 | restart@fc4ab000 { | |
127 | compatible = "qcom,pshold"; | |
128 | reg = <0xfc4ab000 0x4>; | |
129 | }; | |
130 | ||
131 | msmgpio: pinctrl@fd510000 { | |
132 | compatible = "qcom,msm8994-pinctrl"; | |
133 | reg = <0xfd510000 0x4000>; | |
134 | interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; | |
135 | gpio-controller; | |
136 | #gpio-cells = <2>; | |
137 | interrupt-controller; | |
138 | #interrupt-cells = <2>; | |
139 | }; | |
140 | ||
141 | blsp1_uart2: serial@f991e000 { | |
142 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
143 | reg = <0xf991e000 0x1000>; | |
144 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; | |
145 | status = "disabled"; | |
146 | clock-names = "core", "iface"; | |
147 | clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>, | |
148 | <&clock_gcc GCC_BLSP1_AHB_CLK>; | |
149 | }; | |
150 | ||
151 | tcsr_mutex_regs: syscon@fd484000 { | |
152 | compatible = "syscon"; | |
153 | reg = <0xfd484000 0x2000>; | |
154 | }; | |
155 | ||
156 | clock_gcc: clock-controller@fc400000 { | |
157 | compatible = "qcom,gcc-msm8994"; | |
158 | #clock-cells = <1>; | |
159 | #reset-cells = <1>; | |
160 | #power-domain-cells = <1>; | |
161 | reg = <0xfc400000 0x2000>; | |
162 | }; | |
163 | }; | |
164 | ||
165 | memory { | |
166 | device_type = "memory"; | |
167 | // We expect the bootloader to fill in the reg | |
168 | reg = <0 0 0 0>; | |
169 | }; | |
170 | ||
171 | xo_board: xo_board { | |
172 | compatible = "fixed-clock"; | |
173 | #clock-cells = <0>; | |
174 | clock-frequency = <19200000>; | |
175 | }; | |
176 | ||
177 | sleep_clk: sleep_clk { | |
178 | compatible = "fixed-clock"; | |
179 | #clock-cells = <0>; | |
180 | clock-frequency = <32768>; | |
181 | }; | |
182 | ||
183 | reserved-memory { | |
184 | #address-cells = <2>; | |
185 | #size-cells = <2>; | |
186 | ranges; | |
187 | ||
188 | smem_mem: smem_region@6a00000 { | |
189 | reg = <0x0 0x6a00000 0x0 0x200000>; | |
190 | no-map; | |
191 | }; | |
192 | }; | |
193 | ||
194 | tcsr_mutex: hwlock { | |
195 | compatible = "qcom,tcsr-mutex"; | |
196 | syscon = <&tcsr_mutex_regs 0 0x80>; | |
197 | #hwlock-cells = <1>; | |
198 | }; | |
199 | ||
200 | qcom,smem@6a00000 { | |
201 | compatible = "qcom,smem"; | |
202 | memory-region = <&smem_mem>; | |
203 | hwlocks = <&tcsr_mutex 3>; | |
204 | }; | |
205 | }; | |
206 | ||
207 | ||
208 | #include "msm8994-pins.dtsi" |