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6d4cf750 RN |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * SDM845 SoC device tree source | |
4 | * | |
5 | * Copyright (c) 2018, The Linux Foundation. All rights reserved. | |
6 | */ | |
7 | ||
40019e84 | 8 | #include <dt-bindings/clock/qcom,dispcc-sdm845.h> |
897cf34e | 9 | #include <dt-bindings/clock/qcom,gcc-sdm845.h> |
9aa4a27e | 10 | #include <dt-bindings/clock/qcom,gpucc-sdm845.h> |
ea0edd7e | 11 | #include <dt-bindings/clock/qcom,lpass-sdm845.h> |
717f2013 | 12 | #include <dt-bindings/clock/qcom,rpmh.h> |
05556681 | 13 | #include <dt-bindings/clock/qcom,videocc-sdm845.h> |
71f1fdd9 | 14 | #include <dt-bindings/interconnect/qcom,sdm845.h> |
6d4cf750 | 15 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
ca4db2b5 | 16 | #include <dt-bindings/phy/phy-qcom-qusb2.h> |
596a4343 | 17 | #include <dt-bindings/power/qcom-rpmpd.h> |
ead5eea3 | 18 | #include <dt-bindings/reset/qcom,sdm845-aoss.h> |
13393da0 | 19 | #include <dt-bindings/reset/qcom,sdm845-pdc.h> |
c83545d9 | 20 | #include <dt-bindings/soc/qcom,rpmh-rsc.h> |
c47fc198 AK |
21 | #include <dt-bindings/clock/qcom,gcc-sdm845.h> |
22 | #include <dt-bindings/thermal/thermal.h> | |
6d4cf750 RN |
23 | |
24 | / { | |
25 | interrupt-parent = <&intc>; | |
26 | ||
27 | #address-cells = <2>; | |
28 | #size-cells = <2>; | |
29 | ||
897cf34e DA |
30 | aliases { |
31 | i2c0 = &i2c0; | |
32 | i2c1 = &i2c1; | |
33 | i2c2 = &i2c2; | |
34 | i2c3 = &i2c3; | |
35 | i2c4 = &i2c4; | |
36 | i2c5 = &i2c5; | |
37 | i2c6 = &i2c6; | |
38 | i2c7 = &i2c7; | |
39 | i2c8 = &i2c8; | |
40 | i2c9 = &i2c9; | |
41 | i2c10 = &i2c10; | |
42 | i2c11 = &i2c11; | |
43 | i2c12 = &i2c12; | |
44 | i2c13 = &i2c13; | |
45 | i2c14 = &i2c14; | |
46 | i2c15 = &i2c15; | |
47 | spi0 = &spi0; | |
48 | spi1 = &spi1; | |
49 | spi2 = &spi2; | |
50 | spi3 = &spi3; | |
51 | spi4 = &spi4; | |
52 | spi5 = &spi5; | |
53 | spi6 = &spi6; | |
54 | spi7 = &spi7; | |
55 | spi8 = &spi8; | |
56 | spi9 = &spi9; | |
57 | spi10 = &spi10; | |
58 | spi11 = &spi11; | |
59 | spi12 = &spi12; | |
60 | spi13 = &spi13; | |
61 | spi14 = &spi14; | |
62 | spi15 = &spi15; | |
63 | }; | |
64 | ||
6d4cf750 RN |
65 | chosen { }; |
66 | ||
67 | memory@80000000 { | |
68 | device_type = "memory"; | |
69 | /* We expect the bootloader to fill in the size */ | |
70 | reg = <0 0x80000000 0 0>; | |
71 | }; | |
72 | ||
71c8428e S |
73 | reserved-memory { |
74 | #address-cells = <2>; | |
75 | #size-cells = <2>; | |
76 | ranges; | |
77 | ||
a23b5378 BA |
78 | hyp_mem: memory@85700000 { |
79 | reg = <0 0x85700000 0 0x600000>; | |
80 | no-map; | |
81 | }; | |
82 | ||
83 | xbl_mem: memory@85e00000 { | |
84 | reg = <0 0x85e00000 0 0x100000>; | |
85 | no-map; | |
86 | }; | |
87 | ||
88 | aop_mem: memory@85fc0000 { | |
71c8428e S |
89 | reg = <0 0x85fc0000 0 0x20000>; |
90 | no-map; | |
91 | }; | |
92 | ||
a23b5378 | 93 | aop_cmd_db_mem: memory@85fe0000 { |
2da52398 | 94 | compatible = "qcom,cmd-db"; |
a23b5378 | 95 | reg = <0x0 0x85fe0000 0 0x20000>; |
2da52398 DA |
96 | no-map; |
97 | }; | |
98 | ||
71c8428e | 99 | smem_mem: memory@86000000 { |
a23b5378 | 100 | reg = <0x0 0x86000000 0 0x200000>; |
71c8428e S |
101 | no-map; |
102 | }; | |
103 | ||
a23b5378 | 104 | tz_mem: memory@86200000 { |
71c8428e S |
105 | reg = <0 0x86200000 0 0x2d00000>; |
106 | no-map; | |
107 | }; | |
022bccb8 | 108 | |
bdecbe6b BA |
109 | rmtfs_mem: memory@88f00000 { |
110 | compatible = "qcom,rmtfs-mem"; | |
111 | reg = <0 0x88f00000 0 0x200000>; | |
112 | no-map; | |
113 | ||
114 | qcom,client-id = <1>; | |
115 | qcom,vmid = <15>; | |
116 | }; | |
117 | ||
a23b5378 BA |
118 | qseecom_mem: memory@8ab00000 { |
119 | reg = <0 0x8ab00000 0 0x1400000>; | |
120 | no-map; | |
121 | }; | |
122 | ||
123 | camera_mem: memory@8bf00000 { | |
124 | reg = <0 0x8bf00000 0 0x500000>; | |
125 | no-map; | |
126 | }; | |
127 | ||
128 | ipa_fw_mem: memory@8c400000 { | |
129 | reg = <0 0x8c400000 0 0x10000>; | |
130 | no-map; | |
131 | }; | |
132 | ||
133 | ipa_gsi_mem: memory@8c410000 { | |
134 | reg = <0 0x8c410000 0 0x5000>; | |
135 | no-map; | |
136 | }; | |
137 | ||
138 | gpu_mem: memory@8c415000 { | |
139 | reg = <0 0x8c415000 0 0x2000>; | |
140 | no-map; | |
141 | }; | |
142 | ||
143 | adsp_mem: memory@8c500000 { | |
144 | reg = <0 0x8c500000 0 0x1a00000>; | |
145 | no-map; | |
146 | }; | |
147 | ||
148 | wlan_msa_mem: memory@8df00000 { | |
149 | reg = <0 0x8df00000 0 0x100000>; | |
022bccb8 GS |
150 | no-map; |
151 | }; | |
8ed6d484 SS |
152 | |
153 | mpss_region: memory@8e000000 { | |
154 | reg = <0 0x8e000000 0 0x7800000>; | |
155 | no-map; | |
156 | }; | |
157 | ||
a23b5378 BA |
158 | venus_mem: memory@95800000 { |
159 | reg = <0 0x95800000 0 0x500000>; | |
160 | no-map; | |
161 | }; | |
162 | ||
163 | cdsp_mem: memory@95d00000 { | |
164 | reg = <0 0x95d00000 0 0x800000>; | |
165 | no-map; | |
166 | }; | |
167 | ||
8ed6d484 SS |
168 | mba_region: memory@96500000 { |
169 | reg = <0 0x96500000 0 0x200000>; | |
170 | no-map; | |
171 | }; | |
a23b5378 BA |
172 | |
173 | slpi_mem: memory@96700000 { | |
174 | reg = <0 0x96700000 0 0x1400000>; | |
175 | no-map; | |
176 | }; | |
177 | ||
178 | spss_mem: memory@97b00000 { | |
179 | reg = <0 0x97b00000 0 0x100000>; | |
180 | no-map; | |
181 | }; | |
71c8428e S |
182 | }; |
183 | ||
6d4cf750 RN |
184 | cpus { |
185 | #address-cells = <2>; | |
186 | #size-cells = <0>; | |
187 | ||
188 | CPU0: cpu@0 { | |
189 | device_type = "cpu"; | |
190 | compatible = "qcom,kryo385"; | |
191 | reg = <0x0 0x0>; | |
192 | enable-method = "psci"; | |
9bbd0836 R |
193 | cpu-idle-states = <&LITTLE_CPU_SLEEP_0 |
194 | &LITTLE_CPU_SLEEP_1 | |
195 | &CLUSTER_SLEEP_0>; | |
b6bc6423 | 196 | capacity-dmips-mhz = <607>; |
c604b82a | 197 | qcom,freq-domain = <&cpufreq_hw 0>; |
c47fc198 | 198 | #cooling-cells = <2>; |
6d4cf750 RN |
199 | next-level-cache = <&L2_0>; |
200 | L2_0: l2-cache { | |
201 | compatible = "cache"; | |
202 | next-level-cache = <&L3_0>; | |
203 | L3_0: l3-cache { | |
204 | compatible = "cache"; | |
205 | }; | |
206 | }; | |
207 | }; | |
208 | ||
209 | CPU1: cpu@100 { | |
210 | device_type = "cpu"; | |
211 | compatible = "qcom,kryo385"; | |
212 | reg = <0x0 0x100>; | |
213 | enable-method = "psci"; | |
9bbd0836 R |
214 | cpu-idle-states = <&LITTLE_CPU_SLEEP_0 |
215 | &LITTLE_CPU_SLEEP_1 | |
216 | &CLUSTER_SLEEP_0>; | |
b6bc6423 | 217 | capacity-dmips-mhz = <607>; |
c604b82a | 218 | qcom,freq-domain = <&cpufreq_hw 0>; |
c47fc198 | 219 | #cooling-cells = <2>; |
6d4cf750 RN |
220 | next-level-cache = <&L2_100>; |
221 | L2_100: l2-cache { | |
222 | compatible = "cache"; | |
223 | next-level-cache = <&L3_0>; | |
224 | }; | |
225 | }; | |
226 | ||
227 | CPU2: cpu@200 { | |
228 | device_type = "cpu"; | |
229 | compatible = "qcom,kryo385"; | |
230 | reg = <0x0 0x200>; | |
231 | enable-method = "psci"; | |
9bbd0836 R |
232 | cpu-idle-states = <&LITTLE_CPU_SLEEP_0 |
233 | &LITTLE_CPU_SLEEP_1 | |
234 | &CLUSTER_SLEEP_0>; | |
b6bc6423 | 235 | capacity-dmips-mhz = <607>; |
c604b82a | 236 | qcom,freq-domain = <&cpufreq_hw 0>; |
c47fc198 | 237 | #cooling-cells = <2>; |
6d4cf750 RN |
238 | next-level-cache = <&L2_200>; |
239 | L2_200: l2-cache { | |
240 | compatible = "cache"; | |
241 | next-level-cache = <&L3_0>; | |
242 | }; | |
243 | }; | |
244 | ||
245 | CPU3: cpu@300 { | |
246 | device_type = "cpu"; | |
247 | compatible = "qcom,kryo385"; | |
248 | reg = <0x0 0x300>; | |
249 | enable-method = "psci"; | |
9bbd0836 R |
250 | cpu-idle-states = <&LITTLE_CPU_SLEEP_0 |
251 | &LITTLE_CPU_SLEEP_1 | |
252 | &CLUSTER_SLEEP_0>; | |
b6bc6423 | 253 | capacity-dmips-mhz = <607>; |
c604b82a | 254 | qcom,freq-domain = <&cpufreq_hw 0>; |
c47fc198 | 255 | #cooling-cells = <2>; |
6d4cf750 RN |
256 | next-level-cache = <&L2_300>; |
257 | L2_300: l2-cache { | |
258 | compatible = "cache"; | |
259 | next-level-cache = <&L3_0>; | |
260 | }; | |
261 | }; | |
262 | ||
263 | CPU4: cpu@400 { | |
264 | device_type = "cpu"; | |
265 | compatible = "qcom,kryo385"; | |
266 | reg = <0x0 0x400>; | |
267 | enable-method = "psci"; | |
b6bc6423 | 268 | capacity-dmips-mhz = <1024>; |
9bbd0836 R |
269 | cpu-idle-states = <&BIG_CPU_SLEEP_0 |
270 | &BIG_CPU_SLEEP_1 | |
271 | &CLUSTER_SLEEP_0>; | |
c604b82a | 272 | qcom,freq-domain = <&cpufreq_hw 1>; |
c47fc198 | 273 | #cooling-cells = <2>; |
6d4cf750 RN |
274 | next-level-cache = <&L2_400>; |
275 | L2_400: l2-cache { | |
276 | compatible = "cache"; | |
277 | next-level-cache = <&L3_0>; | |
278 | }; | |
279 | }; | |
280 | ||
281 | CPU5: cpu@500 { | |
282 | device_type = "cpu"; | |
283 | compatible = "qcom,kryo385"; | |
284 | reg = <0x0 0x500>; | |
285 | enable-method = "psci"; | |
b6bc6423 | 286 | capacity-dmips-mhz = <1024>; |
9bbd0836 R |
287 | cpu-idle-states = <&BIG_CPU_SLEEP_0 |
288 | &BIG_CPU_SLEEP_1 | |
289 | &CLUSTER_SLEEP_0>; | |
c604b82a | 290 | qcom,freq-domain = <&cpufreq_hw 1>; |
c47fc198 | 291 | #cooling-cells = <2>; |
6d4cf750 RN |
292 | next-level-cache = <&L2_500>; |
293 | L2_500: l2-cache { | |
294 | compatible = "cache"; | |
295 | next-level-cache = <&L3_0>; | |
296 | }; | |
297 | }; | |
298 | ||
299 | CPU6: cpu@600 { | |
300 | device_type = "cpu"; | |
301 | compatible = "qcom,kryo385"; | |
302 | reg = <0x0 0x600>; | |
303 | enable-method = "psci"; | |
b6bc6423 | 304 | capacity-dmips-mhz = <1024>; |
9bbd0836 R |
305 | cpu-idle-states = <&BIG_CPU_SLEEP_0 |
306 | &BIG_CPU_SLEEP_1 | |
307 | &CLUSTER_SLEEP_0>; | |
c604b82a | 308 | qcom,freq-domain = <&cpufreq_hw 1>; |
c47fc198 | 309 | #cooling-cells = <2>; |
6d4cf750 RN |
310 | next-level-cache = <&L2_600>; |
311 | L2_600: l2-cache { | |
312 | compatible = "cache"; | |
313 | next-level-cache = <&L3_0>; | |
314 | }; | |
315 | }; | |
316 | ||
317 | CPU7: cpu@700 { | |
318 | device_type = "cpu"; | |
319 | compatible = "qcom,kryo385"; | |
320 | reg = <0x0 0x700>; | |
321 | enable-method = "psci"; | |
b6bc6423 | 322 | capacity-dmips-mhz = <1024>; |
9bbd0836 R |
323 | cpu-idle-states = <&BIG_CPU_SLEEP_0 |
324 | &BIG_CPU_SLEEP_1 | |
325 | &CLUSTER_SLEEP_0>; | |
c604b82a | 326 | qcom,freq-domain = <&cpufreq_hw 1>; |
c47fc198 | 327 | #cooling-cells = <2>; |
6d4cf750 RN |
328 | next-level-cache = <&L2_700>; |
329 | L2_700: l2-cache { | |
330 | compatible = "cache"; | |
331 | next-level-cache = <&L3_0>; | |
332 | }; | |
333 | }; | |
7b5ee83d MK |
334 | |
335 | cpu-map { | |
336 | cluster0 { | |
337 | core0 { | |
338 | cpu = <&CPU0>; | |
339 | }; | |
340 | ||
341 | core1 { | |
342 | cpu = <&CPU1>; | |
343 | }; | |
344 | ||
345 | core2 { | |
346 | cpu = <&CPU2>; | |
347 | }; | |
348 | ||
349 | core3 { | |
350 | cpu = <&CPU3>; | |
351 | }; | |
7b5ee83d | 352 | |
14d27be1 | 353 | core4 { |
7b5ee83d MK |
354 | cpu = <&CPU4>; |
355 | }; | |
356 | ||
14d27be1 | 357 | core5 { |
7b5ee83d MK |
358 | cpu = <&CPU5>; |
359 | }; | |
360 | ||
14d27be1 | 361 | core6 { |
7b5ee83d MK |
362 | cpu = <&CPU6>; |
363 | }; | |
364 | ||
14d27be1 | 365 | core7 { |
7b5ee83d MK |
366 | cpu = <&CPU7>; |
367 | }; | |
368 | }; | |
369 | }; | |
9bbd0836 R |
370 | |
371 | idle-states { | |
372 | entry-method = "psci"; | |
373 | ||
374 | LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { | |
375 | compatible = "arm,idle-state"; | |
376 | idle-state-name = "little-power-down"; | |
377 | arm,psci-suspend-param = <0x40000003>; | |
378 | entry-latency-us = <350>; | |
379 | exit-latency-us = <461>; | |
380 | min-residency-us = <1890>; | |
381 | local-timer-stop; | |
382 | }; | |
383 | ||
384 | LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { | |
385 | compatible = "arm,idle-state"; | |
386 | idle-state-name = "little-rail-power-down"; | |
387 | arm,psci-suspend-param = <0x40000004>; | |
388 | entry-latency-us = <360>; | |
389 | exit-latency-us = <531>; | |
390 | min-residency-us = <3934>; | |
391 | local-timer-stop; | |
392 | }; | |
393 | ||
394 | BIG_CPU_SLEEP_0: cpu-sleep-1-0 { | |
395 | compatible = "arm,idle-state"; | |
396 | idle-state-name = "big-power-down"; | |
397 | arm,psci-suspend-param = <0x40000003>; | |
398 | entry-latency-us = <264>; | |
399 | exit-latency-us = <621>; | |
400 | min-residency-us = <952>; | |
401 | local-timer-stop; | |
402 | }; | |
403 | ||
404 | BIG_CPU_SLEEP_1: cpu-sleep-1-1 { | |
405 | compatible = "arm,idle-state"; | |
406 | idle-state-name = "big-rail-power-down"; | |
407 | arm,psci-suspend-param = <0x40000004>; | |
408 | entry-latency-us = <702>; | |
409 | exit-latency-us = <1061>; | |
410 | min-residency-us = <4488>; | |
411 | local-timer-stop; | |
412 | }; | |
413 | ||
414 | CLUSTER_SLEEP_0: cluster-sleep-0 { | |
415 | compatible = "arm,idle-state"; | |
416 | idle-state-name = "cluster-power-down"; | |
417 | arm,psci-suspend-param = <0x400000F4>; | |
418 | entry-latency-us = <3263>; | |
419 | exit-latency-us = <6562>; | |
420 | min-residency-us = <9987>; | |
421 | local-timer-stop; | |
422 | }; | |
423 | }; | |
6d4cf750 RN |
424 | }; |
425 | ||
000c4662 SB |
426 | pmu { |
427 | compatible = "arm,armv8-pmuv3"; | |
428 | interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
429 | }; | |
430 | ||
6d4cf750 RN |
431 | timer { |
432 | compatible = "arm,armv8-timer"; | |
433 | interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, | |
434 | <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, | |
435 | <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, | |
436 | <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; | |
437 | }; | |
438 | ||
439 | clocks { | |
440 | xo_board: xo-board { | |
441 | compatible = "fixed-clock"; | |
442 | #clock-cells = <0>; | |
5ea3939c DA |
443 | clock-frequency = <38400000>; |
444 | clock-output-names = "xo_board"; | |
6d4cf750 RN |
445 | }; |
446 | ||
447 | sleep_clk: sleep-clk { | |
448 | compatible = "fixed-clock"; | |
449 | #clock-cells = <0>; | |
450 | clock-frequency = <32764>; | |
451 | }; | |
452 | }; | |
453 | ||
77bb7f94 SS |
454 | firmware { |
455 | scm { | |
456 | compatible = "qcom,scm-sdm845", "qcom,scm"; | |
457 | }; | |
458 | }; | |
459 | ||
6ef7c11b BA |
460 | adsp_pas: remoteproc-adsp { |
461 | compatible = "qcom,sdm845-adsp-pas"; | |
462 | ||
463 | interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, | |
464 | <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, | |
465 | <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, | |
466 | <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, | |
467 | <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; | |
468 | interrupt-names = "wdog", "fatal", "ready", | |
469 | "handover", "stop-ack"; | |
470 | ||
471 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
472 | clock-names = "xo"; | |
473 | ||
474 | memory-region = <&adsp_mem>; | |
475 | ||
476 | qcom,smem-states = <&adsp_smp2p_out 0>; | |
477 | qcom,smem-state-names = "stop"; | |
478 | ||
479 | status = "disabled"; | |
480 | ||
481 | glink-edge { | |
482 | interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; | |
483 | label = "lpass"; | |
484 | qcom,remote-pid = <2>; | |
485 | mboxes = <&apss_shared 8>; | |
486 | }; | |
487 | }; | |
488 | ||
489 | cdsp_pas: remoteproc-cdsp { | |
490 | compatible = "qcom,sdm845-cdsp-pas"; | |
491 | ||
492 | interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, | |
493 | <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, | |
494 | <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, | |
495 | <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, | |
496 | <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; | |
497 | interrupt-names = "wdog", "fatal", "ready", | |
498 | "handover", "stop-ack"; | |
499 | ||
500 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
501 | clock-names = "xo"; | |
502 | ||
503 | memory-region = <&cdsp_mem>; | |
504 | ||
505 | qcom,smem-states = <&cdsp_smp2p_out 0>; | |
506 | qcom,smem-state-names = "stop"; | |
507 | ||
508 | status = "disabled"; | |
509 | ||
510 | glink-edge { | |
511 | interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; | |
512 | label = "turing"; | |
513 | qcom,remote-pid = <5>; | |
514 | mboxes = <&apss_shared 4>; | |
515 | }; | |
516 | }; | |
517 | ||
71c8428e S |
518 | tcsr_mutex: hwlock { |
519 | compatible = "qcom,tcsr-mutex"; | |
520 | syscon = <&tcsr_mutex_regs 0 0x1000>; | |
521 | #hwlock-cells = <1>; | |
522 | }; | |
523 | ||
524 | smem { | |
525 | compatible = "qcom,smem"; | |
526 | memory-region = <&smem_mem>; | |
527 | hwlocks = <&tcsr_mutex 3>; | |
528 | }; | |
529 | ||
3debb1f3 BA |
530 | smp2p-cdsp { |
531 | compatible = "qcom,smp2p"; | |
532 | qcom,smem = <94>, <432>; | |
533 | ||
534 | interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; | |
535 | ||
536 | mboxes = <&apss_shared 6>; | |
537 | ||
538 | qcom,local-pid = <0>; | |
539 | qcom,remote-pid = <5>; | |
540 | ||
541 | cdsp_smp2p_out: master-kernel { | |
542 | qcom,entry-name = "master-kernel"; | |
543 | #qcom,smem-state-cells = <1>; | |
544 | }; | |
545 | ||
546 | cdsp_smp2p_in: slave-kernel { | |
547 | qcom,entry-name = "slave-kernel"; | |
548 | ||
549 | interrupt-controller; | |
550 | #interrupt-cells = <2>; | |
551 | }; | |
552 | }; | |
553 | ||
554 | smp2p-lpass { | |
555 | compatible = "qcom,smp2p"; | |
556 | qcom,smem = <443>, <429>; | |
557 | ||
558 | interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; | |
559 | ||
560 | mboxes = <&apss_shared 10>; | |
561 | ||
562 | qcom,local-pid = <0>; | |
563 | qcom,remote-pid = <2>; | |
564 | ||
565 | adsp_smp2p_out: master-kernel { | |
566 | qcom,entry-name = "master-kernel"; | |
567 | #qcom,smem-state-cells = <1>; | |
568 | }; | |
569 | ||
570 | adsp_smp2p_in: slave-kernel { | |
571 | qcom,entry-name = "slave-kernel"; | |
572 | ||
573 | interrupt-controller; | |
574 | #interrupt-cells = <2>; | |
575 | }; | |
576 | }; | |
577 | ||
578 | smp2p-mpss { | |
579 | compatible = "qcom,smp2p"; | |
580 | qcom,smem = <435>, <428>; | |
581 | interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; | |
582 | mboxes = <&apss_shared 14>; | |
583 | qcom,local-pid = <0>; | |
584 | qcom,remote-pid = <1>; | |
585 | ||
586 | modem_smp2p_out: master-kernel { | |
587 | qcom,entry-name = "master-kernel"; | |
588 | #qcom,smem-state-cells = <1>; | |
589 | }; | |
590 | ||
591 | modem_smp2p_in: slave-kernel { | |
592 | qcom,entry-name = "slave-kernel"; | |
593 | interrupt-controller; | |
594 | #interrupt-cells = <2>; | |
595 | }; | |
596 | }; | |
597 | ||
598 | smp2p-slpi { | |
599 | compatible = "qcom,smp2p"; | |
600 | qcom,smem = <481>, <430>; | |
601 | interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; | |
602 | mboxes = <&apss_shared 26>; | |
603 | qcom,local-pid = <0>; | |
604 | qcom,remote-pid = <3>; | |
605 | ||
606 | slpi_smp2p_out: master-kernel { | |
607 | qcom,entry-name = "master-kernel"; | |
608 | #qcom,smem-state-cells = <1>; | |
609 | }; | |
610 | ||
611 | slpi_smp2p_in: slave-kernel { | |
612 | qcom,entry-name = "slave-kernel"; | |
613 | interrupt-controller; | |
614 | #interrupt-cells = <2>; | |
615 | }; | |
616 | }; | |
617 | ||
6d4cf750 RN |
618 | psci { |
619 | compatible = "arm,psci-1.0"; | |
620 | method = "smc"; | |
621 | }; | |
622 | ||
623 | soc: soc { | |
bede7d2d BA |
624 | #address-cells = <2>; |
625 | #size-cells = <2>; | |
9feb667d BA |
626 | ranges = <0 0 0 0 0x10 0>; |
627 | dma-ranges = <0 0 0 0 0x10 0>; | |
6d4cf750 RN |
628 | compatible = "simple-bus"; |
629 | ||
54d7a20d DA |
630 | gcc: clock-controller@100000 { |
631 | compatible = "qcom,gcc-sdm845"; | |
bede7d2d | 632 | reg = <0 0x00100000 0 0x1f0000>; |
54d7a20d DA |
633 | #clock-cells = <1>; |
634 | #reset-cells = <1>; | |
635 | #power-domain-cells = <1>; | |
636 | }; | |
637 | ||
ca4db2b5 MG |
638 | qfprom@784000 { |
639 | compatible = "qcom,qfprom"; | |
bede7d2d | 640 | reg = <0 0x00784000 0 0x8ff>; |
ca4db2b5 MG |
641 | #address-cells = <1>; |
642 | #size-cells = <1>; | |
643 | ||
644 | qusb2p_hstx_trim: hstx-trim-primary@1eb { | |
645 | reg = <0x1eb 0x1>; | |
646 | bits = <1 4>; | |
647 | }; | |
648 | ||
649 | qusb2s_hstx_trim: hstx-trim-secondary@1eb { | |
650 | reg = <0x1eb 0x2>; | |
651 | bits = <6 4>; | |
652 | }; | |
653 | }; | |
654 | ||
6e17f814 VK |
655 | rng: rng@793000 { |
656 | compatible = "qcom,prng-ee"; | |
bede7d2d | 657 | reg = <0 0x00793000 0 0x1000>; |
6e17f814 VK |
658 | clocks = <&gcc GCC_PRNG_AHB_CLK>; |
659 | clock-names = "core"; | |
660 | }; | |
661 | ||
897cf34e DA |
662 | qupv3_id_0: geniqup@8c0000 { |
663 | compatible = "qcom,geni-se-qup"; | |
bede7d2d | 664 | reg = <0 0x008c0000 0 0x6000>; |
897cf34e DA |
665 | clock-names = "m-ahb", "s-ahb"; |
666 | clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, | |
667 | <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; | |
bede7d2d BA |
668 | #address-cells = <2>; |
669 | #size-cells = <2>; | |
897cf34e | 670 | ranges; |
499ff116 | 671 | status = "disabled"; |
897cf34e DA |
672 | |
673 | i2c0: i2c@880000 { | |
674 | compatible = "qcom,geni-i2c"; | |
bede7d2d | 675 | reg = <0 0x00880000 0 0x4000>; |
897cf34e DA |
676 | clock-names = "se"; |
677 | clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; | |
678 | pinctrl-names = "default"; | |
679 | pinctrl-0 = <&qup_i2c0_default>; | |
680 | interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; | |
681 | #address-cells = <1>; | |
682 | #size-cells = <0>; | |
683 | status = "disabled"; | |
684 | }; | |
685 | ||
686 | spi0: spi@880000 { | |
687 | compatible = "qcom,geni-spi"; | |
bede7d2d | 688 | reg = <0 0x00880000 0 0x4000>; |
897cf34e DA |
689 | clock-names = "se"; |
690 | clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; | |
691 | pinctrl-names = "default"; | |
692 | pinctrl-0 = <&qup_spi0_default>; | |
693 | interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; | |
694 | #address-cells = <1>; | |
695 | #size-cells = <0>; | |
696 | status = "disabled"; | |
697 | }; | |
698 | ||
bb2203d5 MK |
699 | uart0: serial@880000 { |
700 | compatible = "qcom,geni-uart"; | |
bede7d2d | 701 | reg = <0 0x00880000 0 0x4000>; |
bb2203d5 MK |
702 | clock-names = "se"; |
703 | clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; | |
704 | pinctrl-names = "default"; | |
705 | pinctrl-0 = <&qup_uart0_default>; | |
706 | interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; | |
707 | status = "disabled"; | |
708 | }; | |
709 | ||
897cf34e DA |
710 | i2c1: i2c@884000 { |
711 | compatible = "qcom,geni-i2c"; | |
bede7d2d | 712 | reg = <0 0x00884000 0 0x4000>; |
897cf34e DA |
713 | clock-names = "se"; |
714 | clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; | |
715 | pinctrl-names = "default"; | |
716 | pinctrl-0 = <&qup_i2c1_default>; | |
717 | interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; | |
718 | #address-cells = <1>; | |
719 | #size-cells = <0>; | |
720 | status = "disabled"; | |
721 | }; | |
722 | ||
723 | spi1: spi@884000 { | |
724 | compatible = "qcom,geni-spi"; | |
bede7d2d | 725 | reg = <0 0x00884000 0 0x4000>; |
897cf34e DA |
726 | clock-names = "se"; |
727 | clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; | |
728 | pinctrl-names = "default"; | |
729 | pinctrl-0 = <&qup_spi1_default>; | |
730 | interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; | |
731 | #address-cells = <1>; | |
732 | #size-cells = <0>; | |
733 | status = "disabled"; | |
734 | }; | |
735 | ||
bb2203d5 MK |
736 | uart1: serial@884000 { |
737 | compatible = "qcom,geni-uart"; | |
bede7d2d | 738 | reg = <0 0x00884000 0 0x4000>; |
bb2203d5 MK |
739 | clock-names = "se"; |
740 | clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; | |
741 | pinctrl-names = "default"; | |
742 | pinctrl-0 = <&qup_uart1_default>; | |
743 | interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; | |
744 | status = "disabled"; | |
745 | }; | |
746 | ||
897cf34e DA |
747 | i2c2: i2c@888000 { |
748 | compatible = "qcom,geni-i2c"; | |
bede7d2d | 749 | reg = <0 0x00888000 0 0x4000>; |
897cf34e DA |
750 | clock-names = "se"; |
751 | clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; | |
752 | pinctrl-names = "default"; | |
753 | pinctrl-0 = <&qup_i2c2_default>; | |
754 | interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; | |
755 | #address-cells = <1>; | |
756 | #size-cells = <0>; | |
757 | status = "disabled"; | |
758 | }; | |
759 | ||
760 | spi2: spi@888000 { | |
761 | compatible = "qcom,geni-spi"; | |
bede7d2d | 762 | reg = <0 0x00888000 0 0x4000>; |
897cf34e DA |
763 | clock-names = "se"; |
764 | clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; | |
765 | pinctrl-names = "default"; | |
766 | pinctrl-0 = <&qup_spi2_default>; | |
767 | interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; | |
768 | #address-cells = <1>; | |
769 | #size-cells = <0>; | |
770 | status = "disabled"; | |
771 | }; | |
772 | ||
bb2203d5 MK |
773 | uart2: serial@888000 { |
774 | compatible = "qcom,geni-uart"; | |
bede7d2d | 775 | reg = <0 0x00888000 0 0x4000>; |
bb2203d5 MK |
776 | clock-names = "se"; |
777 | clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; | |
778 | pinctrl-names = "default"; | |
779 | pinctrl-0 = <&qup_uart2_default>; | |
780 | interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; | |
781 | status = "disabled"; | |
782 | }; | |
783 | ||
897cf34e DA |
784 | i2c3: i2c@88c000 { |
785 | compatible = "qcom,geni-i2c"; | |
bede7d2d | 786 | reg = <0 0x0088c000 0 0x4000>; |
897cf34e DA |
787 | clock-names = "se"; |
788 | clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; | |
789 | pinctrl-names = "default"; | |
790 | pinctrl-0 = <&qup_i2c3_default>; | |
791 | interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; | |
792 | #address-cells = <1>; | |
793 | #size-cells = <0>; | |
794 | status = "disabled"; | |
795 | }; | |
796 | ||
797 | spi3: spi@88c000 { | |
798 | compatible = "qcom,geni-spi"; | |
bede7d2d | 799 | reg = <0 0x0088c000 0 0x4000>; |
897cf34e DA |
800 | clock-names = "se"; |
801 | clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; | |
802 | pinctrl-names = "default"; | |
803 | pinctrl-0 = <&qup_spi3_default>; | |
804 | interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; | |
805 | #address-cells = <1>; | |
806 | #size-cells = <0>; | |
807 | status = "disabled"; | |
808 | }; | |
809 | ||
bb2203d5 MK |
810 | uart3: serial@88c000 { |
811 | compatible = "qcom,geni-uart"; | |
bede7d2d | 812 | reg = <0 0x0088c000 0 0x4000>; |
bb2203d5 MK |
813 | clock-names = "se"; |
814 | clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; | |
815 | pinctrl-names = "default"; | |
816 | pinctrl-0 = <&qup_uart3_default>; | |
817 | interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; | |
818 | status = "disabled"; | |
819 | }; | |
820 | ||
897cf34e DA |
821 | i2c4: i2c@890000 { |
822 | compatible = "qcom,geni-i2c"; | |
bede7d2d | 823 | reg = <0 0x00890000 0 0x4000>; |
897cf34e DA |
824 | clock-names = "se"; |
825 | clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; | |
826 | pinctrl-names = "default"; | |
827 | pinctrl-0 = <&qup_i2c4_default>; | |
828 | interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; | |
829 | #address-cells = <1>; | |
830 | #size-cells = <0>; | |
831 | status = "disabled"; | |
832 | }; | |
833 | ||
834 | spi4: spi@890000 { | |
835 | compatible = "qcom,geni-spi"; | |
bede7d2d | 836 | reg = <0 0x00890000 0 0x4000>; |
897cf34e DA |
837 | clock-names = "se"; |
838 | clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; | |
839 | pinctrl-names = "default"; | |
840 | pinctrl-0 = <&qup_spi4_default>; | |
841 | interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; | |
842 | #address-cells = <1>; | |
843 | #size-cells = <0>; | |
844 | status = "disabled"; | |
845 | }; | |
846 | ||
bb2203d5 MK |
847 | uart4: serial@890000 { |
848 | compatible = "qcom,geni-uart"; | |
bede7d2d | 849 | reg = <0 0x00890000 0 0x4000>; |
bb2203d5 MK |
850 | clock-names = "se"; |
851 | clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; | |
852 | pinctrl-names = "default"; | |
853 | pinctrl-0 = <&qup_uart4_default>; | |
854 | interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; | |
855 | status = "disabled"; | |
856 | }; | |
857 | ||
897cf34e DA |
858 | i2c5: i2c@894000 { |
859 | compatible = "qcom,geni-i2c"; | |
bede7d2d | 860 | reg = <0 0x00894000 0 0x4000>; |
897cf34e DA |
861 | clock-names = "se"; |
862 | clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; | |
863 | pinctrl-names = "default"; | |
864 | pinctrl-0 = <&qup_i2c5_default>; | |
865 | interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; | |
866 | #address-cells = <1>; | |
867 | #size-cells = <0>; | |
868 | status = "disabled"; | |
869 | }; | |
870 | ||
871 | spi5: spi@894000 { | |
872 | compatible = "qcom,geni-spi"; | |
bede7d2d | 873 | reg = <0 0x00894000 0 0x4000>; |
897cf34e DA |
874 | clock-names = "se"; |
875 | clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; | |
876 | pinctrl-names = "default"; | |
877 | pinctrl-0 = <&qup_spi5_default>; | |
878 | interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; | |
879 | #address-cells = <1>; | |
880 | #size-cells = <0>; | |
881 | status = "disabled"; | |
882 | }; | |
883 | ||
bb2203d5 MK |
884 | uart5: serial@894000 { |
885 | compatible = "qcom,geni-uart"; | |
bede7d2d | 886 | reg = <0 0x00894000 0 0x4000>; |
bb2203d5 MK |
887 | clock-names = "se"; |
888 | clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; | |
889 | pinctrl-names = "default"; | |
890 | pinctrl-0 = <&qup_uart5_default>; | |
891 | interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; | |
892 | status = "disabled"; | |
893 | }; | |
894 | ||
897cf34e DA |
895 | i2c6: i2c@898000 { |
896 | compatible = "qcom,geni-i2c"; | |
bede7d2d | 897 | reg = <0 0x00898000 0 0x4000>; |
897cf34e DA |
898 | clock-names = "se"; |
899 | clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; | |
900 | pinctrl-names = "default"; | |
901 | pinctrl-0 = <&qup_i2c6_default>; | |
902 | interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; | |
903 | #address-cells = <1>; | |
904 | #size-cells = <0>; | |
905 | status = "disabled"; | |
906 | }; | |
907 | ||
908 | spi6: spi@898000 { | |
909 | compatible = "qcom,geni-spi"; | |
bede7d2d | 910 | reg = <0 0x00898000 0 0x4000>; |
897cf34e DA |
911 | clock-names = "se"; |
912 | clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; | |
913 | pinctrl-names = "default"; | |
914 | pinctrl-0 = <&qup_spi6_default>; | |
915 | interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; | |
916 | #address-cells = <1>; | |
917 | #size-cells = <0>; | |
918 | status = "disabled"; | |
919 | }; | |
920 | ||
bb2203d5 MK |
921 | uart6: serial@898000 { |
922 | compatible = "qcom,geni-uart"; | |
bede7d2d | 923 | reg = <0 0x00898000 0 0x4000>; |
bb2203d5 MK |
924 | clock-names = "se"; |
925 | clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; | |
926 | pinctrl-names = "default"; | |
927 | pinctrl-0 = <&qup_uart6_default>; | |
928 | interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; | |
929 | status = "disabled"; | |
930 | }; | |
931 | ||
897cf34e DA |
932 | i2c7: i2c@89c000 { |
933 | compatible = "qcom,geni-i2c"; | |
bede7d2d | 934 | reg = <0 0x0089c000 0 0x4000>; |
897cf34e DA |
935 | clock-names = "se"; |
936 | clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; | |
937 | pinctrl-names = "default"; | |
938 | pinctrl-0 = <&qup_i2c7_default>; | |
939 | interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; | |
940 | #address-cells = <1>; | |
941 | #size-cells = <0>; | |
942 | status = "disabled"; | |
943 | }; | |
944 | ||
945 | spi7: spi@89c000 { | |
946 | compatible = "qcom,geni-spi"; | |
bede7d2d | 947 | reg = <0 0x0089c000 0 0x4000>; |
897cf34e DA |
948 | clock-names = "se"; |
949 | clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; | |
950 | pinctrl-names = "default"; | |
951 | pinctrl-0 = <&qup_spi7_default>; | |
952 | interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; | |
953 | #address-cells = <1>; | |
954 | #size-cells = <0>; | |
955 | status = "disabled"; | |
956 | }; | |
bb2203d5 MK |
957 | |
958 | uart7: serial@89c000 { | |
959 | compatible = "qcom,geni-uart"; | |
bede7d2d | 960 | reg = <0 0x0089c000 0 0x4000>; |
bb2203d5 MK |
961 | clock-names = "se"; |
962 | clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; | |
963 | pinctrl-names = "default"; | |
964 | pinctrl-0 = <&qup_uart7_default>; | |
965 | interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; | |
966 | status = "disabled"; | |
967 | }; | |
897cf34e DA |
968 | }; |
969 | ||
970 | qupv3_id_1: geniqup@ac0000 { | |
971 | compatible = "qcom,geni-se-qup"; | |
bede7d2d | 972 | reg = <0 0x00ac0000 0 0x6000>; |
897cf34e DA |
973 | clock-names = "m-ahb", "s-ahb"; |
974 | clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, | |
975 | <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; | |
bede7d2d BA |
976 | #address-cells = <2>; |
977 | #size-cells = <2>; | |
897cf34e DA |
978 | ranges; |
979 | status = "disabled"; | |
980 | ||
981 | i2c8: i2c@a80000 { | |
982 | compatible = "qcom,geni-i2c"; | |
bede7d2d | 983 | reg = <0 0x00a80000 0 0x4000>; |
897cf34e DA |
984 | clock-names = "se"; |
985 | clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; | |
986 | pinctrl-names = "default"; | |
987 | pinctrl-0 = <&qup_i2c8_default>; | |
988 | interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; | |
989 | #address-cells = <1>; | |
990 | #size-cells = <0>; | |
991 | status = "disabled"; | |
992 | }; | |
993 | ||
994 | spi8: spi@a80000 { | |
995 | compatible = "qcom,geni-spi"; | |
bede7d2d | 996 | reg = <0 0x00a80000 0 0x4000>; |
897cf34e DA |
997 | clock-names = "se"; |
998 | clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; | |
999 | pinctrl-names = "default"; | |
1000 | pinctrl-0 = <&qup_spi8_default>; | |
1001 | interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; | |
1002 | #address-cells = <1>; | |
1003 | #size-cells = <0>; | |
1004 | status = "disabled"; | |
1005 | }; | |
1006 | ||
bb2203d5 MK |
1007 | uart8: serial@a80000 { |
1008 | compatible = "qcom,geni-uart"; | |
bede7d2d | 1009 | reg = <0 0x00a80000 0 0x4000>; |
bb2203d5 MK |
1010 | clock-names = "se"; |
1011 | clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; | |
1012 | pinctrl-names = "default"; | |
1013 | pinctrl-0 = <&qup_uart8_default>; | |
1014 | interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; | |
1015 | status = "disabled"; | |
1016 | }; | |
1017 | ||
897cf34e DA |
1018 | i2c9: i2c@a84000 { |
1019 | compatible = "qcom,geni-i2c"; | |
bede7d2d | 1020 | reg = <0 0x00a84000 0 0x4000>; |
897cf34e DA |
1021 | clock-names = "se"; |
1022 | clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; | |
1023 | pinctrl-names = "default"; | |
1024 | pinctrl-0 = <&qup_i2c9_default>; | |
1025 | interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; | |
1026 | #address-cells = <1>; | |
1027 | #size-cells = <0>; | |
1028 | status = "disabled"; | |
1029 | }; | |
1030 | ||
1031 | spi9: spi@a84000 { | |
1032 | compatible = "qcom,geni-spi"; | |
bede7d2d | 1033 | reg = <0 0x00a84000 0 0x4000>; |
897cf34e DA |
1034 | clock-names = "se"; |
1035 | clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; | |
1036 | pinctrl-names = "default"; | |
1037 | pinctrl-0 = <&qup_spi9_default>; | |
1038 | interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; | |
1039 | #address-cells = <1>; | |
1040 | #size-cells = <0>; | |
1041 | status = "disabled"; | |
1042 | }; | |
1043 | ||
1044 | uart9: serial@a84000 { | |
1045 | compatible = "qcom,geni-debug-uart"; | |
bede7d2d | 1046 | reg = <0 0x00a84000 0 0x4000>; |
897cf34e DA |
1047 | clock-names = "se"; |
1048 | clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; | |
1049 | pinctrl-names = "default"; | |
1050 | pinctrl-0 = <&qup_uart9_default>; | |
1051 | interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; | |
1052 | status = "disabled"; | |
1053 | }; | |
1054 | ||
1055 | i2c10: i2c@a88000 { | |
1056 | compatible = "qcom,geni-i2c"; | |
bede7d2d | 1057 | reg = <0 0x00a88000 0 0x4000>; |
897cf34e DA |
1058 | clock-names = "se"; |
1059 | clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; | |
1060 | pinctrl-names = "default"; | |
1061 | pinctrl-0 = <&qup_i2c10_default>; | |
1062 | interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; | |
1063 | #address-cells = <1>; | |
1064 | #size-cells = <0>; | |
1065 | status = "disabled"; | |
1066 | }; | |
1067 | ||
1068 | spi10: spi@a88000 { | |
1069 | compatible = "qcom,geni-spi"; | |
bede7d2d | 1070 | reg = <0 0x00a88000 0 0x4000>; |
897cf34e DA |
1071 | clock-names = "se"; |
1072 | clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; | |
1073 | pinctrl-names = "default"; | |
1074 | pinctrl-0 = <&qup_spi10_default>; | |
1075 | interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; | |
1076 | #address-cells = <1>; | |
1077 | #size-cells = <0>; | |
1078 | status = "disabled"; | |
1079 | }; | |
1080 | ||
bb2203d5 MK |
1081 | uart10: serial@a88000 { |
1082 | compatible = "qcom,geni-uart"; | |
bede7d2d | 1083 | reg = <0 0x00a88000 0 0x4000>; |
bb2203d5 MK |
1084 | clock-names = "se"; |
1085 | clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; | |
1086 | pinctrl-names = "default"; | |
1087 | pinctrl-0 = <&qup_uart10_default>; | |
1088 | interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; | |
1089 | status = "disabled"; | |
1090 | }; | |
1091 | ||
897cf34e DA |
1092 | i2c11: i2c@a8c000 { |
1093 | compatible = "qcom,geni-i2c"; | |
bede7d2d | 1094 | reg = <0 0x00a8c000 0 0x4000>; |
897cf34e DA |
1095 | clock-names = "se"; |
1096 | clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; | |
1097 | pinctrl-names = "default"; | |
1098 | pinctrl-0 = <&qup_i2c11_default>; | |
1099 | interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; | |
1100 | #address-cells = <1>; | |
1101 | #size-cells = <0>; | |
1102 | status = "disabled"; | |
1103 | }; | |
1104 | ||
1105 | spi11: spi@a8c000 { | |
1106 | compatible = "qcom,geni-spi"; | |
bede7d2d | 1107 | reg = <0 0x00a8c000 0 0x4000>; |
897cf34e DA |
1108 | clock-names = "se"; |
1109 | clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; | |
1110 | pinctrl-names = "default"; | |
1111 | pinctrl-0 = <&qup_spi11_default>; | |
1112 | interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; | |
1113 | #address-cells = <1>; | |
1114 | #size-cells = <0>; | |
1115 | status = "disabled"; | |
1116 | }; | |
1117 | ||
bb2203d5 MK |
1118 | uart11: serial@a8c000 { |
1119 | compatible = "qcom,geni-uart"; | |
bede7d2d | 1120 | reg = <0 0x00a8c000 0 0x4000>; |
bb2203d5 MK |
1121 | clock-names = "se"; |
1122 | clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; | |
1123 | pinctrl-names = "default"; | |
1124 | pinctrl-0 = <&qup_uart11_default>; | |
1125 | interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; | |
1126 | status = "disabled"; | |
1127 | }; | |
1128 | ||
897cf34e DA |
1129 | i2c12: i2c@a90000 { |
1130 | compatible = "qcom,geni-i2c"; | |
bede7d2d | 1131 | reg = <0 0x00a90000 0 0x4000>; |
897cf34e DA |
1132 | clock-names = "se"; |
1133 | clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; | |
1134 | pinctrl-names = "default"; | |
1135 | pinctrl-0 = <&qup_i2c12_default>; | |
1136 | interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; | |
1137 | #address-cells = <1>; | |
1138 | #size-cells = <0>; | |
1139 | status = "disabled"; | |
1140 | }; | |
1141 | ||
1142 | spi12: spi@a90000 { | |
1143 | compatible = "qcom,geni-spi"; | |
bede7d2d | 1144 | reg = <0 0x00a90000 0 0x4000>; |
897cf34e DA |
1145 | clock-names = "se"; |
1146 | clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; | |
1147 | pinctrl-names = "default"; | |
1148 | pinctrl-0 = <&qup_spi12_default>; | |
1149 | interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; | |
1150 | #address-cells = <1>; | |
1151 | #size-cells = <0>; | |
1152 | status = "disabled"; | |
1153 | }; | |
1154 | ||
bb2203d5 MK |
1155 | uart12: serial@a90000 { |
1156 | compatible = "qcom,geni-uart"; | |
bede7d2d | 1157 | reg = <0 0x00a90000 0 0x4000>; |
bb2203d5 MK |
1158 | clock-names = "se"; |
1159 | clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; | |
1160 | pinctrl-names = "default"; | |
1161 | pinctrl-0 = <&qup_uart12_default>; | |
1162 | interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; | |
1163 | status = "disabled"; | |
1164 | }; | |
1165 | ||
897cf34e DA |
1166 | i2c13: i2c@a94000 { |
1167 | compatible = "qcom,geni-i2c"; | |
bede7d2d | 1168 | reg = <0 0x00a94000 0 0x4000>; |
897cf34e DA |
1169 | clock-names = "se"; |
1170 | clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; | |
1171 | pinctrl-names = "default"; | |
1172 | pinctrl-0 = <&qup_i2c13_default>; | |
1173 | interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; | |
1174 | #address-cells = <1>; | |
1175 | #size-cells = <0>; | |
1176 | status = "disabled"; | |
1177 | }; | |
1178 | ||
1179 | spi13: spi@a94000 { | |
1180 | compatible = "qcom,geni-spi"; | |
bede7d2d | 1181 | reg = <0 0x00a94000 0 0x4000>; |
897cf34e DA |
1182 | clock-names = "se"; |
1183 | clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; | |
1184 | pinctrl-names = "default"; | |
1185 | pinctrl-0 = <&qup_spi13_default>; | |
1186 | interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; | |
1187 | #address-cells = <1>; | |
1188 | #size-cells = <0>; | |
1189 | status = "disabled"; | |
1190 | }; | |
1191 | ||
bb2203d5 MK |
1192 | uart13: serial@a94000 { |
1193 | compatible = "qcom,geni-uart"; | |
bede7d2d | 1194 | reg = <0 0x00a94000 0 0x4000>; |
bb2203d5 MK |
1195 | clock-names = "se"; |
1196 | clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; | |
1197 | pinctrl-names = "default"; | |
1198 | pinctrl-0 = <&qup_uart13_default>; | |
1199 | interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; | |
1200 | status = "disabled"; | |
1201 | }; | |
1202 | ||
897cf34e DA |
1203 | i2c14: i2c@a98000 { |
1204 | compatible = "qcom,geni-i2c"; | |
bede7d2d | 1205 | reg = <0 0x00a98000 0 0x4000>; |
897cf34e DA |
1206 | clock-names = "se"; |
1207 | clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; | |
1208 | pinctrl-names = "default"; | |
1209 | pinctrl-0 = <&qup_i2c14_default>; | |
1210 | interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; | |
1211 | #address-cells = <1>; | |
1212 | #size-cells = <0>; | |
1213 | status = "disabled"; | |
1214 | }; | |
1215 | ||
1216 | spi14: spi@a98000 { | |
1217 | compatible = "qcom,geni-spi"; | |
bede7d2d | 1218 | reg = <0 0x00a98000 0 0x4000>; |
897cf34e DA |
1219 | clock-names = "se"; |
1220 | clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; | |
1221 | pinctrl-names = "default"; | |
1222 | pinctrl-0 = <&qup_spi14_default>; | |
1223 | interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; | |
1224 | #address-cells = <1>; | |
1225 | #size-cells = <0>; | |
1226 | status = "disabled"; | |
1227 | }; | |
1228 | ||
bb2203d5 MK |
1229 | uart14: serial@a98000 { |
1230 | compatible = "qcom,geni-uart"; | |
bede7d2d | 1231 | reg = <0 0x00a98000 0 0x4000>; |
bb2203d5 MK |
1232 | clock-names = "se"; |
1233 | clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; | |
1234 | pinctrl-names = "default"; | |
1235 | pinctrl-0 = <&qup_uart14_default>; | |
1236 | interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; | |
1237 | status = "disabled"; | |
1238 | }; | |
1239 | ||
897cf34e DA |
1240 | i2c15: i2c@a9c000 { |
1241 | compatible = "qcom,geni-i2c"; | |
bede7d2d | 1242 | reg = <0 0x00a9c000 0 0x4000>; |
897cf34e DA |
1243 | clock-names = "se"; |
1244 | clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; | |
1245 | pinctrl-names = "default"; | |
1246 | pinctrl-0 = <&qup_i2c15_default>; | |
1247 | interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; | |
1248 | #address-cells = <1>; | |
1249 | #size-cells = <0>; | |
1250 | status = "disabled"; | |
1251 | }; | |
1252 | ||
1253 | spi15: spi@a9c000 { | |
1254 | compatible = "qcom,geni-spi"; | |
bede7d2d | 1255 | reg = <0 0x00a9c000 0 0x4000>; |
897cf34e DA |
1256 | clock-names = "se"; |
1257 | clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; | |
1258 | pinctrl-names = "default"; | |
1259 | pinctrl-0 = <&qup_spi15_default>; | |
1260 | interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; | |
1261 | #address-cells = <1>; | |
1262 | #size-cells = <0>; | |
1263 | status = "disabled"; | |
1264 | }; | |
bb2203d5 MK |
1265 | |
1266 | uart15: serial@a9c000 { | |
1267 | compatible = "qcom,geni-uart"; | |
bede7d2d | 1268 | reg = <0 0x00a9c000 0 0x4000>; |
bb2203d5 MK |
1269 | clock-names = "se"; |
1270 | clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; | |
1271 | pinctrl-names = "default"; | |
1272 | pinctrl-0 = <&qup_uart15_default>; | |
1273 | interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; | |
1274 | status = "disabled"; | |
1275 | }; | |
897cf34e DA |
1276 | }; |
1277 | ||
cc16687f EG |
1278 | ufs_mem_hc: ufshc@1d84000 { |
1279 | compatible = "qcom,sdm845-ufshc", "qcom,ufshc", | |
1280 | "jedec,ufs-2.0"; | |
bede7d2d | 1281 | reg = <0 0x01d84000 0 0x2500>; |
cc16687f EG |
1282 | interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; |
1283 | phys = <&ufs_mem_phy_lanes>; | |
1284 | phy-names = "ufsphy"; | |
1285 | lanes-per-direction = <2>; | |
1286 | power-domains = <&gcc UFS_PHY_GDSC>; | |
71278b05 | 1287 | #reset-cells = <1>; |
cc16687f EG |
1288 | |
1289 | iommus = <&apps_smmu 0x100 0xf>; | |
1290 | ||
1291 | clock-names = | |
1292 | "core_clk", | |
1293 | "bus_aggr_clk", | |
1294 | "iface_clk", | |
1295 | "core_clk_unipro", | |
1296 | "ref_clk", | |
1297 | "tx_lane0_sync_clk", | |
1298 | "rx_lane0_sync_clk", | |
1299 | "rx_lane1_sync_clk"; | |
1300 | clocks = | |
1301 | <&gcc GCC_UFS_PHY_AXI_CLK>, | |
1302 | <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, | |
1303 | <&gcc GCC_UFS_PHY_AHB_CLK>, | |
1304 | <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, | |
1305 | <&rpmhcc RPMH_CXO_CLK>, | |
1306 | <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, | |
1307 | <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, | |
1308 | <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; | |
1309 | freq-table-hz = | |
1310 | <50000000 200000000>, | |
1311 | <0 0>, | |
1312 | <0 0>, | |
1313 | <37500000 150000000>, | |
1314 | <0 0>, | |
1315 | <0 0>, | |
1316 | <0 0>, | |
1317 | <0 0>; | |
1318 | ||
1319 | status = "disabled"; | |
1320 | }; | |
1321 | ||
1322 | ufs_mem_phy: phy@1d87000 { | |
1323 | compatible = "qcom,sdm845-qmp-ufs-phy"; | |
bede7d2d BA |
1324 | reg = <0 0x01d87000 0 0x18c>; |
1325 | #address-cells = <2>; | |
1326 | #size-cells = <2>; | |
cc16687f EG |
1327 | ranges; |
1328 | clock-names = "ref", | |
1329 | "ref_aux"; | |
1330 | clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, | |
1331 | <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; | |
1332 | ||
71278b05 EG |
1333 | resets = <&ufs_mem_hc 0>; |
1334 | reset-names = "ufsphy"; | |
cc16687f EG |
1335 | status = "disabled"; |
1336 | ||
1337 | ufs_mem_phy_lanes: lanes@1d87400 { | |
bede7d2d BA |
1338 | reg = <0 0x01d87400 0 0x108>, |
1339 | <0 0x01d87600 0 0x1e0>, | |
1340 | <0 0x01d87c00 0 0x1dc>, | |
1341 | <0 0x01d87800 0 0x108>, | |
1342 | <0 0x01d87a00 0 0x1e0>; | |
cc16687f EG |
1343 | #phy-cells = <0>; |
1344 | }; | |
1345 | }; | |
1346 | ||
54d7a20d DA |
1347 | tcsr_mutex_regs: syscon@1f40000 { |
1348 | compatible = "syscon"; | |
bede7d2d | 1349 | reg = <0 0x01f40000 0 0x40000>; |
54d7a20d DA |
1350 | }; |
1351 | ||
1352 | tlmm: pinctrl@3400000 { | |
1353 | compatible = "qcom,sdm845-pinctrl"; | |
bede7d2d | 1354 | reg = <0 0x03400000 0 0xc00000>; |
54d7a20d DA |
1355 | interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
1356 | gpio-controller; | |
1357 | #gpio-cells = <2>; | |
1358 | interrupt-controller; | |
1359 | #interrupt-cells = <2>; | |
bc2c8062 | 1360 | gpio-ranges = <&tlmm 0 0 150>; |
897cf34e | 1361 | |
e1ce8539 DA |
1362 | qspi_clk: qspi-clk { |
1363 | pinmux { | |
1364 | pins = "gpio95"; | |
1365 | function = "qspi_clk"; | |
1366 | }; | |
1367 | }; | |
1368 | ||
1369 | qspi_cs0: qspi-cs0 { | |
1370 | pinmux { | |
1371 | pins = "gpio90"; | |
1372 | function = "qspi_cs"; | |
1373 | }; | |
1374 | }; | |
1375 | ||
1376 | qspi_cs1: qspi-cs1 { | |
1377 | pinmux { | |
1378 | pins = "gpio89"; | |
1379 | function = "qspi_cs"; | |
1380 | }; | |
1381 | }; | |
1382 | ||
1383 | qspi_data01: qspi-data01 { | |
1384 | pinmux-data { | |
1385 | pins = "gpio91", "gpio92"; | |
1386 | function = "qspi_data"; | |
1387 | }; | |
1388 | }; | |
1389 | ||
1390 | qspi_data12: qspi-data12 { | |
1391 | pinmux-data { | |
1392 | pins = "gpio93", "gpio94"; | |
1393 | function = "qspi_data"; | |
1394 | }; | |
1395 | }; | |
1396 | ||
897cf34e DA |
1397 | qup_i2c0_default: qup-i2c0-default { |
1398 | pinmux { | |
1399 | pins = "gpio0", "gpio1"; | |
1400 | function = "qup0"; | |
1401 | }; | |
1402 | }; | |
1403 | ||
1404 | qup_i2c1_default: qup-i2c1-default { | |
1405 | pinmux { | |
1406 | pins = "gpio17", "gpio18"; | |
1407 | function = "qup1"; | |
1408 | }; | |
1409 | }; | |
1410 | ||
1411 | qup_i2c2_default: qup-i2c2-default { | |
1412 | pinmux { | |
1413 | pins = "gpio27", "gpio28"; | |
1414 | function = "qup2"; | |
1415 | }; | |
1416 | }; | |
1417 | ||
1418 | qup_i2c3_default: qup-i2c3-default { | |
1419 | pinmux { | |
1420 | pins = "gpio41", "gpio42"; | |
1421 | function = "qup3"; | |
1422 | }; | |
1423 | }; | |
1424 | ||
1425 | qup_i2c4_default: qup-i2c4-default { | |
1426 | pinmux { | |
1427 | pins = "gpio89", "gpio90"; | |
1428 | function = "qup4"; | |
1429 | }; | |
1430 | }; | |
1431 | ||
1432 | qup_i2c5_default: qup-i2c5-default { | |
1433 | pinmux { | |
1434 | pins = "gpio85", "gpio86"; | |
1435 | function = "qup5"; | |
1436 | }; | |
1437 | }; | |
1438 | ||
1439 | qup_i2c6_default: qup-i2c6-default { | |
1440 | pinmux { | |
1441 | pins = "gpio45", "gpio46"; | |
1442 | function = "qup6"; | |
1443 | }; | |
1444 | }; | |
1445 | ||
1446 | qup_i2c7_default: qup-i2c7-default { | |
1447 | pinmux { | |
1448 | pins = "gpio93", "gpio94"; | |
1449 | function = "qup7"; | |
1450 | }; | |
1451 | }; | |
1452 | ||
1453 | qup_i2c8_default: qup-i2c8-default { | |
1454 | pinmux { | |
1455 | pins = "gpio65", "gpio66"; | |
1456 | function = "qup8"; | |
1457 | }; | |
1458 | }; | |
1459 | ||
1460 | qup_i2c9_default: qup-i2c9-default { | |
1461 | pinmux { | |
1462 | pins = "gpio6", "gpio7"; | |
1463 | function = "qup9"; | |
1464 | }; | |
1465 | }; | |
1466 | ||
1467 | qup_i2c10_default: qup-i2c10-default { | |
1468 | pinmux { | |
1469 | pins = "gpio55", "gpio56"; | |
1470 | function = "qup10"; | |
1471 | }; | |
1472 | }; | |
1473 | ||
1474 | qup_i2c11_default: qup-i2c11-default { | |
1475 | pinmux { | |
1476 | pins = "gpio31", "gpio32"; | |
1477 | function = "qup11"; | |
1478 | }; | |
1479 | }; | |
1480 | ||
1481 | qup_i2c12_default: qup-i2c12-default { | |
1482 | pinmux { | |
1483 | pins = "gpio49", "gpio50"; | |
1484 | function = "qup12"; | |
1485 | }; | |
1486 | }; | |
1487 | ||
1488 | qup_i2c13_default: qup-i2c13-default { | |
1489 | pinmux { | |
1490 | pins = "gpio105", "gpio106"; | |
1491 | function = "qup13"; | |
1492 | }; | |
1493 | }; | |
1494 | ||
1495 | qup_i2c14_default: qup-i2c14-default { | |
1496 | pinmux { | |
1497 | pins = "gpio33", "gpio34"; | |
1498 | function = "qup14"; | |
1499 | }; | |
1500 | }; | |
1501 | ||
1502 | qup_i2c15_default: qup-i2c15-default { | |
1503 | pinmux { | |
1504 | pins = "gpio81", "gpio82"; | |
1505 | function = "qup15"; | |
1506 | }; | |
1507 | }; | |
1508 | ||
1509 | qup_spi0_default: qup-spi0-default { | |
1510 | pinmux { | |
1511 | pins = "gpio0", "gpio1", | |
1512 | "gpio2", "gpio3"; | |
1513 | function = "qup0"; | |
1514 | }; | |
1515 | }; | |
1516 | ||
1517 | qup_spi1_default: qup-spi1-default { | |
1518 | pinmux { | |
1519 | pins = "gpio17", "gpio18", | |
1520 | "gpio19", "gpio20"; | |
1521 | function = "qup1"; | |
1522 | }; | |
1523 | }; | |
1524 | ||
1525 | qup_spi2_default: qup-spi2-default { | |
1526 | pinmux { | |
1527 | pins = "gpio27", "gpio28", | |
1528 | "gpio29", "gpio30"; | |
1529 | function = "qup2"; | |
1530 | }; | |
1531 | }; | |
1532 | ||
1533 | qup_spi3_default: qup-spi3-default { | |
1534 | pinmux { | |
1535 | pins = "gpio41", "gpio42", | |
1536 | "gpio43", "gpio44"; | |
1537 | function = "qup3"; | |
1538 | }; | |
1539 | }; | |
1540 | ||
1541 | qup_spi4_default: qup-spi4-default { | |
1542 | pinmux { | |
1543 | pins = "gpio89", "gpio90", | |
1544 | "gpio91", "gpio92"; | |
1545 | function = "qup4"; | |
1546 | }; | |
1547 | }; | |
1548 | ||
1549 | qup_spi5_default: qup-spi5-default { | |
1550 | pinmux { | |
1551 | pins = "gpio85", "gpio86", | |
1552 | "gpio87", "gpio88"; | |
1553 | function = "qup5"; | |
1554 | }; | |
1555 | }; | |
1556 | ||
1557 | qup_spi6_default: qup-spi6-default { | |
1558 | pinmux { | |
1559 | pins = "gpio45", "gpio46", | |
1560 | "gpio47", "gpio48"; | |
1561 | function = "qup6"; | |
1562 | }; | |
1563 | }; | |
1564 | ||
1565 | qup_spi7_default: qup-spi7-default { | |
1566 | pinmux { | |
1567 | pins = "gpio93", "gpio94", | |
1568 | "gpio95", "gpio96"; | |
1569 | function = "qup7"; | |
1570 | }; | |
1571 | }; | |
1572 | ||
1573 | qup_spi8_default: qup-spi8-default { | |
1574 | pinmux { | |
1575 | pins = "gpio65", "gpio66", | |
1576 | "gpio67", "gpio68"; | |
1577 | function = "qup8"; | |
1578 | }; | |
1579 | }; | |
1580 | ||
1581 | qup_spi9_default: qup-spi9-default { | |
1582 | pinmux { | |
1583 | pins = "gpio6", "gpio7", | |
1584 | "gpio4", "gpio5"; | |
1585 | function = "qup9"; | |
1586 | }; | |
1587 | }; | |
1588 | ||
1589 | qup_spi10_default: qup-spi10-default { | |
1590 | pinmux { | |
1591 | pins = "gpio55", "gpio56", | |
1592 | "gpio53", "gpio54"; | |
1593 | function = "qup10"; | |
1594 | }; | |
1595 | }; | |
1596 | ||
1597 | qup_spi11_default: qup-spi11-default { | |
1598 | pinmux { | |
1599 | pins = "gpio31", "gpio32", | |
1600 | "gpio33", "gpio34"; | |
1601 | function = "qup11"; | |
1602 | }; | |
1603 | }; | |
1604 | ||
1605 | qup_spi12_default: qup-spi12-default { | |
1606 | pinmux { | |
1607 | pins = "gpio49", "gpio50", | |
1608 | "gpio51", "gpio52"; | |
1609 | function = "qup12"; | |
1610 | }; | |
1611 | }; | |
1612 | ||
1613 | qup_spi13_default: qup-spi13-default { | |
1614 | pinmux { | |
1615 | pins = "gpio105", "gpio106", | |
1616 | "gpio107", "gpio108"; | |
1617 | function = "qup13"; | |
1618 | }; | |
1619 | }; | |
1620 | ||
1621 | qup_spi14_default: qup-spi14-default { | |
1622 | pinmux { | |
1623 | pins = "gpio33", "gpio34", | |
1624 | "gpio31", "gpio32"; | |
1625 | function = "qup14"; | |
1626 | }; | |
1627 | }; | |
1628 | ||
1629 | qup_spi15_default: qup-spi15-default { | |
1630 | pinmux { | |
1631 | pins = "gpio81", "gpio82", | |
1632 | "gpio83", "gpio84"; | |
1633 | function = "qup15"; | |
1634 | }; | |
1635 | }; | |
1636 | ||
bb2203d5 MK |
1637 | qup_uart0_default: qup-uart0-default { |
1638 | pinmux { | |
1639 | pins = "gpio2", "gpio3"; | |
1640 | function = "qup0"; | |
1641 | }; | |
1642 | }; | |
1643 | ||
1644 | qup_uart1_default: qup-uart1-default { | |
1645 | pinmux { | |
1646 | pins = "gpio19", "gpio20"; | |
1647 | function = "qup1"; | |
1648 | }; | |
1649 | }; | |
1650 | ||
1651 | qup_uart2_default: qup-uart2-default { | |
1652 | pinmux { | |
1653 | pins = "gpio29", "gpio30"; | |
1654 | function = "qup2"; | |
1655 | }; | |
1656 | }; | |
1657 | ||
1658 | qup_uart3_default: qup-uart3-default { | |
1659 | pinmux { | |
1660 | pins = "gpio43", "gpio44"; | |
1661 | function = "qup3"; | |
1662 | }; | |
1663 | }; | |
1664 | ||
1665 | qup_uart4_default: qup-uart4-default { | |
1666 | pinmux { | |
1667 | pins = "gpio91", "gpio92"; | |
1668 | function = "qup4"; | |
1669 | }; | |
1670 | }; | |
1671 | ||
1672 | qup_uart5_default: qup-uart5-default { | |
1673 | pinmux { | |
1674 | pins = "gpio87", "gpio88"; | |
1675 | function = "qup5"; | |
1676 | }; | |
1677 | }; | |
1678 | ||
1679 | qup_uart6_default: qup-uart6-default { | |
1680 | pinmux { | |
1681 | pins = "gpio47", "gpio48"; | |
1682 | function = "qup6"; | |
1683 | }; | |
1684 | }; | |
1685 | ||
1686 | qup_uart7_default: qup-uart7-default { | |
1687 | pinmux { | |
1688 | pins = "gpio95", "gpio96"; | |
1689 | function = "qup7"; | |
1690 | }; | |
1691 | }; | |
1692 | ||
1693 | qup_uart8_default: qup-uart8-default { | |
1694 | pinmux { | |
1695 | pins = "gpio67", "gpio68"; | |
1696 | function = "qup8"; | |
1697 | }; | |
1698 | }; | |
1699 | ||
897cf34e DA |
1700 | qup_uart9_default: qup-uart9-default { |
1701 | pinmux { | |
1702 | pins = "gpio4", "gpio5"; | |
1703 | function = "qup9"; | |
1704 | }; | |
1705 | }; | |
bb2203d5 MK |
1706 | |
1707 | qup_uart10_default: qup-uart10-default { | |
1708 | pinmux { | |
1709 | pins = "gpio53", "gpio54"; | |
1710 | function = "qup10"; | |
1711 | }; | |
1712 | }; | |
1713 | ||
1714 | qup_uart11_default: qup-uart11-default { | |
1715 | pinmux { | |
1716 | pins = "gpio33", "gpio34"; | |
1717 | function = "qup11"; | |
1718 | }; | |
1719 | }; | |
1720 | ||
1721 | qup_uart12_default: qup-uart12-default { | |
1722 | pinmux { | |
1723 | pins = "gpio51", "gpio52"; | |
1724 | function = "qup12"; | |
1725 | }; | |
1726 | }; | |
1727 | ||
1728 | qup_uart13_default: qup-uart13-default { | |
1729 | pinmux { | |
1730 | pins = "gpio107", "gpio108"; | |
1731 | function = "qup13"; | |
1732 | }; | |
1733 | }; | |
1734 | ||
1735 | qup_uart14_default: qup-uart14-default { | |
1736 | pinmux { | |
1737 | pins = "gpio31", "gpio32"; | |
1738 | function = "qup14"; | |
1739 | }; | |
1740 | }; | |
1741 | ||
1742 | qup_uart15_default: qup-uart15-default { | |
1743 | pinmux { | |
1744 | pins = "gpio83", "gpio84"; | |
1745 | function = "qup15"; | |
1746 | }; | |
1747 | }; | |
54d7a20d DA |
1748 | }; |
1749 | ||
e76c3672 SS |
1750 | mss_pil: remoteproc@4080000 { |
1751 | compatible = "qcom,sdm845-mss-pil"; | |
1752 | reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; | |
1753 | reg-names = "qdsp6", "rmb"; | |
1754 | ||
1755 | interrupts-extended = | |
1756 | <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, | |
1757 | <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, | |
1758 | <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, | |
1759 | <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, | |
1760 | <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, | |
1761 | <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; | |
1762 | interrupt-names = "wdog", "fatal", "ready", | |
1763 | "handover", "stop-ack", | |
1764 | "shutdown-ack"; | |
1765 | ||
1766 | clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, | |
1767 | <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, | |
1768 | <&gcc GCC_BOOT_ROM_AHB_CLK>, | |
1769 | <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, | |
1770 | <&gcc GCC_MSS_SNOC_AXI_CLK>, | |
1771 | <&gcc GCC_MSS_MFAB_AXIS_CLK>, | |
1772 | <&gcc GCC_PRNG_AHB_CLK>, | |
1773 | <&rpmhcc RPMH_CXO_CLK>; | |
1774 | clock-names = "iface", "bus", "mem", "gpll0_mss", | |
1775 | "snoc_axi", "mnoc_axi", "prng", "xo"; | |
1776 | ||
1777 | qcom,smem-states = <&modem_smp2p_out 0>; | |
1778 | qcom,smem-state-names = "stop"; | |
1779 | ||
1780 | resets = <&aoss_reset AOSS_CC_MSS_RESTART>, | |
1781 | <&pdc_reset PDC_MODEM_SYNC_RESET>; | |
1782 | reset-names = "mss_restart", "pdc_reset"; | |
1783 | ||
1784 | qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; | |
1785 | ||
1786 | power-domains = <&aoss_qmp 2>, | |
1787 | <&rpmhpd SDM845_CX>, | |
1788 | <&rpmhpd SDM845_MX>, | |
1789 | <&rpmhpd SDM845_MSS>; | |
1790 | power-domain-names = "load_state", "cx", "mx", "mss"; | |
1791 | ||
1792 | mba { | |
1793 | memory-region = <&mba_region>; | |
1794 | }; | |
1795 | ||
1796 | mpss { | |
1797 | memory-region = <&mpss_region>; | |
1798 | }; | |
1799 | ||
1800 | glink-edge { | |
1801 | interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; | |
1802 | label = "modem"; | |
1803 | qcom,remote-pid = <1>; | |
1804 | mboxes = <&apss_shared 12>; | |
1805 | }; | |
1806 | }; | |
1807 | ||
9aa4a27e DA |
1808 | gpucc: clock-controller@5090000 { |
1809 | compatible = "qcom,sdm845-gpucc"; | |
bede7d2d | 1810 | reg = <0 0x05090000 0 0x9000>; |
9aa4a27e DA |
1811 | #clock-cells = <1>; |
1812 | #reset-cells = <1>; | |
1813 | #power-domain-cells = <1>; | |
1814 | clocks = <&rpmhcc RPMH_CXO_CLK>; | |
1815 | clock-names = "xo"; | |
1816 | }; | |
1817 | ||
67d62e5a EG |
1818 | sdhc_2: sdhci@8804000 { |
1819 | compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; | |
bede7d2d | 1820 | reg = <0 0x08804000 0 0x1000>; |
67d62e5a EG |
1821 | |
1822 | interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, | |
1823 | <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; | |
1824 | interrupt-names = "hc_irq", "pwr_irq"; | |
1825 | ||
1826 | clocks = <&gcc GCC_SDCC2_AHB_CLK>, | |
1827 | <&gcc GCC_SDCC2_APPS_CLK>; | |
1828 | clock-names = "iface", "core"; | |
55fae1d5 | 1829 | iommus = <&apps_smmu 0xa0 0xf>; |
67d62e5a EG |
1830 | |
1831 | status = "disabled"; | |
1832 | }; | |
1833 | ||
e1ce8539 DA |
1834 | qspi: spi@88df000 { |
1835 | compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; | |
bede7d2d | 1836 | reg = <0 0x088df000 0 0x600>; |
e1ce8539 DA |
1837 | #address-cells = <1>; |
1838 | #size-cells = <0>; | |
1839 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; | |
1840 | clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, | |
1841 | <&gcc GCC_QSPI_CORE_CLK>; | |
1842 | clock-names = "iface", "core"; | |
1843 | status = "disabled"; | |
1844 | }; | |
1845 | ||
ca4db2b5 MG |
1846 | usb_1_hsphy: phy@88e2000 { |
1847 | compatible = "qcom,sdm845-qusb2-phy"; | |
bede7d2d | 1848 | reg = <0 0x088e2000 0 0x400>; |
ca4db2b5 MG |
1849 | status = "disabled"; |
1850 | #phy-cells = <0>; | |
1851 | ||
1852 | clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, | |
1853 | <&rpmhcc RPMH_CXO_CLK>; | |
1854 | clock-names = "cfg_ahb", "ref"; | |
1855 | ||
1856 | resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; | |
1857 | ||
1858 | nvmem-cells = <&qusb2p_hstx_trim>; | |
1859 | }; | |
1860 | ||
1861 | usb_2_hsphy: phy@88e3000 { | |
1862 | compatible = "qcom,sdm845-qusb2-phy"; | |
bede7d2d | 1863 | reg = <0 0x088e3000 0 0x400>; |
ca4db2b5 MG |
1864 | status = "disabled"; |
1865 | #phy-cells = <0>; | |
1866 | ||
1867 | clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, | |
1868 | <&rpmhcc RPMH_CXO_CLK>; | |
1869 | clock-names = "cfg_ahb", "ref"; | |
1870 | ||
1871 | resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; | |
1872 | ||
1873 | nvmem-cells = <&qusb2s_hstx_trim>; | |
1874 | }; | |
1875 | ||
1876 | usb_1_qmpphy: phy@88e9000 { | |
1877 | compatible = "qcom,sdm845-qmp-usb3-phy"; | |
bede7d2d BA |
1878 | reg = <0 0x088e9000 0 0x18c>, |
1879 | <0 0x088e8000 0 0x10>; | |
ca4db2b5 MG |
1880 | reg-names = "reg-base", "dp_com"; |
1881 | status = "disabled"; | |
1882 | #clock-cells = <1>; | |
bede7d2d BA |
1883 | #address-cells = <2>; |
1884 | #size-cells = <2>; | |
ca4db2b5 MG |
1885 | ranges; |
1886 | ||
1887 | clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, | |
1888 | <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, | |
1889 | <&gcc GCC_USB3_PRIM_CLKREF_CLK>, | |
1890 | <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; | |
1891 | clock-names = "aux", "cfg_ahb", "ref", "com_aux"; | |
1892 | ||
1893 | resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, | |
1894 | <&gcc GCC_USB3_PHY_PRIM_BCR>; | |
1895 | reset-names = "phy", "common"; | |
1896 | ||
9ebfcba1 | 1897 | usb_1_ssphy: lanes@88e9200 { |
bede7d2d BA |
1898 | reg = <0 0x088e9200 0 0x128>, |
1899 | <0 0x088e9400 0 0x200>, | |
1900 | <0 0x088e9c00 0 0x218>, | |
1901 | <0 0x088e9600 0 0x128>, | |
1902 | <0 0x088e9800 0 0x200>, | |
1903 | <0 0x088e9a00 0 0x100>; | |
ca4db2b5 MG |
1904 | #phy-cells = <0>; |
1905 | clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; | |
1906 | clock-names = "pipe0"; | |
1907 | clock-output-names = "usb3_phy_pipe_clk_src"; | |
1908 | }; | |
1909 | }; | |
1910 | ||
1911 | usb_2_qmpphy: phy@88eb000 { | |
1912 | compatible = "qcom,sdm845-qmp-usb3-uni-phy"; | |
bede7d2d | 1913 | reg = <0 0x088eb000 0 0x18c>; |
ca4db2b5 MG |
1914 | status = "disabled"; |
1915 | #clock-cells = <1>; | |
bede7d2d BA |
1916 | #address-cells = <2>; |
1917 | #size-cells = <2>; | |
ca4db2b5 MG |
1918 | ranges; |
1919 | ||
1920 | clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, | |
1921 | <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, | |
1922 | <&gcc GCC_USB3_SEC_CLKREF_CLK>, | |
1923 | <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; | |
1924 | clock-names = "aux", "cfg_ahb", "ref", "com_aux"; | |
1925 | ||
1926 | resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, | |
1927 | <&gcc GCC_USB3_PHY_SEC_BCR>; | |
1928 | reset-names = "phy", "common"; | |
1929 | ||
1930 | usb_2_ssphy: lane@88eb200 { | |
bede7d2d BA |
1931 | reg = <0 0x088eb200 0 0x128>, |
1932 | <0 0x088eb400 0 0x1fc>, | |
1933 | <0 0x088eb800 0 0x218>, | |
1934 | <0 0x088eb600 0 0x70>; | |
ca4db2b5 MG |
1935 | #phy-cells = <0>; |
1936 | clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; | |
1937 | clock-names = "pipe0"; | |
1938 | clock-output-names = "usb3_uni_phy_pipe_clk_src"; | |
1939 | }; | |
1940 | }; | |
1941 | ||
1942 | usb_1: usb@a6f8800 { | |
1943 | compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; | |
bede7d2d | 1944 | reg = <0 0x0a6f8800 0 0x400>; |
ca4db2b5 | 1945 | status = "disabled"; |
bede7d2d BA |
1946 | #address-cells = <2>; |
1947 | #size-cells = <2>; | |
ca4db2b5 | 1948 | ranges; |
9a8a9d17 | 1949 | dma-ranges; |
ca4db2b5 MG |
1950 | |
1951 | clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, | |
1952 | <&gcc GCC_USB30_PRIM_MASTER_CLK>, | |
1953 | <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, | |
1954 | <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, | |
1955 | <&gcc GCC_USB30_PRIM_SLEEP_CLK>; | |
1956 | clock-names = "cfg_noc", "core", "iface", "mock_utmi", | |
1957 | "sleep"; | |
1958 | ||
1959 | assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, | |
1960 | <&gcc GCC_USB30_PRIM_MASTER_CLK>; | |
1961 | assigned-clock-rates = <19200000>, <150000000>; | |
1962 | ||
1963 | interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, | |
1964 | <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, | |
1965 | <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, | |
1966 | <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; | |
1967 | interrupt-names = "hs_phy_irq", "ss_phy_irq", | |
1968 | "dm_hs_phy_irq", "dp_hs_phy_irq"; | |
1969 | ||
1970 | power-domains = <&gcc USB30_PRIM_GDSC>; | |
1971 | ||
1972 | resets = <&gcc GCC_USB30_PRIM_BCR>; | |
1973 | ||
1974 | usb_1_dwc3: dwc3@a600000 { | |
1975 | compatible = "snps,dwc3"; | |
bede7d2d | 1976 | reg = <0 0x0a600000 0 0xcd00>; |
ca4db2b5 | 1977 | interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; |
9a8a9d17 | 1978 | iommus = <&apps_smmu 0x740 0>; |
ca4db2b5 MG |
1979 | snps,dis_u2_susphy_quirk; |
1980 | snps,dis_enblslpm_quirk; | |
1981 | phys = <&usb_1_hsphy>, <&usb_1_ssphy>; | |
1982 | phy-names = "usb2-phy", "usb3-phy"; | |
1983 | }; | |
1984 | }; | |
1985 | ||
1986 | usb_2: usb@a8f8800 { | |
1987 | compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; | |
bede7d2d | 1988 | reg = <0 0x0a8f8800 0 0x400>; |
ca4db2b5 | 1989 | status = "disabled"; |
bede7d2d BA |
1990 | #address-cells = <2>; |
1991 | #size-cells = <2>; | |
ca4db2b5 | 1992 | ranges; |
9a8a9d17 | 1993 | dma-ranges; |
ca4db2b5 MG |
1994 | |
1995 | clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, | |
1996 | <&gcc GCC_USB30_SEC_MASTER_CLK>, | |
1997 | <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, | |
1998 | <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, | |
1999 | <&gcc GCC_USB30_SEC_SLEEP_CLK>; | |
2000 | clock-names = "cfg_noc", "core", "iface", "mock_utmi", | |
2001 | "sleep"; | |
2002 | ||
2003 | assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, | |
2004 | <&gcc GCC_USB30_SEC_MASTER_CLK>; | |
2005 | assigned-clock-rates = <19200000>, <150000000>; | |
2006 | ||
2007 | interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, | |
2008 | <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, | |
2009 | <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, | |
2010 | <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; | |
2011 | interrupt-names = "hs_phy_irq", "ss_phy_irq", | |
2012 | "dm_hs_phy_irq", "dp_hs_phy_irq"; | |
2013 | ||
2014 | power-domains = <&gcc USB30_SEC_GDSC>; | |
2015 | ||
2016 | resets = <&gcc GCC_USB30_SEC_BCR>; | |
2017 | ||
2018 | usb_2_dwc3: dwc3@a800000 { | |
2019 | compatible = "snps,dwc3"; | |
bede7d2d | 2020 | reg = <0 0x0a800000 0 0xcd00>; |
ca4db2b5 | 2021 | interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
9a8a9d17 | 2022 | iommus = <&apps_smmu 0x760 0>; |
ca4db2b5 MG |
2023 | snps,dis_u2_susphy_quirk; |
2024 | snps,dis_enblslpm_quirk; | |
2025 | phys = <&usb_2_hsphy>, <&usb_2_ssphy>; | |
2026 | phy-names = "usb2-phy", "usb3-phy"; | |
2027 | }; | |
2028 | }; | |
2029 | ||
05556681 TD |
2030 | videocc: clock-controller@ab00000 { |
2031 | compatible = "qcom,sdm845-videocc"; | |
bede7d2d | 2032 | reg = <0 0x0ab00000 0 0x10000>; |
05556681 TD |
2033 | #clock-cells = <1>; |
2034 | #power-domain-cells = <1>; | |
2035 | #reset-cells = <1>; | |
2036 | }; | |
2037 | ||
08c2a076 JS |
2038 | mdss: mdss@ae00000 { |
2039 | compatible = "qcom,sdm845-mdss"; | |
bede7d2d | 2040 | reg = <0 0x0ae00000 0 0x1000>; |
08c2a076 JS |
2041 | reg-names = "mdss"; |
2042 | ||
2043 | power-domains = <&dispcc MDSS_GDSC>; | |
2044 | ||
2045 | clocks = <&gcc GCC_DISP_AHB_CLK>, | |
2046 | <&gcc GCC_DISP_AXI_CLK>, | |
2047 | <&dispcc DISP_CC_MDSS_MDP_CLK>; | |
2048 | clock-names = "iface", "bus", "core"; | |
2049 | ||
2050 | assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; | |
2051 | assigned-clock-rates = <300000000>; | |
2052 | ||
2053 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; | |
2054 | interrupt-controller; | |
2055 | #interrupt-cells = <1>; | |
2056 | ||
2057 | iommus = <&apps_smmu 0x880 0x8>, | |
2058 | <&apps_smmu 0xc80 0x8>; | |
2059 | ||
2060 | status = "disabled"; | |
2061 | ||
bede7d2d BA |
2062 | #address-cells = <2>; |
2063 | #size-cells = <2>; | |
08c2a076 JS |
2064 | ranges; |
2065 | ||
2066 | mdss_mdp: mdp@ae01000 { | |
2067 | compatible = "qcom,sdm845-dpu"; | |
bede7d2d BA |
2068 | reg = <0 0x0ae01000 0 0x8f000>, |
2069 | <0 0x0aeb0000 0 0x2008>; | |
08c2a076 JS |
2070 | reg-names = "mdp", "vbif"; |
2071 | ||
2072 | clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, | |
2073 | <&dispcc DISP_CC_MDSS_AXI_CLK>, | |
2074 | <&dispcc DISP_CC_MDSS_MDP_CLK>, | |
2075 | <&dispcc DISP_CC_MDSS_VSYNC_CLK>; | |
2076 | clock-names = "iface", "bus", "core", "vsync"; | |
2077 | ||
2078 | assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, | |
2079 | <&dispcc DISP_CC_MDSS_VSYNC_CLK>; | |
2080 | assigned-clock-rates = <300000000>, | |
2081 | <19200000>; | |
2082 | ||
2083 | interrupt-parent = <&mdss>; | |
2084 | interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; | |
2085 | ||
2086 | status = "disabled"; | |
2087 | ||
2088 | ports { | |
2089 | #address-cells = <1>; | |
2090 | #size-cells = <0>; | |
2091 | ||
2092 | port@0 { | |
2093 | reg = <0>; | |
2094 | dpu_intf1_out: endpoint { | |
2095 | remote-endpoint = <&dsi0_in>; | |
2096 | }; | |
2097 | }; | |
2098 | ||
2099 | port@1 { | |
2100 | reg = <1>; | |
2101 | dpu_intf2_out: endpoint { | |
2102 | remote-endpoint = <&dsi1_in>; | |
2103 | }; | |
2104 | }; | |
2105 | }; | |
2106 | }; | |
2107 | ||
2108 | dsi0: dsi@ae94000 { | |
2109 | compatible = "qcom,mdss-dsi-ctrl"; | |
bede7d2d | 2110 | reg = <0 0x0ae94000 0 0x400>; |
08c2a076 JS |
2111 | reg-names = "dsi_ctrl"; |
2112 | ||
2113 | interrupt-parent = <&mdss>; | |
2114 | interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; | |
2115 | ||
2116 | clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, | |
2117 | <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, | |
2118 | <&dispcc DISP_CC_MDSS_PCLK0_CLK>, | |
2119 | <&dispcc DISP_CC_MDSS_ESC0_CLK>, | |
2120 | <&dispcc DISP_CC_MDSS_AHB_CLK>, | |
2121 | <&dispcc DISP_CC_MDSS_AXI_CLK>; | |
2122 | clock-names = "byte", | |
2123 | "byte_intf", | |
2124 | "pixel", | |
2125 | "core", | |
2126 | "iface", | |
2127 | "bus"; | |
2128 | ||
2129 | phys = <&dsi0_phy>; | |
2130 | phy-names = "dsi"; | |
2131 | ||
2132 | status = "disabled"; | |
2133 | ||
2134 | #address-cells = <1>; | |
2135 | #size-cells = <0>; | |
2136 | ||
2137 | ports { | |
2138 | #address-cells = <1>; | |
2139 | #size-cells = <0>; | |
2140 | ||
2141 | port@0 { | |
2142 | reg = <0>; | |
2143 | dsi0_in: endpoint { | |
2144 | remote-endpoint = <&dpu_intf1_out>; | |
2145 | }; | |
2146 | }; | |
2147 | ||
2148 | port@1 { | |
2149 | reg = <1>; | |
2150 | dsi0_out: endpoint { | |
2151 | }; | |
2152 | }; | |
2153 | }; | |
2154 | }; | |
2155 | ||
2156 | dsi0_phy: dsi-phy@ae94400 { | |
2157 | compatible = "qcom,dsi-phy-10nm"; | |
bede7d2d BA |
2158 | reg = <0 0x0ae94400 0 0x200>, |
2159 | <0 0x0ae94600 0 0x280>, | |
2160 | <0 0x0ae94a00 0 0x1e0>; | |
08c2a076 JS |
2161 | reg-names = "dsi_phy", |
2162 | "dsi_phy_lane", | |
2163 | "dsi_pll"; | |
2164 | ||
2165 | #clock-cells = <1>; | |
2166 | #phy-cells = <0>; | |
2167 | ||
0c0e7270 MK |
2168 | clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, |
2169 | <&rpmhcc RPMH_CXO_CLK>; | |
2170 | clock-names = "iface", "ref"; | |
08c2a076 JS |
2171 | |
2172 | status = "disabled"; | |
2173 | }; | |
2174 | ||
2175 | dsi1: dsi@ae96000 { | |
2176 | compatible = "qcom,mdss-dsi-ctrl"; | |
bede7d2d | 2177 | reg = <0 0x0ae96000 0 0x400>; |
08c2a076 JS |
2178 | reg-names = "dsi_ctrl"; |
2179 | ||
2180 | interrupt-parent = <&mdss>; | |
2181 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; | |
2182 | ||
2183 | clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, | |
2184 | <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, | |
2185 | <&dispcc DISP_CC_MDSS_PCLK1_CLK>, | |
2186 | <&dispcc DISP_CC_MDSS_ESC1_CLK>, | |
2187 | <&dispcc DISP_CC_MDSS_AHB_CLK>, | |
2188 | <&dispcc DISP_CC_MDSS_AXI_CLK>; | |
2189 | clock-names = "byte", | |
2190 | "byte_intf", | |
2191 | "pixel", | |
2192 | "core", | |
2193 | "iface", | |
2194 | "bus"; | |
2195 | ||
2196 | phys = <&dsi1_phy>; | |
2197 | phy-names = "dsi"; | |
2198 | ||
2199 | status = "disabled"; | |
2200 | ||
2201 | #address-cells = <1>; | |
2202 | #size-cells = <0>; | |
2203 | ||
2204 | ports { | |
2205 | #address-cells = <1>; | |
2206 | #size-cells = <0>; | |
2207 | ||
2208 | port@0 { | |
2209 | reg = <0>; | |
2210 | dsi1_in: endpoint { | |
2211 | remote-endpoint = <&dpu_intf2_out>; | |
2212 | }; | |
2213 | }; | |
2214 | ||
2215 | port@1 { | |
2216 | reg = <1>; | |
2217 | dsi1_out: endpoint { | |
2218 | }; | |
2219 | }; | |
2220 | }; | |
2221 | }; | |
2222 | ||
2223 | dsi1_phy: dsi-phy@ae96400 { | |
2224 | compatible = "qcom,dsi-phy-10nm"; | |
bede7d2d BA |
2225 | reg = <0 0x0ae96400 0 0x200>, |
2226 | <0 0x0ae96600 0 0x280>, | |
2227 | <0 0x0ae96a00 0 0x10e>; | |
08c2a076 JS |
2228 | reg-names = "dsi_phy", |
2229 | "dsi_phy_lane", | |
2230 | "dsi_pll"; | |
2231 | ||
2232 | #clock-cells = <1>; | |
2233 | #phy-cells = <0>; | |
2234 | ||
0c0e7270 MK |
2235 | clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, |
2236 | <&rpmhcc RPMH_CXO_CLK>; | |
2237 | clock-names = "iface", "ref"; | |
08c2a076 JS |
2238 | |
2239 | status = "disabled"; | |
2240 | }; | |
2241 | }; | |
2242 | ||
c7980010 JC |
2243 | gpu@5000000 { |
2244 | compatible = "qcom,adreno-630.2", "qcom,adreno"; | |
2245 | #stream-id-cells = <16>; | |
2246 | ||
2247 | reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>; | |
2248 | reg-names = "kgsl_3d0_reg_memory", "cx_mem"; | |
2249 | ||
2250 | /* | |
2251 | * Look ma, no clocks! The GPU clocks and power are | |
2252 | * controlled entirely by the GMU | |
2253 | */ | |
2254 | ||
2255 | interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; | |
2256 | ||
2257 | iommus = <&adreno_smmu 0>; | |
2258 | ||
2259 | operating-points-v2 = <&gpu_opp_table>; | |
2260 | ||
2261 | qcom,gmu = <&gmu>; | |
2262 | ||
217073b4 | 2263 | zap_shader: zap-shader { |
3fdeaee9 JC |
2264 | memory-region = <&gpu_mem>; |
2265 | }; | |
2266 | ||
c7980010 JC |
2267 | gpu_opp_table: opp-table { |
2268 | compatible = "operating-points-v2"; | |
2269 | ||
2270 | opp-710000000 { | |
2271 | opp-hz = /bits/ 64 <710000000>; | |
2272 | opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; | |
2273 | }; | |
2274 | ||
2275 | opp-675000000 { | |
2276 | opp-hz = /bits/ 64 <675000000>; | |
2277 | opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; | |
2278 | }; | |
2279 | ||
2280 | opp-596000000 { | |
2281 | opp-hz = /bits/ 64 <596000000>; | |
2282 | opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; | |
2283 | }; | |
2284 | ||
2285 | opp-520000000 { | |
2286 | opp-hz = /bits/ 64 <520000000>; | |
2287 | opp-level = <RPMH_REGULATOR_LEVEL_NOM>; | |
2288 | }; | |
2289 | ||
2290 | opp-414000000 { | |
2291 | opp-hz = /bits/ 64 <414000000>; | |
2292 | opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; | |
2293 | }; | |
2294 | ||
2295 | opp-342000000 { | |
2296 | opp-hz = /bits/ 64 <342000000>; | |
2297 | opp-level = <RPMH_REGULATOR_LEVEL_SVS>; | |
2298 | }; | |
2299 | ||
2300 | opp-257000000 { | |
2301 | opp-hz = /bits/ 64 <257000000>; | |
2302 | opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; | |
2303 | }; | |
2304 | }; | |
2305 | }; | |
2306 | ||
2307 | adreno_smmu: iommu@5040000 { | |
2308 | compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; | |
2309 | reg = <0 0x5040000 0 0x10000>; | |
2310 | #iommu-cells = <1>; | |
2311 | #global-interrupts = <2>; | |
2312 | interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, | |
2313 | <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, | |
2314 | <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, | |
2315 | <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, | |
2316 | <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, | |
2317 | <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, | |
2318 | <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, | |
2319 | <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, | |
2320 | <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, | |
2321 | <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; | |
2322 | clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, | |
2323 | <&gcc GCC_GPU_CFG_AHB_CLK>; | |
2324 | clock-names = "bus", "iface"; | |
2325 | ||
2326 | power-domains = <&gpucc GPU_CX_GDSC>; | |
2327 | }; | |
2328 | ||
2329 | gmu: gmu@506a000 { | |
2330 | compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; | |
2331 | ||
2332 | reg = <0 0x506a000 0 0x30000>, | |
2333 | <0 0xb280000 0 0x10000>, | |
2334 | <0 0xb480000 0 0x10000>; | |
2335 | reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; | |
2336 | ||
2337 | interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, | |
2338 | <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; | |
2339 | interrupt-names = "hfi", "gmu"; | |
2340 | ||
2341 | clocks = <&gpucc GPU_CC_CX_GMU_CLK>, | |
2342 | <&gpucc GPU_CC_CXO_CLK>, | |
2343 | <&gcc GCC_DDRSS_GPU_AXI_CLK>, | |
2344 | <&gcc GCC_GPU_MEMNOC_GFX_CLK>; | |
2345 | clock-names = "gmu", "cxo", "axi", "memnoc"; | |
2346 | ||
2347 | power-domains = <&gpucc GPU_CX_GDSC>, | |
2348 | <&gpucc GPU_GX_GDSC>; | |
2349 | power-domain-names = "cx", "gx"; | |
2350 | ||
2351 | iommus = <&adreno_smmu 5>; | |
2352 | ||
2353 | operating-points-v2 = <&gmu_opp_table>; | |
2354 | ||
2355 | gmu_opp_table: opp-table { | |
2356 | compatible = "operating-points-v2"; | |
2357 | ||
2358 | opp-400000000 { | |
2359 | opp-hz = /bits/ 64 <400000000>; | |
2360 | opp-level = <RPMH_REGULATOR_LEVEL_SVS>; | |
2361 | }; | |
2362 | ||
2363 | opp-200000000 { | |
2364 | opp-hz = /bits/ 64 <200000000>; | |
2365 | opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; | |
2366 | }; | |
2367 | }; | |
2368 | }; | |
2369 | ||
40019e84 MK |
2370 | dispcc: clock-controller@af00000 { |
2371 | compatible = "qcom,sdm845-dispcc"; | |
bede7d2d | 2372 | reg = <0 0x0af00000 0 0x10000>; |
40019e84 MK |
2373 | #clock-cells = <1>; |
2374 | #reset-cells = <1>; | |
2375 | #power-domain-cells = <1>; | |
2376 | }; | |
2377 | ||
13393da0 SS |
2378 | pdc_reset: reset-controller@b2e0000 { |
2379 | compatible = "qcom,sdm845-pdc-global"; | |
bede7d2d | 2380 | reg = <0 0x0b2e0000 0 0x20000>; |
13393da0 SS |
2381 | #reset-cells = <1>; |
2382 | }; | |
2383 | ||
cda676b5 AK |
2384 | tsens0: thermal-sensor@c263000 { |
2385 | compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; | |
bede7d2d BA |
2386 | reg = <0 0x0c263000 0 0x1ff>, /* TM */ |
2387 | <0 0x0c222000 0 0x1ff>; /* SROT */ | |
cda676b5 AK |
2388 | #qcom,sensors = <13>; |
2389 | #thermal-sensor-cells = <1>; | |
2390 | }; | |
2391 | ||
2392 | tsens1: thermal-sensor@c265000 { | |
2393 | compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; | |
bede7d2d BA |
2394 | reg = <0 0x0c265000 0 0x1ff>, /* TM */ |
2395 | <0 0x0c223000 0 0x1ff>; /* SROT */ | |
cda676b5 AK |
2396 | #qcom,sensors = <8>; |
2397 | #thermal-sensor-cells = <1>; | |
2398 | }; | |
2399 | ||
ead5eea3 SS |
2400 | aoss_reset: reset-controller@c2a0000 { |
2401 | compatible = "qcom,sdm845-aoss-cc"; | |
bede7d2d | 2402 | reg = <0 0x0c2a0000 0 0x31000>; |
ead5eea3 SS |
2403 | #reset-cells = <1>; |
2404 | }; | |
2405 | ||
a7977438 BA |
2406 | aoss_qmp: qmp@c300000 { |
2407 | compatible = "qcom,sdm845-aoss-qmp"; | |
2408 | reg = <0 0x0c300000 0 0x100000>; | |
2409 | interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; | |
2410 | mboxes = <&apss_shared 0>; | |
2411 | ||
2412 | #clock-cells = <0>; | |
2413 | #power-domain-cells = <1>; | |
2414 | }; | |
2415 | ||
54d7a20d DA |
2416 | spmi_bus: spmi@c440000 { |
2417 | compatible = "qcom,spmi-pmic-arb"; | |
bede7d2d BA |
2418 | reg = <0 0x0c440000 0 0x1100>, |
2419 | <0 0x0c600000 0 0x2000000>, | |
2420 | <0 0x0e600000 0 0x100000>, | |
2421 | <0 0x0e700000 0 0xa0000>, | |
2422 | <0 0x0c40a000 0 0x26000>; | |
54d7a20d DA |
2423 | reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; |
2424 | interrupt-names = "periph_irq"; | |
2425 | interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; | |
2426 | qcom,ee = <0>; | |
2427 | qcom,channel = <0>; | |
2428 | #address-cells = <2>; | |
2429 | #size-cells = <0>; | |
2430 | interrupt-controller; | |
2431 | #interrupt-cells = <4>; | |
2432 | cell-index = <0>; | |
2433 | }; | |
2434 | ||
4429e575 VG |
2435 | apps_smmu: iommu@15000000 { |
2436 | compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; | |
bede7d2d | 2437 | reg = <0 0x15000000 0 0x80000>; |
4429e575 VG |
2438 | #iommu-cells = <2>; |
2439 | #global-interrupts = <1>; | |
2440 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, | |
2441 | <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, | |
2442 | <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, | |
2443 | <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, | |
2444 | <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, | |
2445 | <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, | |
2446 | <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, | |
2447 | <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, | |
2448 | <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, | |
2449 | <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, | |
2450 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, | |
2451 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, | |
2452 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, | |
2453 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, | |
2454 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
2455 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
2456 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, | |
2457 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, | |
2458 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, | |
2459 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, | |
2460 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, | |
2461 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, | |
2462 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
2463 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
2464 | <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, | |
2465 | <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, | |
2466 | <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, | |
2467 | <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, | |
2468 | <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, | |
2469 | <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, | |
2470 | <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, | |
2471 | <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, | |
2472 | <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, | |
2473 | <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, | |
2474 | <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, | |
2475 | <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, | |
2476 | <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, | |
2477 | <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, | |
2478 | <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, | |
2479 | <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, | |
2480 | <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, | |
2481 | <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, | |
2482 | <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, | |
2483 | <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, | |
2484 | <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, | |
2485 | <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, | |
2486 | <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, | |
2487 | <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, | |
2488 | <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, | |
2489 | <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, | |
2490 | <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, | |
2491 | <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, | |
2492 | <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, | |
2493 | <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, | |
2494 | <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, | |
2495 | <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, | |
2496 | <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, | |
2497 | <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, | |
2498 | <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, | |
2499 | <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, | |
2500 | <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, | |
2501 | <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, | |
2502 | <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, | |
2503 | <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, | |
2504 | <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; | |
2505 | }; | |
2506 | ||
0cef5dd4 TD |
2507 | lpasscc: clock-controller@17014000 { |
2508 | compatible = "qcom,sdm845-lpasscc"; | |
1d918e9a | 2509 | reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; |
0cef5dd4 TD |
2510 | reg-names = "cc", "qdsp6ss"; |
2511 | #clock-cells = <1>; | |
2512 | status = "disabled"; | |
2513 | }; | |
2514 | ||
54d7a20d DA |
2515 | apss_shared: mailbox@17990000 { |
2516 | compatible = "qcom,sdm845-apss-shared"; | |
bede7d2d | 2517 | reg = <0 0x17990000 0 0x1000>; |
54d7a20d DA |
2518 | #mbox-cells = <1>; |
2519 | }; | |
2520 | ||
c83545d9 DA |
2521 | apps_rsc: rsc@179c0000 { |
2522 | label = "apps_rsc"; | |
2523 | compatible = "qcom,rpmh-rsc"; | |
bede7d2d BA |
2524 | reg = <0 0x179c0000 0 0x10000>, |
2525 | <0 0x179d0000 0 0x10000>, | |
2526 | <0 0x179e0000 0 0x10000>; | |
c83545d9 DA |
2527 | reg-names = "drv-0", "drv-1", "drv-2"; |
2528 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, | |
2529 | <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, | |
2530 | <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
2531 | qcom,tcs-offset = <0xd00>; | |
2532 | qcom,drv-id = <2>; | |
2533 | qcom,tcs-config = <ACTIVE_TCS 2>, | |
2534 | <SLEEP_TCS 3>, | |
2535 | <WAKE_TCS 3>, | |
2536 | <CONTROL_TCS 1>; | |
717f2013 DA |
2537 | |
2538 | rpmhcc: clock-controller { | |
2539 | compatible = "qcom,sdm845-rpmh-clk"; | |
2540 | #clock-cells = <1>; | |
2541 | }; | |
5b6f186f RN |
2542 | |
2543 | rpmhpd: power-controller { | |
2544 | compatible = "qcom,sdm845-rpmhpd"; | |
2545 | #power-domain-cells = <1>; | |
2546 | operating-points-v2 = <&rpmhpd_opp_table>; | |
2547 | ||
2548 | rpmhpd_opp_table: opp-table { | |
2549 | compatible = "operating-points-v2"; | |
2550 | ||
2551 | rpmhpd_opp_ret: opp1 { | |
596a4343 | 2552 | opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; |
5b6f186f RN |
2553 | }; |
2554 | ||
2555 | rpmhpd_opp_min_svs: opp2 { | |
596a4343 | 2556 | opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; |
5b6f186f RN |
2557 | }; |
2558 | ||
2559 | rpmhpd_opp_low_svs: opp3 { | |
596a4343 | 2560 | opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; |
5b6f186f RN |
2561 | }; |
2562 | ||
2563 | rpmhpd_opp_svs: opp4 { | |
596a4343 | 2564 | opp-level = <RPMH_REGULATOR_LEVEL_SVS>; |
5b6f186f RN |
2565 | }; |
2566 | ||
2567 | rpmhpd_opp_svs_l1: opp5 { | |
596a4343 | 2568 | opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; |
5b6f186f RN |
2569 | }; |
2570 | ||
2571 | rpmhpd_opp_nom: opp6 { | |
596a4343 | 2572 | opp-level = <RPMH_REGULATOR_LEVEL_NOM>; |
5b6f186f RN |
2573 | }; |
2574 | ||
2575 | rpmhpd_opp_nom_l1: opp7 { | |
596a4343 | 2576 | opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; |
5b6f186f RN |
2577 | }; |
2578 | ||
2579 | rpmhpd_opp_nom_l2: opp8 { | |
596a4343 | 2580 | opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; |
5b6f186f RN |
2581 | }; |
2582 | ||
2583 | rpmhpd_opp_turbo: opp9 { | |
596a4343 | 2584 | opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; |
5b6f186f RN |
2585 | }; |
2586 | ||
2587 | rpmhpd_opp_turbo_l1: opp10 { | |
596a4343 | 2588 | opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; |
5b6f186f RN |
2589 | }; |
2590 | }; | |
2591 | }; | |
5e820489 DD |
2592 | |
2593 | rsc_hlos: interconnect { | |
2594 | compatible = "qcom,sdm845-rsc-hlos"; | |
2595 | #interconnect-cells = <1>; | |
2596 | }; | |
c83545d9 DA |
2597 | }; |
2598 | ||
6d4cf750 RN |
2599 | intc: interrupt-controller@17a00000 { |
2600 | compatible = "arm,gic-v3"; | |
bede7d2d BA |
2601 | #address-cells = <2>; |
2602 | #size-cells = <2>; | |
6d4cf750 RN |
2603 | ranges; |
2604 | #interrupt-cells = <3>; | |
2605 | interrupt-controller; | |
bede7d2d BA |
2606 | reg = <0 0x17a00000 0 0x10000>, /* GICD */ |
2607 | <0 0x17a60000 0 0x100000>; /* GICR * 8 */ | |
6d4cf750 RN |
2608 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
2609 | ||
2610 | gic-its@17a40000 { | |
2611 | compatible = "arm,gic-v3-its"; | |
2612 | msi-controller; | |
2613 | #msi-cells = <1>; | |
bede7d2d | 2614 | reg = <0 0x17a40000 0 0x20000>; |
6d4cf750 RN |
2615 | status = "disabled"; |
2616 | }; | |
2617 | }; | |
2618 | ||
6d4cf750 | 2619 | timer@17c90000 { |
bede7d2d BA |
2620 | #address-cells = <2>; |
2621 | #size-cells = <2>; | |
6d4cf750 RN |
2622 | ranges; |
2623 | compatible = "arm,armv7-timer-mem"; | |
bede7d2d | 2624 | reg = <0 0x17c90000 0 0x1000>; |
6d4cf750 RN |
2625 | |
2626 | frame@17ca0000 { | |
2627 | frame-number = <0>; | |
2628 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, | |
2629 | <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
bede7d2d BA |
2630 | reg = <0 0x17ca0000 0 0x1000>, |
2631 | <0 0x17cb0000 0 0x1000>; | |
6d4cf750 RN |
2632 | }; |
2633 | ||
2634 | frame@17cc0000 { | |
2635 | frame-number = <1>; | |
2636 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
bede7d2d | 2637 | reg = <0 0x17cc0000 0 0x1000>; |
6d4cf750 RN |
2638 | status = "disabled"; |
2639 | }; | |
2640 | ||
2641 | frame@17cd0000 { | |
2642 | frame-number = <2>; | |
2643 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
bede7d2d | 2644 | reg = <0 0x17cd0000 0 0x1000>; |
6d4cf750 RN |
2645 | status = "disabled"; |
2646 | }; | |
2647 | ||
2648 | frame@17ce0000 { | |
2649 | frame-number = <3>; | |
2650 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
bede7d2d | 2651 | reg = <0 0x17ce0000 0 0x1000>; |
6d4cf750 RN |
2652 | status = "disabled"; |
2653 | }; | |
2654 | ||
2655 | frame@17cf0000 { | |
2656 | frame-number = <4>; | |
2657 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
bede7d2d | 2658 | reg = <0 0x17cf0000 0 0x1000>; |
6d4cf750 RN |
2659 | status = "disabled"; |
2660 | }; | |
2661 | ||
2662 | frame@17d00000 { | |
2663 | frame-number = <5>; | |
2664 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; | |
bede7d2d | 2665 | reg = <0 0x17d00000 0 0x1000>; |
6d4cf750 RN |
2666 | status = "disabled"; |
2667 | }; | |
2668 | ||
2669 | frame@17d10000 { | |
2670 | frame-number = <6>; | |
2671 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; | |
bede7d2d | 2672 | reg = <0 0x17d10000 0 0x1000>; |
6d4cf750 RN |
2673 | status = "disabled"; |
2674 | }; | |
2675 | }; | |
c604b82a TD |
2676 | |
2677 | cpufreq_hw: cpufreq@17d43000 { | |
2678 | compatible = "qcom,cpufreq-hw"; | |
bede7d2d | 2679 | reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; |
c604b82a TD |
2680 | reg-names = "freq-domain0", "freq-domain1"; |
2681 | ||
2682 | clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; | |
2683 | clock-names = "xo", "alternate"; | |
2684 | ||
2685 | #freq-domain-cells = <1>; | |
2686 | }; | |
022bccb8 GS |
2687 | |
2688 | wifi: wifi@18800000 { | |
2689 | compatible = "qcom,wcn3990-wifi"; | |
2690 | status = "disabled"; | |
bede7d2d | 2691 | reg = <0 0x18800000 0 0x800000>; |
022bccb8 GS |
2692 | reg-names = "membase"; |
2693 | memory-region = <&wlan_msa_mem>; | |
bc94e5f4 DA |
2694 | clock-names = "cxo_ref_clk_pin"; |
2695 | clocks = <&rpmhcc RPMH_RF_CLK2>; | |
022bccb8 GS |
2696 | interrupts = |
2697 | <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, | |
2698 | <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, | |
2699 | <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, | |
2700 | <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, | |
2701 | <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, | |
2702 | <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, | |
2703 | <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, | |
2704 | <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, | |
2705 | <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, | |
2706 | <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, | |
2707 | <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, | |
2708 | <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; | |
bc94e5f4 | 2709 | iommus = <&apps_smmu 0x0040 0x1>; |
022bccb8 | 2710 | }; |
6d4cf750 | 2711 | }; |
4884788b AK |
2712 | |
2713 | thermal-zones { | |
2714 | cpu0-thermal { | |
2715 | polling-delay-passive = <250>; | |
2716 | polling-delay = <1000>; | |
2717 | ||
2718 | thermal-sensors = <&tsens0 1>; | |
2719 | ||
2720 | trips { | |
c47fc198 AK |
2721 | cpu0_alert0: trip-point@0 { |
2722 | temperature = <90000>; | |
2723 | hysteresis = <2000>; | |
2724 | type = "passive"; | |
2725 | }; | |
2726 | ||
2727 | cpu0_alert1: trip-point@1 { | |
2728 | temperature = <95000>; | |
4884788b AK |
2729 | hysteresis = <2000>; |
2730 | type = "passive"; | |
2731 | }; | |
2732 | ||
c47fc198 | 2733 | cpu0_crit: cpu_crit { |
4884788b AK |
2734 | temperature = <110000>; |
2735 | hysteresis = <1000>; | |
2736 | type = "critical"; | |
2737 | }; | |
2738 | }; | |
c47fc198 AK |
2739 | |
2740 | cooling-maps { | |
2741 | map0 { | |
2742 | trip = <&cpu0_alert0>; | |
2743 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2744 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2745 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2746 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
2747 | }; | |
2748 | map1 { | |
2749 | trip = <&cpu0_alert1>; | |
2750 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2751 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2752 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2753 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
2754 | }; | |
2755 | }; | |
4884788b AK |
2756 | }; |
2757 | ||
2758 | cpu1-thermal { | |
2759 | polling-delay-passive = <250>; | |
2760 | polling-delay = <1000>; | |
2761 | ||
2762 | thermal-sensors = <&tsens0 2>; | |
2763 | ||
2764 | trips { | |
c47fc198 AK |
2765 | cpu1_alert0: trip-point@0 { |
2766 | temperature = <90000>; | |
4884788b AK |
2767 | hysteresis = <2000>; |
2768 | type = "passive"; | |
2769 | }; | |
2770 | ||
c47fc198 AK |
2771 | cpu1_alert1: trip-point@1 { |
2772 | temperature = <95000>; | |
2773 | hysteresis = <2000>; | |
2774 | type = "passive"; | |
2775 | }; | |
2776 | ||
2777 | cpu1_crit: cpu_crit { | |
4884788b AK |
2778 | temperature = <110000>; |
2779 | hysteresis = <1000>; | |
2780 | type = "critical"; | |
2781 | }; | |
2782 | }; | |
c47fc198 AK |
2783 | |
2784 | cooling-maps { | |
2785 | map0 { | |
2786 | trip = <&cpu1_alert0>; | |
2787 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2788 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2789 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2790 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
2791 | }; | |
2792 | map1 { | |
2793 | trip = <&cpu1_alert1>; | |
2794 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2795 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2796 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2797 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
2798 | }; | |
2799 | }; | |
4884788b AK |
2800 | }; |
2801 | ||
2802 | cpu2-thermal { | |
2803 | polling-delay-passive = <250>; | |
2804 | polling-delay = <1000>; | |
2805 | ||
2806 | thermal-sensors = <&tsens0 3>; | |
2807 | ||
2808 | trips { | |
c47fc198 AK |
2809 | cpu2_alert0: trip-point@0 { |
2810 | temperature = <90000>; | |
4884788b AK |
2811 | hysteresis = <2000>; |
2812 | type = "passive"; | |
2813 | }; | |
2814 | ||
c47fc198 AK |
2815 | cpu2_alert1: trip-point@1 { |
2816 | temperature = <95000>; | |
2817 | hysteresis = <2000>; | |
2818 | type = "passive"; | |
2819 | }; | |
2820 | ||
2821 | cpu2_crit: cpu_crit { | |
4884788b AK |
2822 | temperature = <110000>; |
2823 | hysteresis = <1000>; | |
2824 | type = "critical"; | |
2825 | }; | |
2826 | }; | |
c47fc198 AK |
2827 | |
2828 | cooling-maps { | |
2829 | map0 { | |
2830 | trip = <&cpu2_alert0>; | |
2831 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2832 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2833 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2834 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
2835 | }; | |
2836 | map1 { | |
2837 | trip = <&cpu2_alert1>; | |
2838 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2839 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2840 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2841 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
2842 | }; | |
2843 | }; | |
4884788b AK |
2844 | }; |
2845 | ||
2846 | cpu3-thermal { | |
2847 | polling-delay-passive = <250>; | |
2848 | polling-delay = <1000>; | |
2849 | ||
2850 | thermal-sensors = <&tsens0 4>; | |
2851 | ||
2852 | trips { | |
c47fc198 AK |
2853 | cpu3_alert0: trip-point@0 { |
2854 | temperature = <90000>; | |
4884788b AK |
2855 | hysteresis = <2000>; |
2856 | type = "passive"; | |
2857 | }; | |
2858 | ||
c47fc198 AK |
2859 | cpu3_alert1: trip-point@1 { |
2860 | temperature = <95000>; | |
2861 | hysteresis = <2000>; | |
2862 | type = "passive"; | |
2863 | }; | |
2864 | ||
2865 | cpu3_crit: cpu_crit { | |
4884788b AK |
2866 | temperature = <110000>; |
2867 | hysteresis = <1000>; | |
2868 | type = "critical"; | |
2869 | }; | |
2870 | }; | |
c47fc198 AK |
2871 | |
2872 | cooling-maps { | |
2873 | map0 { | |
2874 | trip = <&cpu3_alert0>; | |
2875 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2876 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2877 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2878 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
2879 | }; | |
2880 | map1 { | |
2881 | trip = <&cpu3_alert1>; | |
2882 | cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2883 | <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2884 | <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2885 | <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
2886 | }; | |
2887 | }; | |
4884788b AK |
2888 | }; |
2889 | ||
2890 | cpu4-thermal { | |
2891 | polling-delay-passive = <250>; | |
2892 | polling-delay = <1000>; | |
2893 | ||
2894 | thermal-sensors = <&tsens0 7>; | |
2895 | ||
2896 | trips { | |
c47fc198 AK |
2897 | cpu4_alert0: trip-point@0 { |
2898 | temperature = <90000>; | |
4884788b AK |
2899 | hysteresis = <2000>; |
2900 | type = "passive"; | |
2901 | }; | |
2902 | ||
c47fc198 AK |
2903 | cpu4_alert1: trip-point@1 { |
2904 | temperature = <95000>; | |
2905 | hysteresis = <2000>; | |
2906 | type = "passive"; | |
2907 | }; | |
2908 | ||
2909 | cpu4_crit: cpu_crit { | |
4884788b AK |
2910 | temperature = <110000>; |
2911 | hysteresis = <1000>; | |
2912 | type = "critical"; | |
2913 | }; | |
2914 | }; | |
c47fc198 AK |
2915 | |
2916 | cooling-maps { | |
2917 | map0 { | |
2918 | trip = <&cpu4_alert0>; | |
2919 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2920 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2921 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2922 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
2923 | }; | |
2924 | map1 { | |
2925 | trip = <&cpu4_alert1>; | |
2926 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2927 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2928 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2929 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
2930 | }; | |
2931 | }; | |
4884788b AK |
2932 | }; |
2933 | ||
2934 | cpu5-thermal { | |
2935 | polling-delay-passive = <250>; | |
2936 | polling-delay = <1000>; | |
2937 | ||
2938 | thermal-sensors = <&tsens0 8>; | |
2939 | ||
2940 | trips { | |
c47fc198 AK |
2941 | cpu5_alert0: trip-point@0 { |
2942 | temperature = <90000>; | |
4884788b AK |
2943 | hysteresis = <2000>; |
2944 | type = "passive"; | |
2945 | }; | |
2946 | ||
c47fc198 AK |
2947 | cpu5_alert1: trip-point@1 { |
2948 | temperature = <95000>; | |
2949 | hysteresis = <2000>; | |
2950 | type = "passive"; | |
2951 | }; | |
2952 | ||
2953 | cpu5_crit: cpu_crit { | |
4884788b AK |
2954 | temperature = <110000>; |
2955 | hysteresis = <1000>; | |
2956 | type = "critical"; | |
2957 | }; | |
2958 | }; | |
c47fc198 AK |
2959 | |
2960 | cooling-maps { | |
2961 | map0 { | |
2962 | trip = <&cpu5_alert0>; | |
2963 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2964 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2965 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2966 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
2967 | }; | |
2968 | map1 { | |
2969 | trip = <&cpu5_alert1>; | |
2970 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2971 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2972 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
2973 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
2974 | }; | |
2975 | }; | |
4884788b AK |
2976 | }; |
2977 | ||
2978 | cpu6-thermal { | |
2979 | polling-delay-passive = <250>; | |
2980 | polling-delay = <1000>; | |
2981 | ||
2982 | thermal-sensors = <&tsens0 9>; | |
2983 | ||
2984 | trips { | |
c47fc198 AK |
2985 | cpu6_alert0: trip-point@0 { |
2986 | temperature = <90000>; | |
4884788b AK |
2987 | hysteresis = <2000>; |
2988 | type = "passive"; | |
2989 | }; | |
2990 | ||
c47fc198 AK |
2991 | cpu6_alert1: trip-point@1 { |
2992 | temperature = <95000>; | |
2993 | hysteresis = <2000>; | |
2994 | type = "passive"; | |
2995 | }; | |
2996 | ||
2997 | cpu6_crit: cpu_crit { | |
4884788b AK |
2998 | temperature = <110000>; |
2999 | hysteresis = <1000>; | |
3000 | type = "critical"; | |
3001 | }; | |
3002 | }; | |
c47fc198 AK |
3003 | |
3004 | cooling-maps { | |
3005 | map0 { | |
3006 | trip = <&cpu6_alert0>; | |
3007 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3008 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3009 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3010 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3011 | }; | |
3012 | map1 { | |
3013 | trip = <&cpu6_alert1>; | |
3014 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3015 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3016 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3017 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3018 | }; | |
3019 | }; | |
4884788b AK |
3020 | }; |
3021 | ||
3022 | cpu7-thermal { | |
3023 | polling-delay-passive = <250>; | |
3024 | polling-delay = <1000>; | |
3025 | ||
3026 | thermal-sensors = <&tsens0 10>; | |
3027 | ||
3028 | trips { | |
c47fc198 AK |
3029 | cpu7_alert0: trip-point@0 { |
3030 | temperature = <90000>; | |
4884788b AK |
3031 | hysteresis = <2000>; |
3032 | type = "passive"; | |
3033 | }; | |
3034 | ||
c47fc198 AK |
3035 | cpu7_alert1: trip-point@1 { |
3036 | temperature = <95000>; | |
3037 | hysteresis = <2000>; | |
3038 | type = "passive"; | |
3039 | }; | |
3040 | ||
3041 | cpu7_crit: cpu_crit { | |
4884788b AK |
3042 | temperature = <110000>; |
3043 | hysteresis = <1000>; | |
3044 | type = "critical"; | |
3045 | }; | |
3046 | }; | |
c47fc198 AK |
3047 | |
3048 | cooling-maps { | |
3049 | map0 { | |
3050 | trip = <&cpu7_alert0>; | |
3051 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3052 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3053 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3054 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3055 | }; | |
3056 | map1 { | |
3057 | trip = <&cpu7_alert1>; | |
3058 | cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3059 | <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3060 | <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, | |
3061 | <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
3062 | }; | |
3063 | }; | |
4884788b | 3064 | }; |
1c403ec2 AK |
3065 | |
3066 | aoss0-thermal { | |
3067 | polling-delay-passive = <250>; | |
3068 | polling-delay = <1000>; | |
3069 | ||
3070 | thermal-sensors = <&tsens0 0>; | |
3071 | ||
3072 | trips { | |
3073 | aoss0_alert0: trip-point@0 { | |
3074 | temperature = <90000>; | |
3075 | hysteresis = <2000>; | |
3076 | type = "hot"; | |
3077 | }; | |
3078 | }; | |
3079 | }; | |
3080 | ||
3081 | cluster0-thermal { | |
3082 | polling-delay-passive = <250>; | |
3083 | polling-delay = <1000>; | |
3084 | ||
3085 | thermal-sensors = <&tsens0 5>; | |
3086 | ||
3087 | trips { | |
3088 | cluster0_alert0: trip-point@0 { | |
3089 | temperature = <90000>; | |
3090 | hysteresis = <2000>; | |
3091 | type = "hot"; | |
3092 | }; | |
3093 | cluster0_crit: cluster0_crit { | |
3094 | temperature = <110000>; | |
3095 | hysteresis = <2000>; | |
3096 | type = "critical"; | |
3097 | }; | |
3098 | }; | |
3099 | }; | |
3100 | ||
3101 | cluster1-thermal { | |
3102 | polling-delay-passive = <250>; | |
3103 | polling-delay = <1000>; | |
3104 | ||
3105 | thermal-sensors = <&tsens0 6>; | |
3106 | ||
3107 | trips { | |
3108 | cluster1_alert0: trip-point@0 { | |
3109 | temperature = <90000>; | |
3110 | hysteresis = <2000>; | |
3111 | type = "hot"; | |
3112 | }; | |
3113 | cluster1_crit: cluster1_crit { | |
3114 | temperature = <110000>; | |
3115 | hysteresis = <2000>; | |
3116 | type = "critical"; | |
3117 | }; | |
3118 | }; | |
3119 | }; | |
3120 | ||
3121 | gpu-thermal-top { | |
3122 | polling-delay-passive = <250>; | |
3123 | polling-delay = <1000>; | |
3124 | ||
3125 | thermal-sensors = <&tsens0 11>; | |
3126 | ||
3127 | trips { | |
3128 | gpu1_alert0: trip-point@0 { | |
3129 | temperature = <90000>; | |
3130 | hysteresis = <2000>; | |
3131 | type = "hot"; | |
3132 | }; | |
3133 | }; | |
3134 | }; | |
3135 | ||
3136 | gpu-thermal-bottom { | |
3137 | polling-delay-passive = <250>; | |
3138 | polling-delay = <1000>; | |
3139 | ||
3140 | thermal-sensors = <&tsens0 12>; | |
3141 | ||
3142 | trips { | |
3143 | gpu2_alert0: trip-point@0 { | |
3144 | temperature = <90000>; | |
3145 | hysteresis = <2000>; | |
3146 | type = "hot"; | |
3147 | }; | |
3148 | }; | |
3149 | }; | |
3150 | ||
3151 | aoss1-thermal { | |
3152 | polling-delay-passive = <250>; | |
3153 | polling-delay = <1000>; | |
3154 | ||
3155 | thermal-sensors = <&tsens1 0>; | |
3156 | ||
3157 | trips { | |
3158 | aoss1_alert0: trip-point@0 { | |
3159 | temperature = <90000>; | |
3160 | hysteresis = <2000>; | |
3161 | type = "hot"; | |
3162 | }; | |
3163 | }; | |
3164 | }; | |
3165 | ||
3166 | q6-modem-thermal { | |
3167 | polling-delay-passive = <250>; | |
3168 | polling-delay = <1000>; | |
3169 | ||
3170 | thermal-sensors = <&tsens1 1>; | |
3171 | ||
3172 | trips { | |
3173 | q6_modem_alert0: trip-point@0 { | |
3174 | temperature = <90000>; | |
3175 | hysteresis = <2000>; | |
3176 | type = "hot"; | |
3177 | }; | |
3178 | }; | |
3179 | }; | |
3180 | ||
3181 | mem-thermal { | |
3182 | polling-delay-passive = <250>; | |
3183 | polling-delay = <1000>; | |
3184 | ||
3185 | thermal-sensors = <&tsens1 2>; | |
3186 | ||
3187 | trips { | |
3188 | mem_alert0: trip-point@0 { | |
3189 | temperature = <90000>; | |
3190 | hysteresis = <2000>; | |
3191 | type = "hot"; | |
3192 | }; | |
3193 | }; | |
3194 | }; | |
3195 | ||
3196 | wlan-thermal { | |
3197 | polling-delay-passive = <250>; | |
3198 | polling-delay = <1000>; | |
3199 | ||
3200 | thermal-sensors = <&tsens1 3>; | |
3201 | ||
3202 | trips { | |
3203 | wlan_alert0: trip-point@0 { | |
3204 | temperature = <90000>; | |
3205 | hysteresis = <2000>; | |
3206 | type = "hot"; | |
3207 | }; | |
3208 | }; | |
3209 | }; | |
3210 | ||
3211 | q6-hvx-thermal { | |
3212 | polling-delay-passive = <250>; | |
3213 | polling-delay = <1000>; | |
3214 | ||
3215 | thermal-sensors = <&tsens1 4>; | |
3216 | ||
3217 | trips { | |
3218 | q6_hvx_alert0: trip-point@0 { | |
3219 | temperature = <90000>; | |
3220 | hysteresis = <2000>; | |
3221 | type = "hot"; | |
3222 | }; | |
3223 | }; | |
3224 | }; | |
3225 | ||
3226 | camera-thermal { | |
3227 | polling-delay-passive = <250>; | |
3228 | polling-delay = <1000>; | |
3229 | ||
3230 | thermal-sensors = <&tsens1 5>; | |
3231 | ||
3232 | trips { | |
3233 | camera_alert0: trip-point@0 { | |
3234 | temperature = <90000>; | |
3235 | hysteresis = <2000>; | |
3236 | type = "hot"; | |
3237 | }; | |
3238 | }; | |
3239 | }; | |
3240 | ||
3241 | video-thermal { | |
3242 | polling-delay-passive = <250>; | |
3243 | polling-delay = <1000>; | |
3244 | ||
3245 | thermal-sensors = <&tsens1 6>; | |
3246 | ||
3247 | trips { | |
3248 | video_alert0: trip-point@0 { | |
3249 | temperature = <90000>; | |
3250 | hysteresis = <2000>; | |
3251 | type = "hot"; | |
3252 | }; | |
3253 | }; | |
3254 | }; | |
3255 | ||
3256 | modem-thermal { | |
3257 | polling-delay-passive = <250>; | |
3258 | polling-delay = <1000>; | |
3259 | ||
3260 | thermal-sensors = <&tsens1 7>; | |
3261 | ||
3262 | trips { | |
3263 | modem_alert0: trip-point@0 { | |
3264 | temperature = <90000>; | |
3265 | hysteresis = <2000>; | |
3266 | type = "hot"; | |
3267 | }; | |
3268 | }; | |
3269 | }; | |
4884788b | 3270 | }; |
6d4cf750 | 3271 | }; |