[mirror_ubuntu-focal-kernel.git] / arch / arm64 / boot / dts / renesas / r8a774a1.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the r8a774a1 SoC
 *
 * Copyright (C) 2018 Renesas Electronics Corp.
 */

#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/renesas-cpg-mssr.h>

/ {
	compatible = "renesas,r8a774a1";
	#address-cells = <2>;
	#size-cells = <2>;

	/*
	 * The external audio clocks are configured as 0 Hz fixed frequency
	 * clocks by default.
	 * Boards that provide audio clocks should override them.
	 */
	audio_clk_a: audio_clk_a {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	audio_clk_b: audio_clk_b {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	audio_clk_c: audio_clk_c {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	/* External CAN clock - to be overridden by boards that provide it */
	can_clk: can {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		a57_0: cpu@0 {
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0x0>;
			device_type = "cpu";
			power-domains = <&sysc 0>;
			next-level-cache = <&L2_CA57>;
			enable-method = "psci";
			clocks =<&cpg CPG_CORE 0>;
		};

		a57_1: cpu@1 {
			compatible = "arm,cortex-a57", "arm,armv8";
			reg = <0x1>;
			device_type = "cpu";
			power-domains = <&sysc 1>;
			next-level-cache = <&L2_CA57>;
			enable-method = "psci";
			clocks =<&cpg CPG_CORE 0>;
		};

		L2_CA57: cache-controller-0 {
			compatible = "cache";
			power-domains = <&sysc 12>;
			cache-unified;
			cache-level = <2>;
		};
	};

	extal_clk: extal {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board */
		clock-frequency = <0>;
	};

	extalr_clk: extalr {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board */
		clock-frequency = <0>;
	};

	/* External PCIe clock - can be overridden by the board */
	pcie_bus_clk: pcie_bus {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	pmu_a57 {
		compatible = "arm,cortex-a57-pmu";
		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
				      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&a57_0>, <&a57_1>;
	};

	psci {
		compatible = "arm,psci-1.0", "arm,psci-0.2";
		method = "smc";
	};

	/* External SCIF clock - to be overridden by boards that provide it */
	scif_clk: scif {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	soc {
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		rwdt: watchdog@e6020000 {
			compatible = "renesas,r8a774a1-wdt",
				     "renesas,rcar-gen3-wdt";
			reg = <0 0xe6020000 0 0x0c>;
			clocks = <&cpg CPG_MOD 402>;
			power-domains = <&sysc 32>;
			resets = <&cpg 402>;
			status = "disabled";
		};

		gpio0: gpio@e6050000 {
			compatible = "renesas,gpio-r8a774a1",
				     "renesas,rcar-gen3-gpio";
			reg = <0 0xe6050000 0 0x50>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 0 16>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 912>;
			power-domains = <&sysc 32>;
			resets = <&cpg 912>;
		};

		gpio1: gpio@e6051000 {
			compatible = "renesas,gpio-r8a774a1",
				     "renesas,rcar-gen3-gpio";
			reg = <0 0xe6051000 0 0x50>;
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 32 29>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 911>;
			power-domains = <&sysc 32>;
			resets = <&cpg 911>;
		};

		gpio2: gpio@e6052000 {
			compatible = "renesas,gpio-r8a774a1",
				     "renesas,rcar-gen3-gpio";
			reg = <0 0xe6052000 0 0x50>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 64 15>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 910>;
			power-domains = <&sysc 32>;
			resets = <&cpg 910>;
		};

		gpio3: gpio@e6053000 {
			compatible = "renesas,gpio-r8a774a1",
				     "renesas,rcar-gen3-gpio";
			reg = <0 0xe6053000 0 0x50>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 96 16>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 909>;
			power-domains = <&sysc 32>;
			resets = <&cpg 909>;
		};

		gpio4: gpio@e6054000 {
			compatible = "renesas,gpio-r8a774a1",
				     "renesas,rcar-gen3-gpio";
			reg = <0 0xe6054000 0 0x50>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 128 18>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 908>;
			power-domains = <&sysc 32>;
			resets = <&cpg 908>;
		};

		gpio5: gpio@e6055000 {
			compatible = "renesas,gpio-r8a774a1",
				     "renesas,rcar-gen3-gpio";
			reg = <0 0xe6055000 0 0x50>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 160 26>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 907>;
			power-domains = <&sysc 32>;
			resets = <&cpg 907>;
		};

		gpio6: gpio@e6055400 {
			compatible = "renesas,gpio-r8a774a1",
				     "renesas,rcar-gen3-gpio";
			reg = <0 0xe6055400 0 0x50>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 192 32>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 906>;
			power-domains = <&sysc 32>;
			resets = <&cpg 906>;
		};

		gpio7: gpio@e6055800 {
			compatible = "renesas,gpio-r8a774a1",
				     "renesas,rcar-gen3-gpio";
			reg = <0 0xe6055800 0 0x50>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 224 4>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 905>;
			power-domains = <&sysc 32>;
			resets = <&cpg 905>;
		};

		pfc: pin-controller@e6060000 {
			compatible = "renesas,pfc-r8a774a1";
			reg = <0 0xe6060000 0 0x50c>;
		};

		cpg: clock-controller@e6150000 {
			compatible = "renesas,r8a774a1-cpg-mssr";
			reg = <0 0xe6150000 0 0x0bb0>;
			clocks = <&extal_clk>, <&extalr_clk>;
			clock-names = "extal", "extalr";
			#clock-cells = <2>;
			#power-domain-cells = <0>;
			#reset-cells = <1>;
		};

		rst: reset-controller@e6160000 {
			compatible = "renesas,r8a774a1-rst";
			reg = <0 0xe6160000 0 0x018c>;
		};

		sysc: system-controller@e6180000 {
			compatible = "renesas,r8a774a1-sysc";
			reg = <0 0xe6180000 0 0x0400>;
			#power-domain-cells = <1>;
		};

		intc_ex: interrupt-controller@e61c0000 {
			compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc";
			#interrupt-cells = <2>;
			interrupt-controller;
			reg = <0 0xe61c0000 0 0x200>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 407>;
			power-domains = <&sysc 32>;
			resets = <&cpg 407>;
		};

		hscif0: serial@e6540000 {
			compatible = "renesas,hscif-r8a774a1",
				     "renesas,rcar-gen3-hscif",
				     "renesas,hscif";
			reg = <0 0xe6540000 0 0x60>;
			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 520>,
				 <&cpg CPG_CORE 19>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
			       <&dmac2 0x31>, <&dmac2 0x30>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc 32>;
			resets = <&cpg 520>;
			status = "disabled";
		};

		hscif1: serial@e6550000 {
			compatible = "renesas,hscif-r8a774a1",
				     "renesas,rcar-gen3-hscif",
				     "renesas,hscif";
			reg = <0 0xe6550000 0 0x60>;
			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 519>,
				 <&cpg CPG_CORE 19>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac1 0x33>, <&dmac1 0x32>,
			       <&dmac2 0x33>, <&dmac2 0x32>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc 32>;
			resets = <&cpg 519>;
			status = "disabled";
		};

		hscif2: serial@e6560000 {
			compatible = "renesas,hscif-r8a774a1",
				     "renesas,rcar-gen3-hscif",
				     "renesas,hscif";
			reg = <0 0xe6560000 0 0x60>;
			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 518>,
				 <&cpg CPG_CORE 19>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac1 0x35>, <&dmac1 0x34>,
			       <&dmac2 0x35>, <&dmac2 0x34>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc 32>;
			resets = <&cpg 518>;
			status = "disabled";
		};

		hscif3: serial@e66a0000 {
			compatible = "renesas,hscif-r8a774a1",
				     "renesas,rcar-gen3-hscif",
				     "renesas,hscif";
			reg = <0 0xe66a0000 0 0x60>;
			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 517>,
				 <&cpg CPG_CORE 19>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0x37>, <&dmac0 0x36>;
			dma-names = "tx", "rx";
			power-domains = <&sysc 32>;
			resets = <&cpg 517>;
			status = "disabled";
		};

		hscif4: serial@e66b0000 {
			compatible = "renesas,hscif-r8a774a1",
				     "renesas,rcar-gen3-hscif",
				     "renesas,hscif";
			reg = <0 0xe66b0000 0 0x60>;
			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 516>,
				 <&cpg CPG_CORE 19>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0x39>, <&dmac0 0x38>;
			dma-names = "tx", "rx";
			power-domains = <&sysc 32>;
			resets = <&cpg 516>;
			status = "disabled";
		};

		dmac0: dma-controller@e6700000 {
			compatible = "renesas,dmac-r8a774a1",
				     "renesas,rcar-dmac";
			reg = <0 0xe6700000 0 0x10000>;
			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error",
					"ch0", "ch1", "ch2", "ch3",
					"ch4", "ch5", "ch6", "ch7",
					"ch8", "ch9", "ch10", "ch11",
					"ch12", "ch13", "ch14", "ch15";
			clocks = <&cpg CPG_MOD 219>;
			clock-names = "fck";
			power-domains = <&sysc 32>;
			resets = <&cpg 219>;
			#dma-cells = <1>;
			dma-channels = <16>;
		};

		dmac1: dma-controller@e7300000 {
			compatible = "renesas,dmac-r8a774a1",
				     "renesas,rcar-dmac";
			reg = <0 0xe7300000 0 0x10000>;
			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error",
					"ch0", "ch1", "ch2", "ch3",
					"ch4", "ch5", "ch6", "ch7",
					"ch8", "ch9", "ch10", "ch11",
					"ch12", "ch13", "ch14", "ch15";
			clocks = <&cpg CPG_MOD 218>;
			clock-names = "fck";
			power-domains = <&sysc 32>;
			resets = <&cpg 218>;
			#dma-cells = <1>;
			dma-channels = <16>;
		};

		dmac2: dma-controller@e7310000 {
			compatible = "renesas,dmac-r8a774a1",
				     "renesas,rcar-dmac";
			reg = <0 0xe7310000 0 0x10000>;
			interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
				      GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error",
					"ch0", "ch1", "ch2", "ch3",
					"ch4", "ch5", "ch6", "ch7",
					"ch8", "ch9", "ch10", "ch11",
					"ch12", "ch13", "ch14", "ch15";
			clocks = <&cpg CPG_MOD 217>;
			clock-names = "fck";
			power-domains = <&sysc 32>;
			resets = <&cpg 217>;
			#dma-cells = <1>;
			dma-channels = <16>;
		};

		avb: ethernet@e6800000 {
			compatible = "renesas,etheravb-r8a774a1",
				     "renesas,etheravb-rcar-gen3";
			reg = <0 0xe6800000 0 0x800>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "ch0", "ch1", "ch2", "ch3",
					  "ch4", "ch5", "ch6", "ch7",
					  "ch8", "ch9", "ch10", "ch11",
					  "ch12", "ch13", "ch14", "ch15",
					  "ch16", "ch17", "ch18", "ch19",
					  "ch20", "ch21", "ch22", "ch23",
					  "ch24";
			clocks = <&cpg CPG_MOD 812>;
			power-domains = <&sysc 32>;
			resets = <&cpg 812>;
			phy-mode = "rgmii";
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		scif0: serial@e6e60000 {
			compatible = "renesas,scif-r8a774a1",
				     "renesas,rcar-gen3-scif", "renesas,scif";
			reg = <0 0xe6e60000 0 0x40>;
			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 207>,
				 <&cpg CPG_CORE 19>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
			       <&dmac2 0x51>, <&dmac2 0x50>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc 32>;
			resets = <&cpg 207>;
			status = "disabled";
		};

		scif1: serial@e6e68000 {
			compatible = "renesas,scif-r8a774a1",
				     "renesas,rcar-gen3-scif", "renesas,scif";
			reg = <0 0xe6e68000 0 0x40>;
			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 206>,
				 <&cpg CPG_CORE 19>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
			       <&dmac2 0x53>, <&dmac2 0x52>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc 32>;
			resets = <&cpg 206>;
			status = "disabled";
		};

		scif2: serial@e6e88000 {
			compatible = "renesas,scif-r8a774a1",
				     "renesas,rcar-gen3-scif", "renesas,scif";
			reg = <0 0xe6e88000 0 0x40>;
			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 310>,
				 <&cpg CPG_CORE 19>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			power-domains = <&sysc 32>;
			resets = <&cpg 310>;
			status = "disabled";
		};

		scif3: serial@e6c50000 {
			compatible = "renesas,scif-r8a774a1",
				     "renesas,rcar-gen3-scif", "renesas,scif";
			reg = <0 0xe6c50000 0 0x40>;
			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 204>,
				 <&cpg CPG_CORE 19>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0x57>, <&dmac0 0x56>;
			dma-names = "tx", "rx";
			power-domains = <&sysc 32>;
			resets = <&cpg 204>;
			status = "disabled";
		};

		scif4: serial@e6c40000 {
			compatible = "renesas,scif-r8a774a1",
				     "renesas,rcar-gen3-scif", "renesas,scif";
			reg = <0 0xe6c40000 0 0x40>;
			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 203>,
				 <&cpg CPG_CORE 19>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0x59>, <&dmac0 0x58>;
			dma-names = "tx", "rx";
			power-domains = <&sysc 32>;
			resets = <&cpg 203>;
			status = "disabled";
		};

		scif5: serial@e6f30000 {
			compatible = "renesas,scif-r8a774a1",
				     "renesas,rcar-gen3-scif", "renesas,scif";
			reg = <0 0xe6f30000 0 0x40>;
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 202>,
				 <&cpg CPG_CORE 19>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
			       <&dmac2 0x5b>, <&dmac2 0x5a>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc 32>;
			resets = <&cpg 202>;
			status = "disabled";
		};

		gic: interrupt-controller@f1010000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x0 0xf1010000 0 0x1000>,
			      <0x0 0xf1020000 0 0x20000>,
			      <0x0 0xf1040000 0 0x20000>,
			      <0x0 0xf1060000 0 0x20000>;
			interrupts = <GIC_PPI 9
					(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&cpg CPG_MOD 408>;
			clock-names = "clk";
			power-domains = <&sysc 32>;
			resets = <&cpg 408>;
		};

		prr: chipid@fff00044 {
			compatible = "renesas,prr";
			reg = <0 0xfff00044 0 4>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
	};

	/* External USB clocks - can be overridden by the board */
	usb3s0_clk: usb3s0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	usb_extal_clk: usb_extal {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};
};
Commit	Line	Data
90493b09 BD	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Device Tree Source for the r8a774a1 SoC
	4	*
	5	* Copyright (C) 2018 Renesas Electronics Corp.
	6	*/
	7
	8	#include <dt-bindings/interrupt-controller/irq.h>
	9	#include <dt-bindings/interrupt-controller/arm-gic.h>
	10	#include <dt-bindings/clock/renesas-cpg-mssr.h>
	11
	12	/ {
	13	compatible = "renesas,r8a774a1";
	14	#address-cells = <2>;
	15	#size-cells = <2>;
	16
	17	/*
	18	* The external audio clocks are configured as 0 Hz fixed frequency
	19	* clocks by default.
	20	* Boards that provide audio clocks should override them.
	21	*/
	22	audio_clk_a: audio_clk_a {
	23	compatible = "fixed-clock";
	24	#clock-cells = <0>;
	25	clock-frequency = <0>;
	26	};
	27
	28	audio_clk_b: audio_clk_b {
	29	compatible = "fixed-clock";
	30	#clock-cells = <0>;
	31	clock-frequency = <0>;
	32	};
	33
	34	audio_clk_c: audio_clk_c {
	35	compatible = "fixed-clock";
	36	#clock-cells = <0>;
	37	clock-frequency = <0>;
	38	};
	39
	40	/* External CAN clock - to be overridden by boards that provide it */
	41	can_clk: can {
	42	compatible = "fixed-clock";
	43	#clock-cells = <0>;
	44	clock-frequency = <0>;
	45	};
	46
	47	cpus {
	48	#address-cells = <1>;
	49	#size-cells = <0>;
	50
	51	a57_0: cpu@0 {
	52	compatible = "arm,cortex-a57", "arm,armv8";
	53	reg = <0x0>;
	54	device_type = "cpu";
	55	power-domains = <&sysc 0>;
	56	next-level-cache = <&L2_CA57>;
	57	enable-method = "psci";
	58	clocks =<&cpg CPG_CORE 0>;
	59	};
	60
	61	a57_1: cpu@1 {
	62	compatible = "arm,cortex-a57", "arm,armv8";
	63	reg = <0x1>;
	64	device_type = "cpu";
65	power-domains = <&sysc 1>;
66	next-level-cache = <&L2_CA57>;
67	enable-method = "psci";
68	clocks =<&cpg CPG_CORE 0>;
69	};
70
71	L2_CA57: cache-controller-0 {
72	compatible = "cache";
73	power-domains = <&sysc 12>;
74	cache-unified;
75	cache-level = <2>;
76	};
77	};
78
79	extal_clk: extal {
80	compatible = "fixed-clock";
81	#clock-cells = <0>;
82	/* This value must be overridden by the board */
83	clock-frequency = <0>;
84	};
85
86	extalr_clk: extalr {
87	compatible = "fixed-clock";
88	#clock-cells = <0>;
89	/* This value must be overridden by the board */
90	clock-frequency = <0>;
91	};
92
93	/* External PCIe clock - can be overridden by the board */
94	pcie_bus_clk: pcie_bus {
95	compatible = "fixed-clock";
96	#clock-cells = <0>;
97	clock-frequency = <0>;
98	};
99
100	pmu_a57 {
101	compatible = "arm,cortex-a57-pmu";
102	interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
103	<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
104	interrupt-affinity = <&a57_0>, <&a57_1>;
105	};
106
107	psci {
108	compatible = "arm,psci-1.0", "arm,psci-0.2";
109	method = "smc";
110	};
111
112	/* External SCIF clock - to be overridden by boards that provide it */
113	scif_clk: scif {
114	compatible = "fixed-clock";
115	#clock-cells = <0>;
116	clock-frequency = <0>;
117	};
118
119	soc {
120	compatible = "simple-bus";
121	interrupt-parent = <&gic>;
122	#address-cells = <2>;
123	#size-cells = <2>;
124	ranges;
125
426f0b95 BD	126	rwdt: watchdog@e6020000 {
	127	compatible = "renesas,r8a774a1-wdt",
	128	"renesas,rcar-gen3-wdt";
	129	reg = <0 0xe6020000 0 0x0c>;
	130	clocks = <&cpg CPG_MOD 402>;
	131	power-domains = <&sysc 32>;
	132	resets = <&cpg 402>;
	133	status = "disabled";
	134	};
	135
53ae5809 FC	136	gpio0: gpio@e6050000 {
	137	compatible = "renesas,gpio-r8a774a1",
	138	"renesas,rcar-gen3-gpio";
	139	reg = <0 0xe6050000 0 0x50>;
	140	interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	141	#gpio-cells = <2>;
	142	gpio-controller;
	143	gpio-ranges = <&pfc 0 0 16>;
	144	#interrupt-cells = <2>;
	145	interrupt-controller;
	146	clocks = <&cpg CPG_MOD 912>;
	147	power-domains = <&sysc 32>;
	148	resets = <&cpg 912>;
	149	};
	150
	151	gpio1: gpio@e6051000 {
	152	compatible = "renesas,gpio-r8a774a1",
	153	"renesas,rcar-gen3-gpio";
	154	reg = <0 0xe6051000 0 0x50>;
	155	interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
	156	#gpio-cells = <2>;
	157	gpio-controller;
	158	gpio-ranges = <&pfc 0 32 29>;
	159	#interrupt-cells = <2>;
	160	interrupt-controller;
	161	clocks = <&cpg CPG_MOD 911>;
	162	power-domains = <&sysc 32>;
	163	resets = <&cpg 911>;
	164	};
	165
	166	gpio2: gpio@e6052000 {
	167	compatible = "renesas,gpio-r8a774a1",
	168	"renesas,rcar-gen3-gpio";
	169	reg = <0 0xe6052000 0 0x50>;
	170	interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
	171	#gpio-cells = <2>;
	172	gpio-controller;
	173	gpio-ranges = <&pfc 0 64 15>;
	174	#interrupt-cells = <2>;
	175	interrupt-controller;
	176	clocks = <&cpg CPG_MOD 910>;
	177	power-domains = <&sysc 32>;
	178	resets = <&cpg 910>;
	179	};
	180
	181	gpio3: gpio@e6053000 {
	182	compatible = "renesas,gpio-r8a774a1",
	183	"renesas,rcar-gen3-gpio";
	184	reg = <0 0xe6053000 0 0x50>;
	185	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
	186	#gpio-cells = <2>;
	187	gpio-controller;
	188	gpio-ranges = <&pfc 0 96 16>;
	189	#interrupt-cells = <2>;
	190	interrupt-controller;
	191	clocks = <&cpg CPG_MOD 909>;
	192	power-domains = <&sysc 32>;
	193	resets = <&cpg 909>;
	194	};
	195
	196	gpio4: gpio@e6054000 {
	197	compatible = "renesas,gpio-r8a774a1",
	198	"renesas,rcar-gen3-gpio";
	199	reg = <0 0xe6054000 0 0x50>;
200	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
201	#gpio-cells = <2>;
202	gpio-controller;
203	gpio-ranges = <&pfc 0 128 18>;
204	#interrupt-cells = <2>;
205	interrupt-controller;
206	clocks = <&cpg CPG_MOD 908>;
207	power-domains = <&sysc 32>;
208	resets = <&cpg 908>;
209	};
210
211	gpio5: gpio@e6055000 {
212	compatible = "renesas,gpio-r8a774a1",
213	"renesas,rcar-gen3-gpio";
214	reg = <0 0xe6055000 0 0x50>;
215	interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
216	#gpio-cells = <2>;
217	gpio-controller;
218	gpio-ranges = <&pfc 0 160 26>;
219	#interrupt-cells = <2>;
220	interrupt-controller;
221	clocks = <&cpg CPG_MOD 907>;
222	power-domains = <&sysc 32>;
223	resets = <&cpg 907>;
224	};
225
226	gpio6: gpio@e6055400 {
227	compatible = "renesas,gpio-r8a774a1",
228	"renesas,rcar-gen3-gpio";
229	reg = <0 0xe6055400 0 0x50>;
230	interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
231	#gpio-cells = <2>;
232	gpio-controller;
233	gpio-ranges = <&pfc 0 192 32>;
234	#interrupt-cells = <2>;
235	interrupt-controller;
236	clocks = <&cpg CPG_MOD 906>;
237	power-domains = <&sysc 32>;
238	resets = <&cpg 906>;
239	};
240
241	gpio7: gpio@e6055800 {
242	compatible = "renesas,gpio-r8a774a1",
243	"renesas,rcar-gen3-gpio";
244	reg = <0 0xe6055800 0 0x50>;
245	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
246	#gpio-cells = <2>;
247	gpio-controller;
248	gpio-ranges = <&pfc 0 224 4>;
249	#interrupt-cells = <2>;
250	interrupt-controller;
251	clocks = <&cpg CPG_MOD 905>;
252	power-domains = <&sysc 32>;
253	resets = <&cpg 905>;
254	};
255
3698dbd0 FC	256	pfc: pin-controller@e6060000 {
	257	compatible = "renesas,pfc-r8a774a1";
	258	reg = <0 0xe6060000 0 0x50c>;
	259	};
	260
90493b09 BD	261	cpg: clock-controller@e6150000 {
	262	compatible = "renesas,r8a774a1-cpg-mssr";
	263	reg = <0 0xe6150000 0 0x0bb0>;
	264	clocks = <&extal_clk>, <&extalr_clk>;
	265	clock-names = "extal", "extalr";
	266	#clock-cells = <2>;
	267	#power-domain-cells = <0>;
	268	#reset-cells = <1>;
	269	};
	270
	271	rst: reset-controller@e6160000 {
	272	compatible = "renesas,r8a774a1-rst";
	273	reg = <0 0xe6160000 0 0x018c>;
	274	};
	275
	276	sysc: system-controller@e6180000 {
	277	compatible = "renesas,r8a774a1-sysc";
	278	reg = <0 0xe6180000 0 0x0400>;
	279	#power-domain-cells = <1>;
	280	};
	281
a21c572c BD	282	intc_ex: interrupt-controller@e61c0000 {
	283	compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc";
	284	#interrupt-cells = <2>;
	285	interrupt-controller;
	286	reg = <0 0xe61c0000 0 0x200>;
	287	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
	288	GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
	289	GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
	290	GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
	291	GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
	292	GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
	293	clocks = <&cpg CPG_MOD 407>;
	294	power-domains = <&sysc 32>;
	295	resets = <&cpg 407>;
	296	};
	297
3a3933a4 FC	298	hscif0: serial@e6540000 {
	299	compatible = "renesas,hscif-r8a774a1",
	300	"renesas,rcar-gen3-hscif",
	301	"renesas,hscif";
	302	reg = <0 0xe6540000 0 0x60>;
	303	interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
	304	clocks = <&cpg CPG_MOD 520>,
	305	<&cpg CPG_CORE 19>,
	306	<&scif_clk>;
	307	clock-names = "fck", "brg_int", "scif_clk";
	308	dmas = <&dmac1 0x31>, <&dmac1 0x30>,
	309	<&dmac2 0x31>, <&dmac2 0x30>;
	310	dma-names = "tx", "rx", "tx", "rx";
	311	power-domains = <&sysc 32>;
	312	resets = <&cpg 520>;
	313	status = "disabled";
	314	};
	315
	316	hscif1: serial@e6550000 {
	317	compatible = "renesas,hscif-r8a774a1",
	318	"renesas,rcar-gen3-hscif",
	319	"renesas,hscif";
	320	reg = <0 0xe6550000 0 0x60>;
	321	interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
	322	clocks = <&cpg CPG_MOD 519>,
	323	<&cpg CPG_CORE 19>,
	324	<&scif_clk>;
	325	clock-names = "fck", "brg_int", "scif_clk";
	326	dmas = <&dmac1 0x33>, <&dmac1 0x32>,
	327	<&dmac2 0x33>, <&dmac2 0x32>;
	328	dma-names = "tx", "rx", "tx", "rx";
	329	power-domains = <&sysc 32>;
	330	resets = <&cpg 519>;
	331	status = "disabled";
	332	};
	333
	334	hscif2: serial@e6560000 {
	335	compatible = "renesas,hscif-r8a774a1",
	336	"renesas,rcar-gen3-hscif",
	337	"renesas,hscif";
	338	reg = <0 0xe6560000 0 0x60>;
	339	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
	340	clocks = <&cpg CPG_MOD 518>,
	341	<&cpg CPG_CORE 19>,
	342	<&scif_clk>;
	343	clock-names = "fck", "brg_int", "scif_clk";
	344	dmas = <&dmac1 0x35>, <&dmac1 0x34>,
	345	<&dmac2 0x35>, <&dmac2 0x34>;
	346	dma-names = "tx", "rx", "tx", "rx";
	347	power-domains = <&sysc 32>;
	348	resets = <&cpg 518>;
	349	status = "disabled";
	350	};
	351
	352	hscif3: serial@e66a0000 {
	353	compatible = "renesas,hscif-r8a774a1",
	354	"renesas,rcar-gen3-hscif",
	355	"renesas,hscif";
	356	reg = <0 0xe66a0000 0 0x60>;
	357	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
	358	clocks = <&cpg CPG_MOD 517>,
	359	<&cpg CPG_CORE 19>,
	360	<&scif_clk>;
	361	clock-names = "fck", "brg_int", "scif_clk";
362	dmas = <&dmac0 0x37>, <&dmac0 0x36>;
363	dma-names = "tx", "rx";
364	power-domains = <&sysc 32>;
365	resets = <&cpg 517>;
366	status = "disabled";
367	};
368
369	hscif4: serial@e66b0000 {
370	compatible = "renesas,hscif-r8a774a1",
371	"renesas,rcar-gen3-hscif",
372	"renesas,hscif";
373	reg = <0 0xe66b0000 0 0x60>;
374	interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
375	clocks = <&cpg CPG_MOD 516>,
376	<&cpg CPG_CORE 19>,
377	<&scif_clk>;
378	clock-names = "fck", "brg_int", "scif_clk";
379	dmas = <&dmac0 0x39>, <&dmac0 0x38>;
380	dma-names = "tx", "rx";
381	power-domains = <&sysc 32>;
382	resets = <&cpg 516>;
383	status = "disabled";
384	};
385
37a61e4d BD	386	dmac0: dma-controller@e6700000 {
	387	compatible = "renesas,dmac-r8a774a1",
	388	"renesas,rcar-dmac";
	389	reg = <0 0xe6700000 0 0x10000>;
	390	interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
	391	GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
	392	GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
	393	GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
	394	GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
	395	GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
	396	GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
	397	GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
	398	GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
	399	GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
	400	GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
	401	GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
	402	GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
	403	GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
	404	GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
	405	GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
	406	GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
	407	interrupt-names = "error",
	408	"ch0", "ch1", "ch2", "ch3",
	409	"ch4", "ch5", "ch6", "ch7",
	410	"ch8", "ch9", "ch10", "ch11",
	411	"ch12", "ch13", "ch14", "ch15";
	412	clocks = <&cpg CPG_MOD 219>;
	413	clock-names = "fck";
	414	power-domains = <&sysc 32>;
	415	resets = <&cpg 219>;
	416	#dma-cells = <1>;
	417	dma-channels = <16>;
	418	};
	419
	420	dmac1: dma-controller@e7300000 {
	421	compatible = "renesas,dmac-r8a774a1",
	422	"renesas,rcar-dmac";
	423	reg = <0 0xe7300000 0 0x10000>;
	424	interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
	425	GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
	426	GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
	427	GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
	428	GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
	429	GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
	430	GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
	431	GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
	432	GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
	433	GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
	434	GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
	435	GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
	436	GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
	437	GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
	438	GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
	439	GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
	440	GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
	441	interrupt-names = "error",
	442	"ch0", "ch1", "ch2", "ch3",
	443	"ch4", "ch5", "ch6", "ch7",
	444	"ch8", "ch9", "ch10", "ch11",
	445	"ch12", "ch13", "ch14", "ch15";
	446	clocks = <&cpg CPG_MOD 218>;
	447	clock-names = "fck";
	448	power-domains = <&sysc 32>;
	449	resets = <&cpg 218>;
450	#dma-cells = <1>;
451	dma-channels = <16>;
452	};
453
454	dmac2: dma-controller@e7310000 {
455	compatible = "renesas,dmac-r8a774a1",
456	"renesas,rcar-dmac";
457	reg = <0 0xe7310000 0 0x10000>;
458	interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
459	GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
460	GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
461	GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
462	GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
463	GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
464	GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
465	GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
466	GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
467	GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
468	GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
469	GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
470	GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
471	GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
472	GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
473	GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
474	GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
475	interrupt-names = "error",
476	"ch0", "ch1", "ch2", "ch3",
477	"ch4", "ch5", "ch6", "ch7",
478	"ch8", "ch9", "ch10", "ch11",
479	"ch12", "ch13", "ch14", "ch15";
480	clocks = <&cpg CPG_MOD 217>;
481	clock-names = "fck";
482	power-domains = <&sysc 32>;
483	resets = <&cpg 217>;
484	#dma-cells = <1>;
485	dma-channels = <16>;
486	};
487
71bddde2 FC	488	avb: ethernet@e6800000 {
	489	compatible = "renesas,etheravb-r8a774a1",
	490	"renesas,etheravb-rcar-gen3";
	491	reg = <0 0xe6800000 0 0x800>;
	492	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
	493	<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	494	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	495	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	496	<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
	497	<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
	498	<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
	499	<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
	500	<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
	501	<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
	502	<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
	503	<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
	504	<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
	505	<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
	506	<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	507	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	508	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	509	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
	510	<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
	511	<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	512	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	513	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	514	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
	515	<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
	516	<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
	517	interrupt-names = "ch0", "ch1", "ch2", "ch3",
	518	"ch4", "ch5", "ch6", "ch7",
	519	"ch8", "ch9", "ch10", "ch11",
	520	"ch12", "ch13", "ch14", "ch15",
	521	"ch16", "ch17", "ch18", "ch19",
	522	"ch20", "ch21", "ch22", "ch23",
	523	"ch24";
	524	clocks = <&cpg CPG_MOD 812>;
	525	power-domains = <&sysc 32>;
	526	resets = <&cpg 812>;
	527	phy-mode = "rgmii";
	528	#address-cells = <1>;
	529	#size-cells = <0>;
	530	status = "disabled";
	531	};
	532
3a3933a4 FC	533	scif0: serial@e6e60000 {
	534	compatible = "renesas,scif-r8a774a1",
	535	"renesas,rcar-gen3-scif", "renesas,scif";
	536	reg = <0 0xe6e60000 0 0x40>;
	537	interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
	538	clocks = <&cpg CPG_MOD 207>,
	539	<&cpg CPG_CORE 19>,
	540	<&scif_clk>;
	541	clock-names = "fck", "brg_int", "scif_clk";
	542	dmas = <&dmac1 0x51>, <&dmac1 0x50>,
	543	<&dmac2 0x51>, <&dmac2 0x50>;
	544	dma-names = "tx", "rx", "tx", "rx";
	545	power-domains = <&sysc 32>;
	546	resets = <&cpg 207>;
	547	status = "disabled";
	548	};
	549
	550	scif1: serial@e6e68000 {
	551	compatible = "renesas,scif-r8a774a1",
	552	"renesas,rcar-gen3-scif", "renesas,scif";
	553	reg = <0 0xe6e68000 0 0x40>;
	554	interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
	555	clocks = <&cpg CPG_MOD 206>,
	556	<&cpg CPG_CORE 19>,
	557	<&scif_clk>;
	558	clock-names = "fck", "brg_int", "scif_clk";
	559	dmas = <&dmac1 0x53>, <&dmac1 0x52>,
	560	<&dmac2 0x53>, <&dmac2 0x52>;
	561	dma-names = "tx", "rx", "tx", "rx";
	562	power-domains = <&sysc 32>;
	563	resets = <&cpg 206>;
	564	status = "disabled";
	565	};
	566
	567	scif2: serial@e6e88000 {
	568	compatible = "renesas,scif-r8a774a1",
	569	"renesas,rcar-gen3-scif", "renesas,scif";
	570	reg = <0 0xe6e88000 0 0x40>;
	571	interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
	572	clocks = <&cpg CPG_MOD 310>,
	573	<&cpg CPG_CORE 19>,
	574	<&scif_clk>;
	575	clock-names = "fck", "brg_int", "scif_clk";
	576	power-domains = <&sysc 32>;
	577	resets = <&cpg 310>;
	578	status = "disabled";
	579	};
	580
	581	scif3: serial@e6c50000 {
	582	compatible = "renesas,scif-r8a774a1",
	583	"renesas,rcar-gen3-scif", "renesas,scif";
	584	reg = <0 0xe6c50000 0 0x40>;
	585	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	586	clocks = <&cpg CPG_MOD 204>,
	587	<&cpg CPG_CORE 19>,
	588	<&scif_clk>;
	589	clock-names = "fck", "brg_int", "scif_clk";
	590	dmas = <&dmac0 0x57>, <&dmac0 0x56>;
	591	dma-names = "tx", "rx";
	592	power-domains = <&sysc 32>;
	593	resets = <&cpg 204>;
	594	status = "disabled";
	595	};
	596
597	scif4: serial@e6c40000 {
598	compatible = "renesas,scif-r8a774a1",
599	"renesas,rcar-gen3-scif", "renesas,scif";
600	reg = <0 0xe6c40000 0 0x40>;
601	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
602	clocks = <&cpg CPG_MOD 203>,
603	<&cpg CPG_CORE 19>,
604	<&scif_clk>;
605	clock-names = "fck", "brg_int", "scif_clk";
606	dmas = <&dmac0 0x59>, <&dmac0 0x58>;
607	dma-names = "tx", "rx";
608	power-domains = <&sysc 32>;
609	resets = <&cpg 203>;
610	status = "disabled";
611	};
612
613	scif5: serial@e6f30000 {
614	compatible = "renesas,scif-r8a774a1",
615	"renesas,rcar-gen3-scif", "renesas,scif";
616	reg = <0 0xe6f30000 0 0x40>;
617	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
618	clocks = <&cpg CPG_MOD 202>,
619	<&cpg CPG_CORE 19>,
620	<&scif_clk>;
621	clock-names = "fck", "brg_int", "scif_clk";
622	dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
623	<&dmac2 0x5b>, <&dmac2 0x5a>;
624	dma-names = "tx", "rx", "tx", "rx";
625	power-domains = <&sysc 32>;
626	resets = <&cpg 202>;
627	status = "disabled";
628	};
629
90493b09 BD	630	gic: interrupt-controller@f1010000 {
	631	compatible = "arm,gic-400";
	632	#interrupt-cells = <3>;
	633	#address-cells = <0>;
	634	interrupt-controller;
	635	reg = <0x0 0xf1010000 0 0x1000>,
	636	<0x0 0xf1020000 0 0x20000>,
	637	<0x0 0xf1040000 0 0x20000>,
	638	<0x0 0xf1060000 0 0x20000>;
	639	interrupts = <GIC_PPI 9
	640	(GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>;
	641	clocks = <&cpg CPG_MOD 408>;
	642	clock-names = "clk";
	643	power-domains = <&sysc 32>;
	644	resets = <&cpg 408>;
	645	};
	646
	647	prr: chipid@fff00044 {
	648	compatible = "renesas,prr";
	649	reg = <0 0xfff00044 0 4>;
	650	};
	651	};
	652
	653	timer {
	654	compatible = "arm,armv8-timer";
	655	interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	656	<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	657	<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>,
	658	<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_LOW)>;
	659	};
	660
	661	/* External USB clocks - can be overridden by the board */
	662	usb3s0_clk: usb3s0 {
	663	compatible = "fixed-clock";
	664	#clock-cells = <0>;
	665	clock-frequency = <0>;
	666	};
	667
	668	usb_extal_clk: usb_extal {
	669	compatible = "fixed-clock";
	670	#clock-cells = <0>;
	671	clock-frequency = <0>;
	672	};
	673	};