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arm64: dts: renesas: r8a774a1: Add I2C and IIC-DVFS support
[mirror_ubuntu-focal-kernel.git] / arch / arm64 / boot / dts / renesas / r8a774a1.dtsi
CommitLineData
90493b09
BD		 1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the r8a774a1 SoC
4 *
5 * Copyright (C) 2018 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/clock/renesas-cpg-mssr.h>
11
12/ {
13 compatible = "renesas,r8a774a1";
14 #address-cells = <2>;
15 #size-cells = <2>;
16
c674e8a7
BD		 17 aliases {
18 i2c0 = &i2c0;
19 i2c1 = &i2c1;
20 i2c2 = &i2c2;
21 i2c3 = &i2c3;
22 i2c4 = &i2c4;
23 i2c5 = &i2c5;
24 i2c6 = &i2c6;
25 i2c7 = &i2c_dvfs;
26 };
27
90493b09
BD		 28 /*
29 * The external audio clocks are configured as 0 Hz fixed frequency
30 * clocks by default.
31 * Boards that provide audio clocks should override them.
32 */
33 audio_clk_a: audio_clk_a {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <0>;
37 };
38
39 audio_clk_b: audio_clk_b {
40 compatible = "fixed-clock";
41 #clock-cells = <0>;
42 clock-frequency = <0>;
43 };
44
45 audio_clk_c: audio_clk_c {
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <0>;
49 };
50
51 /* External CAN clock - to be overridden by boards that provide it */
52 can_clk: can {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <0>;
56 };
57
58 cpus {
59 #address-cells = <1>;
60 #size-cells = <0>;
61
62 a57_0: cpu@0 {
63 compatible = "arm,cortex-a57", "arm,armv8";
64 reg = <0x0>;
65 device_type = "cpu";
66 power-domains = <&sysc 0>;
67 next-level-cache = <&L2_CA57>;
68 enable-method = "psci";
69 clocks =<&cpg CPG_CORE 0>;
70 };
71
72 a57_1: cpu@1 {
73 compatible = "arm,cortex-a57", "arm,armv8";
74 reg = <0x1>;
75 device_type = "cpu";
76 power-domains = <&sysc 1>;
77 next-level-cache = <&L2_CA57>;
78 enable-method = "psci";
79 clocks =<&cpg CPG_CORE 0>;
80 };
81
82 L2_CA57: cache-controller-0 {
83 compatible = "cache";
84 power-domains = <&sysc 12>;
85 cache-unified;
86 cache-level = <2>;
87 };
88 };
89
90 extal_clk: extal {
91 compatible = "fixed-clock";
92 #clock-cells = <0>;
93 /* This value must be overridden by the board */
94 clock-frequency = <0>;
95 };
96
97 extalr_clk: extalr {
98 compatible = "fixed-clock";
99 #clock-cells = <0>;
100 /* This value must be overridden by the board */
101 clock-frequency = <0>;
102 };
103
104 /* External PCIe clock - can be overridden by the board */
105 pcie_bus_clk: pcie_bus {
106 compatible = "fixed-clock";
107 #clock-cells = <0>;
108 clock-frequency = <0>;
109 };
110
111 pmu_a57 {
112 compatible = "arm,cortex-a57-pmu";
113 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
114 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
115 interrupt-affinity = <&a57_0>, <&a57_1>;
116 };
117
118 psci {
119 compatible = "arm,psci-1.0", "arm,psci-0.2";
120 method = "smc";
121 };
122
123 /* External SCIF clock - to be overridden by boards that provide it */
124 scif_clk: scif {
125 compatible = "fixed-clock";
126 #clock-cells = <0>;
127 clock-frequency = <0>;
128 };
129
130 soc {
131 compatible = "simple-bus";
132 interrupt-parent = <&gic>;
133 #address-cells = <2>;
134 #size-cells = <2>;
135 ranges;
136
426f0b95
BD		 137 rwdt: watchdog@e6020000 {
138 compatible = "renesas,r8a774a1-wdt",
139 "renesas,rcar-gen3-wdt";
140 reg = <0 0xe6020000 0 0x0c>;
141 clocks = <&cpg CPG_MOD 402>;
142 power-domains = <&sysc 32>;
143 resets = <&cpg 402>;
144 status = "disabled";
145 };
146
53ae5809
FC		 147 gpio0: gpio@e6050000 {
148 compatible = "renesas,gpio-r8a774a1",
149 "renesas,rcar-gen3-gpio";
150 reg = <0 0xe6050000 0 0x50>;
151 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
152 #gpio-cells = <2>;
153 gpio-controller;
154 gpio-ranges = <&pfc 0 0 16>;
155 #interrupt-cells = <2>;
156 interrupt-controller;
157 clocks = <&cpg CPG_MOD 912>;
158 power-domains = <&sysc 32>;
159 resets = <&cpg 912>;
160 };
161
162 gpio1: gpio@e6051000 {
163 compatible = "renesas,gpio-r8a774a1",
164 "renesas,rcar-gen3-gpio";
165 reg = <0 0xe6051000 0 0x50>;
166 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
167 #gpio-cells = <2>;
168 gpio-controller;
169 gpio-ranges = <&pfc 0 32 29>;
170 #interrupt-cells = <2>;
171 interrupt-controller;
172 clocks = <&cpg CPG_MOD 911>;
173 power-domains = <&sysc 32>;
174 resets = <&cpg 911>;
175 };
176
177 gpio2: gpio@e6052000 {
178 compatible = "renesas,gpio-r8a774a1",
179 "renesas,rcar-gen3-gpio";
180 reg = <0 0xe6052000 0 0x50>;
181 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
182 #gpio-cells = <2>;
183 gpio-controller;
184 gpio-ranges = <&pfc 0 64 15>;
185 #interrupt-cells = <2>;
186 interrupt-controller;
187 clocks = <&cpg CPG_MOD 910>;
188 power-domains = <&sysc 32>;
189 resets = <&cpg 910>;
190 };
191
192 gpio3: gpio@e6053000 {
193 compatible = "renesas,gpio-r8a774a1",
194 "renesas,rcar-gen3-gpio";
195 reg = <0 0xe6053000 0 0x50>;
196 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
197 #gpio-cells = <2>;
198 gpio-controller;
199 gpio-ranges = <&pfc 0 96 16>;
200 #interrupt-cells = <2>;
201 interrupt-controller;
202 clocks = <&cpg CPG_MOD 909>;
203 power-domains = <&sysc 32>;
204 resets = <&cpg 909>;
205 };
206
207 gpio4: gpio@e6054000 {
208 compatible = "renesas,gpio-r8a774a1",
209 "renesas,rcar-gen3-gpio";
210 reg = <0 0xe6054000 0 0x50>;
211 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
212 #gpio-cells = <2>;
213 gpio-controller;
214 gpio-ranges = <&pfc 0 128 18>;
215 #interrupt-cells = <2>;
216 interrupt-controller;
217 clocks = <&cpg CPG_MOD 908>;
218 power-domains = <&sysc 32>;
219 resets = <&cpg 908>;
220 };
221
222 gpio5: gpio@e6055000 {
223 compatible = "renesas,gpio-r8a774a1",
224 "renesas,rcar-gen3-gpio";
225 reg = <0 0xe6055000 0 0x50>;
226 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
227 #gpio-cells = <2>;
228 gpio-controller;
229 gpio-ranges = <&pfc 0 160 26>;
230 #interrupt-cells = <2>;
231 interrupt-controller;
232 clocks = <&cpg CPG_MOD 907>;
233 power-domains = <&sysc 32>;
234 resets = <&cpg 907>;
235 };
236
237 gpio6: gpio@e6055400 {
238 compatible = "renesas,gpio-r8a774a1",
239 "renesas,rcar-gen3-gpio";
240 reg = <0 0xe6055400 0 0x50>;
241 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
242 #gpio-cells = <2>;
243 gpio-controller;
244 gpio-ranges = <&pfc 0 192 32>;
245 #interrupt-cells = <2>;
246 interrupt-controller;
247 clocks = <&cpg CPG_MOD 906>;
248 power-domains = <&sysc 32>;
249 resets = <&cpg 906>;
250 };
251
252 gpio7: gpio@e6055800 {
253 compatible = "renesas,gpio-r8a774a1",
254 "renesas,rcar-gen3-gpio";
255 reg = <0 0xe6055800 0 0x50>;
256 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
257 #gpio-cells = <2>;
258 gpio-controller;
259 gpio-ranges = <&pfc 0 224 4>;
260 #interrupt-cells = <2>;
261 interrupt-controller;
262 clocks = <&cpg CPG_MOD 905>;
263 power-domains = <&sysc 32>;
264 resets = <&cpg 905>;
265 };
266
3698dbd0
FC		 267 pfc: pin-controller@e6060000 {
268 compatible = "renesas,pfc-r8a774a1";
269 reg = <0 0xe6060000 0 0x50c>;
270 };
271
90493b09
BD		 272 cpg: clock-controller@e6150000 {
273 compatible = "renesas,r8a774a1-cpg-mssr";
274 reg = <0 0xe6150000 0 0x0bb0>;
275 clocks = <&extal_clk>, <&extalr_clk>;
276 clock-names = "extal", "extalr";
277 #clock-cells = <2>;
278 #power-domain-cells = <0>;
279 #reset-cells = <1>;
280 };
281
282 rst: reset-controller@e6160000 {
283 compatible = "renesas,r8a774a1-rst";
284 reg = <0 0xe6160000 0 0x018c>;
285 };
286
287 sysc: system-controller@e6180000 {
288 compatible = "renesas,r8a774a1-sysc";
289 reg = <0 0xe6180000 0 0x0400>;
290 #power-domain-cells = <1>;
291 };
292
a21c572c
BD		 293 intc_ex: interrupt-controller@e61c0000 {
294 compatible = "renesas,intc-ex-r8a774a1", "renesas,irqc";
295 #interrupt-cells = <2>;
296 interrupt-controller;
297 reg = <0 0xe61c0000 0 0x200>;
298 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
299 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
300 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
301 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
302 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
303 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&cpg CPG_MOD 407>;
305 power-domains = <&sysc 32>;
306 resets = <&cpg 407>;
307 };
308
c674e8a7
BD		 309 i2c0: i2c@e6500000 {
310 #address-cells = <1>;
311 #size-cells = <0>;
312 compatible = "renesas,i2c-r8a774a1",
313 "renesas,rcar-gen3-i2c";
314 reg = <0 0xe6500000 0 0x40>;
315 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&cpg CPG_MOD 931>;
317 power-domains = <&sysc 32>;
318 resets = <&cpg 931>;
319 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
320 <&dmac2 0x91>, <&dmac2 0x90>;
321 dma-names = "tx", "rx", "tx", "rx";
322 i2c-scl-internal-delay-ns = <110>;
323 status = "disabled";
324 };
325
326 i2c1: i2c@e6508000 {
327 #address-cells = <1>;
328 #size-cells = <0>;
329 compatible = "renesas,i2c-r8a774a1",
330 "renesas,rcar-gen3-i2c";
331 reg = <0 0xe6508000 0 0x40>;
332 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&cpg CPG_MOD 930>;
334 power-domains = <&sysc 32>;
335 resets = <&cpg 930>;
336 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
337 <&dmac2 0x93>, <&dmac2 0x92>;
338 dma-names = "tx", "rx", "tx", "rx";
339 i2c-scl-internal-delay-ns = <6>;
340 status = "disabled";
341 };
342
343 i2c2: i2c@e6510000 {
344 #address-cells = <1>;
345 #size-cells = <0>;
346 compatible = "renesas,i2c-r8a774a1",
347 "renesas,rcar-gen3-i2c";
348 reg = <0 0xe6510000 0 0x40>;
349 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&cpg CPG_MOD 929>;
351 power-domains = <&sysc 32>;
352 resets = <&cpg 929>;
353 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
354 <&dmac2 0x95>, <&dmac2 0x94>;
355 dma-names = "tx", "rx", "tx", "rx";
356 i2c-scl-internal-delay-ns = <6>;
357 status = "disabled";
358 };
359
360 i2c3: i2c@e66d0000 {
361 #address-cells = <1>;
362 #size-cells = <0>;
363 compatible = "renesas,i2c-r8a774a1",
364 "renesas,rcar-gen3-i2c";
365 reg = <0 0xe66d0000 0 0x40>;
366 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&cpg CPG_MOD 928>;
368 power-domains = <&sysc 32>;
369 resets = <&cpg 928>;
370 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
371 dma-names = "tx", "rx";
372 i2c-scl-internal-delay-ns = <110>;
373 status = "disabled";
374 };
375
376 i2c4: i2c@e66d8000 {
377 #address-cells = <1>;
378 #size-cells = <0>;
379 compatible = "renesas,i2c-r8a774a1",
380 "renesas,rcar-gen3-i2c";
381 reg = <0 0xe66d8000 0 0x40>;
382 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&cpg CPG_MOD 927>;
384 power-domains = <&sysc 32>;
385 resets = <&cpg 927>;
386 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
387 dma-names = "tx", "rx";
388 i2c-scl-internal-delay-ns = <110>;
389 status = "disabled";
390 };
391
392 i2c5: i2c@e66e0000 {
393 #address-cells = <1>;
394 #size-cells = <0>;
395 compatible = "renesas,i2c-r8a774a1",
396 "renesas,rcar-gen3-i2c";
397 reg = <0 0xe66e0000 0 0x40>;
398 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
399 clocks = <&cpg CPG_MOD 919>;
400 power-domains = <&sysc 32>;
401 resets = <&cpg 919>;
402 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
403 dma-names = "tx", "rx";
404 i2c-scl-internal-delay-ns = <110>;
405 status = "disabled";
406 };
407
408 i2c6: i2c@e66e8000 {
409 #address-cells = <1>;
410 #size-cells = <0>;
411 compatible = "renesas,i2c-r8a774a1",
412 "renesas,rcar-gen3-i2c";
413 reg = <0 0xe66e8000 0 0x40>;
414 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&cpg CPG_MOD 918>;
416 power-domains = <&sysc 32>;
417 resets = <&cpg 918>;
418 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
419 dma-names = "tx", "rx";
420 i2c-scl-internal-delay-ns = <6>;
421 status = "disabled";
422 };
423
424 i2c_dvfs: i2c@e60b0000 {
425 #address-cells = <1>;
426 #size-cells = <0>;
427 compatible = "renesas,iic-r8a774a1",
428 "renesas,rcar-gen3-iic",
429 "renesas,rmobile-iic";
430 reg = <0 0xe60b0000 0 0x425>;
431 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
432 clocks = <&cpg CPG_MOD 926>;
433 power-domains = <&sysc 32>;
434 resets = <&cpg 926>;
435 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
436 dma-names = "tx", "rx";
437 status = "disabled";
438 };
439
3a3933a4
FC		 440 hscif0: serial@e6540000 {
441 compatible = "renesas,hscif-r8a774a1",
442 "renesas,rcar-gen3-hscif",
443 "renesas,hscif";
444 reg = <0 0xe6540000 0 0x60>;
445 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&cpg CPG_MOD 520>,
447 <&cpg CPG_CORE 19>,
448 <&scif_clk>;
449 clock-names = "fck", "brg_int", "scif_clk";
450 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
451 <&dmac2 0x31>, <&dmac2 0x30>;
452 dma-names = "tx", "rx", "tx", "rx";
453 power-domains = <&sysc 32>;
454 resets = <&cpg 520>;
455 status = "disabled";
456 };
457
458 hscif1: serial@e6550000 {
459 compatible = "renesas,hscif-r8a774a1",
460 "renesas,rcar-gen3-hscif",
461 "renesas,hscif";
462 reg = <0 0xe6550000 0 0x60>;
463 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
464 clocks = <&cpg CPG_MOD 519>,
465 <&cpg CPG_CORE 19>,
466 <&scif_clk>;
467 clock-names = "fck", "brg_int", "scif_clk";
468 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
469 <&dmac2 0x33>, <&dmac2 0x32>;
470 dma-names = "tx", "rx", "tx", "rx";
471 power-domains = <&sysc 32>;
472 resets = <&cpg 519>;
473 status = "disabled";
474 };
475
476 hscif2: serial@e6560000 {
477 compatible = "renesas,hscif-r8a774a1",
478 "renesas,rcar-gen3-hscif",
479 "renesas,hscif";
480 reg = <0 0xe6560000 0 0x60>;
481 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&cpg CPG_MOD 518>,
483 <&cpg CPG_CORE 19>,
484 <&scif_clk>;
485 clock-names = "fck", "brg_int", "scif_clk";
486 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
487 <&dmac2 0x35>, <&dmac2 0x34>;
488 dma-names = "tx", "rx", "tx", "rx";
489 power-domains = <&sysc 32>;
490 resets = <&cpg 518>;
491 status = "disabled";
492 };
493
494 hscif3: serial@e66a0000 {
495 compatible = "renesas,hscif-r8a774a1",
496 "renesas,rcar-gen3-hscif",
497 "renesas,hscif";
498 reg = <0 0xe66a0000 0 0x60>;
499 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
500 clocks = <&cpg CPG_MOD 517>,
501 <&cpg CPG_CORE 19>,
502 <&scif_clk>;
503 clock-names = "fck", "brg_int", "scif_clk";
504 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
505 dma-names = "tx", "rx";
506 power-domains = <&sysc 32>;
507 resets = <&cpg 517>;
508 status = "disabled";
509 };
510
511 hscif4: serial@e66b0000 {
512 compatible = "renesas,hscif-r8a774a1",
513 "renesas,rcar-gen3-hscif",
514 "renesas,hscif";
515 reg = <0 0xe66b0000 0 0x60>;
516 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&cpg CPG_MOD 516>,
518 <&cpg CPG_CORE 19>,
519 <&scif_clk>;
520 clock-names = "fck", "brg_int", "scif_clk";
521 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
522 dma-names = "tx", "rx";
523 power-domains = <&sysc 32>;
524 resets = <&cpg 516>;
525 status = "disabled";
526 };
527
37a61e4d
BD		 528 dmac0: dma-controller@e6700000 {
529 compatible = "renesas,dmac-r8a774a1",
530 "renesas,rcar-dmac";
531 reg = <0 0xe6700000 0 0x10000>;
532 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
533 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
534 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
535 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
536 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
537 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
538 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
539 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
540 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
541 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
542 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
543 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
544 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
545 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
546 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
547 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
548 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
549 interrupt-names = "error",
550 "ch0", "ch1", "ch2", "ch3",
551 "ch4", "ch5", "ch6", "ch7",
552 "ch8", "ch9", "ch10", "ch11",
553 "ch12", "ch13", "ch14", "ch15";
554 clocks = <&cpg CPG_MOD 219>;
555 clock-names = "fck";
556 power-domains = <&sysc 32>;
557 resets = <&cpg 219>;
558 #dma-cells = <1>;
559 dma-channels = <16>;
560 };
561
562 dmac1: dma-controller@e7300000 {
563 compatible = "renesas,dmac-r8a774a1",
564 "renesas,rcar-dmac";
565 reg = <0 0xe7300000 0 0x10000>;
566 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
567 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
568 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
569 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
570 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
571 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
572 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
573 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
574 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
575 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
576 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
577 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
578 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
579 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
580 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
581 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
582 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
583 interrupt-names = "error",
584 "ch0", "ch1", "ch2", "ch3",
585 "ch4", "ch5", "ch6", "ch7",
586 "ch8", "ch9", "ch10", "ch11",
587 "ch12", "ch13", "ch14", "ch15";
588 clocks = <&cpg CPG_MOD 218>;
589 clock-names = "fck";
590 power-domains = <&sysc 32>;
591 resets = <&cpg 218>;
592 #dma-cells = <1>;
593 dma-channels = <16>;
594 };
595
596 dmac2: dma-controller@e7310000 {
597 compatible = "renesas,dmac-r8a774a1",
598 "renesas,rcar-dmac";
599 reg = <0 0xe7310000 0 0x10000>;
600 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
601 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
602 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
603 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
604 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
605 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
606 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
607 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
608 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
609 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
610 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
611 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
612 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
613 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
614 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
615 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
616 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
617 interrupt-names = "error",
618 "ch0", "ch1", "ch2", "ch3",
619 "ch4", "ch5", "ch6", "ch7",
620 "ch8", "ch9", "ch10", "ch11",
621 "ch12", "ch13", "ch14", "ch15";
622 clocks = <&cpg CPG_MOD 217>;
623 clock-names = "fck";
624 power-domains = <&sysc 32>;
625 resets = <&cpg 217>;
626 #dma-cells = <1>;
627 dma-channels = <16>;
628 };
629
71bddde2
FC		 630 avb: ethernet@e6800000 {
631 compatible = "renesas,etheravb-r8a774a1",
632 "renesas,etheravb-rcar-gen3";
633 reg = <0 0xe6800000 0 0x800>;
634 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
635 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
636 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
637 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
639 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
640 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
641 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
642 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
643 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
644 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
645 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
646 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
647 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
648 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
649 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
656 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
657 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
659 interrupt-names = "ch0", "ch1", "ch2", "ch3",
660 "ch4", "ch5", "ch6", "ch7",
661 "ch8", "ch9", "ch10", "ch11",
662 "ch12", "ch13", "ch14", "ch15",
663 "ch16", "ch17", "ch18", "ch19",
664 "ch20", "ch21", "ch22", "ch23",
665 "ch24";
666 clocks = <&cpg CPG_MOD 812>;
667 power-domains = <&sysc 32>;
668 resets = <&cpg 812>;
669 phy-mode = "rgmii";
670 #address-cells = <1>;
671 #size-cells = <0>;
672 status = "disabled";
673 };
674
3a3933a4
FC		 675 scif0: serial@e6e60000 {
676 compatible = "renesas,scif-r8a774a1",
677 "renesas,rcar-gen3-scif", "renesas,scif";
678 reg = <0 0xe6e60000 0 0x40>;
679 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
680 clocks = <&cpg CPG_MOD 207>,
681 <&cpg CPG_CORE 19>,
682 <&scif_clk>;
683 clock-names = "fck", "brg_int", "scif_clk";
684 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
685 <&dmac2 0x51>, <&dmac2 0x50>;
686 dma-names = "tx", "rx", "tx", "rx";
687 power-domains = <&sysc 32>;
688 resets = <&cpg 207>;
689 status = "disabled";
690 };
691
692 scif1: serial@e6e68000 {
693 compatible = "renesas,scif-r8a774a1",
694 "renesas,rcar-gen3-scif", "renesas,scif";
695 reg = <0 0xe6e68000 0 0x40>;
696 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
697 clocks = <&cpg CPG_MOD 206>,
698 <&cpg CPG_CORE 19>,
699 <&scif_clk>;
700 clock-names = "fck", "brg_int", "scif_clk";
701 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
702 <&dmac2 0x53>, <&dmac2 0x52>;
703 dma-names = "tx", "rx", "tx", "rx";
704 power-domains = <&sysc 32>;
705 resets = <&cpg 206>;
706 status = "disabled";
707 };
708
709 scif2: serial@e6e88000 {
710 compatible = "renesas,scif-r8a774a1",
711 "renesas,rcar-gen3-scif", "renesas,scif";
712 reg = <0 0xe6e88000 0 0x40>;
713 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
714 clocks = <&cpg CPG_MOD 310>,
715 <&cpg CPG_CORE 19>,
716 <&scif_clk>;
717 clock-names = "fck", "brg_int", "scif_clk";
718 power-domains = <&sysc 32>;
719 resets = <&cpg 310>;
720 status = "disabled";
721 };
722
723 scif3: serial@e6c50000 {
724 compatible = "renesas,scif-r8a774a1",
725 "renesas,rcar-gen3-scif", "renesas,scif";
726 reg = <0 0xe6c50000 0 0x40>;
727 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
728 clocks = <&cpg CPG_MOD 204>,
729 <&cpg CPG_CORE 19>,
730 <&scif_clk>;
731 clock-names = "fck", "brg_int", "scif_clk";
732 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
733 dma-names = "tx", "rx";
734 power-domains = <&sysc 32>;
735 resets = <&cpg 204>;
736 status = "disabled";
737 };
738
739 scif4: serial@e6c40000 {
740 compatible = "renesas,scif-r8a774a1",
741 "renesas,rcar-gen3-scif", "renesas,scif";
742 reg = <0 0xe6c40000 0 0x40>;
743 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&cpg CPG_MOD 203>,
745 <&cpg CPG_CORE 19>,
746 <&scif_clk>;
747 clock-names = "fck", "brg_int", "scif_clk";
748 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
749 dma-names = "tx", "rx";
750 power-domains = <&sysc 32>;
751 resets = <&cpg 203>;
752 status = "disabled";
753 };
754
755 scif5: serial@e6f30000 {
756 compatible = "renesas,scif-r8a774a1",
757 "renesas,rcar-gen3-scif", "renesas,scif";
758 reg = <0 0xe6f30000 0 0x40>;
759 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
760 clocks = <&cpg CPG_MOD 202>,
761 <&cpg CPG_CORE 19>,
762 <&scif_clk>;
763 clock-names = "fck", "brg_int", "scif_clk";
764 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
765 <&dmac2 0x5b>, <&dmac2 0x5a>;
766 dma-names = "tx", "rx", "tx", "rx";
767 power-domains = <&sysc 32>;
768 resets = <&cpg 202>;
769 status = "disabled";
770 };
771
663386c3
FC		 772 sdhi0: sd@ee100000 {
773 compatible = "renesas,sdhi-r8a774a1",
774 "renesas,rcar-gen3-sdhi";
775 reg = <0 0xee100000 0 0x2000>;
776 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
777 clocks = <&cpg CPG_MOD 314>;
778 max-frequency = <200000000>;
779 power-domains = <&sysc 32>;
780 resets = <&cpg 314>;
781 status = "disabled";
782 };
783
784 sdhi1: sd@ee120000 {
785 compatible = "renesas,sdhi-r8a774a1",
786 "renesas,rcar-gen3-sdhi";
787 reg = <0 0xee120000 0 0x2000>;
788 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
789 clocks = <&cpg CPG_MOD 313>;
790 max-frequency = <200000000>;
791 power-domains = <&sysc 32>;
792 resets = <&cpg 313>;
793 status = "disabled";
794 };
795
796 sdhi2: sd@ee140000 {
797 compatible = "renesas,sdhi-r8a774a1",
798 "renesas,rcar-gen3-sdhi";
799 reg = <0 0xee140000 0 0x2000>;
800 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
801 clocks = <&cpg CPG_MOD 312>;
802 max-frequency = <200000000>;
803 power-domains = <&sysc 32>;
804 resets = <&cpg 312>;
805 status = "disabled";
806 };
807
808 sdhi3: sd@ee160000 {
809 compatible = "renesas,sdhi-r8a774a1",
810 "renesas,rcar-gen3-sdhi";
811 reg = <0 0xee160000 0 0x2000>;
812 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
813 clocks = <&cpg CPG_MOD 311>;
814 max-frequency = <200000000>;
815 power-domains = <&sysc 32>;
816 resets = <&cpg 311>;
817 status = "disabled";
818 };
819
90493b09
BD		 820 gic: interrupt-controller@f1010000 {
821 compatible = "arm,gic-400";
822 #interrupt-cells = <3>;
823 #address-cells = <0>;
824 interrupt-controller;
825 reg = <0x0 0xf1010000 0 0x1000>,
826 <0x0 0xf1020000 0 0x20000>,
827 <0x0 0xf1040000 0 0x20000>,
828 <0x0 0xf1060000 0 0x20000>;
829 interrupts = <GIC_PPI 9
830 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
831 clocks = <&cpg CPG_MOD 408>;
832 clock-names = "clk";
833 power-domains = <&sysc 32>;
834 resets = <&cpg 408>;
835 };
836
837 prr: chipid@fff00044 {
838 compatible = "renesas,prr";
839 reg = <0 0xfff00044 0 4>;
840 };
841 };
842
843 timer {
844 compatible = "arm,armv8-timer";
845 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
846 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
847 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
848 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
849 };
850
851 /* External USB clocks - can be overridden by the board */
852 usb3s0_clk: usb3s0 {
853 compatible = "fixed-clock";
854 #clock-cells = <0>;
855 clock-frequency = <0>;
856 };
857
858 usb_extal_clk: usb_extal {
859 compatible = "fixed-clock";
860 #clock-cells = <0>;
861 clock-frequency = <0>;
862 };
863};
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