projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 26a7e06d SH |
1 | /* |
| 2 | * Device Tree Source for the r8a7795 SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2015 Renesas Electronics Corp. | |
| 5 | * | |
| 6 | * This file is licensed under the terms of the GNU General Public License | |
| 7 | * version 2. This program is licensed "as is" without any warranty of any | |
| 8 | * kind, whether express or implied. | |
| 9 | */ | |
| 10 | ||
| 49af46b4 | 11 | #include <dt-bindings/clock/r8a7795-cpg-mssr.h> |
| 26a7e06d | 12 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| abbecab1 | 13 | #include <dt-bindings/power/r8a7795-sysc.h> |
| 26a7e06d SH |
14 | |
| 15 | / { | |
| 16 | compatible = "renesas,r8a7795"; | |
| 17 | #address-cells = <2>; | |
| 18 | #size-cells = <2>; | |
| 19 | ||
| 32bc0c51 KM |
20 | aliases { |
| 21 | i2c0 = &i2c0; | |
| 22 | i2c1 = &i2c1; | |
| 23 | i2c2 = &i2c2; | |
| 24 | i2c3 = &i2c3; | |
| 25 | i2c4 = &i2c4; | |
| 26 | i2c5 = &i2c5; | |
| 27 | i2c6 = &i2c6; | |
| d7e0d64a | 28 | i2c7 = &i2c_dvfs; |
| 32bc0c51 KM |
29 | }; |
| 30 | ||
| 12e51557 | 31 | psci { |
| 71585040 | 32 | compatible = "arm,psci-1.0", "arm,psci-0.2"; |
| 12e51557 GI |
33 | method = "smc"; |
| 34 | }; | |
| 35 | ||
| 26a7e06d SH |
36 | cpus { |
| 37 | #address-cells = <1>; | |
| 38 | #size-cells = <0>; | |
| 39 | ||
| 26a7e06d SH |
40 | a57_0: cpu@0 { |
| 41 | compatible = "arm,cortex-a57", "arm,armv8"; | |
| 42 | reg = <0x0>; | |
| 43 | device_type = "cpu"; | |
| abbecab1 | 44 | power-domains = <&sysc R8A7795_PD_CA57_CPU0>; |
| 7b337e61 | 45 | next-level-cache = <&L2_CA57>; |
| 12e51557 | 46 | enable-method = "psci"; |
| 26a7e06d | 47 | }; |
| 0ed1a79e GI |
48 | |
| 49 | a57_1: cpu@1 { | |
| 50 | compatible = "arm,cortex-a57","arm,armv8"; | |
| 51 | reg = <0x1>; | |
| 52 | device_type = "cpu"; | |
| abbecab1 | 53 | power-domains = <&sysc R8A7795_PD_CA57_CPU1>; |
| 7b337e61 | 54 | next-level-cache = <&L2_CA57>; |
| 0ed1a79e GI |
55 | enable-method = "psci"; |
| 56 | }; | |
| a5547642 | 57 | |
| 0ed1a79e GI |
58 | a57_2: cpu@2 { |
| 59 | compatible = "arm,cortex-a57","arm,armv8"; | |
| 60 | reg = <0x2>; | |
| 61 | device_type = "cpu"; | |
| abbecab1 | 62 | power-domains = <&sysc R8A7795_PD_CA57_CPU2>; |
| 7b337e61 | 63 | next-level-cache = <&L2_CA57>; |
| 0ed1a79e GI |
64 | enable-method = "psci"; |
| 65 | }; | |
| a5547642 | 66 | |
| 0ed1a79e GI |
67 | a57_3: cpu@3 { |
| 68 | compatible = "arm,cortex-a57","arm,armv8"; | |
| 69 | reg = <0x3>; | |
| 70 | device_type = "cpu"; | |
| abbecab1 | 71 | power-domains = <&sysc R8A7795_PD_CA57_CPU3>; |
| 7b337e61 | 72 | next-level-cache = <&L2_CA57>; |
| 0ed1a79e GI |
73 | enable-method = "psci"; |
| 74 | }; | |
| 26a7e06d | 75 | |
| 799a75ab GU |
76 | a53_0: cpu@100 { |
| 77 | compatible = "arm,cortex-a53", "arm,armv8"; | |
| 78 | reg = <0x100>; | |
| 79 | device_type = "cpu"; | |
| 80 | power-domains = <&sysc R8A7795_PD_CA53_CPU0>; | |
| 81 | next-level-cache = <&L2_CA53>; | |
| 82 | enable-method = "psci"; | |
| 83 | }; | |
| 84 | ||
| 85 | a53_1: cpu@101 { | |
| 86 | compatible = "arm,cortex-a53","arm,armv8"; | |
| 87 | reg = <0x101>; | |
| 88 | device_type = "cpu"; | |
| 89 | power-domains = <&sysc R8A7795_PD_CA53_CPU1>; | |
| 90 | next-level-cache = <&L2_CA53>; | |
| 91 | enable-method = "psci"; | |
| 92 | }; | |
| 93 | ||
| 94 | a53_2: cpu@102 { | |
| 95 | compatible = "arm,cortex-a53","arm,armv8"; | |
| 96 | reg = <0x102>; | |
| 97 | device_type = "cpu"; | |
| 98 | power-domains = <&sysc R8A7795_PD_CA53_CPU2>; | |
| 99 | next-level-cache = <&L2_CA53>; | |
| 100 | enable-method = "psci"; | |
| 101 | }; | |
| 102 | ||
| 103 | a53_3: cpu@103 { | |
| 104 | compatible = "arm,cortex-a53","arm,armv8"; | |
| 105 | reg = <0x103>; | |
| 106 | device_type = "cpu"; | |
| 107 | power-domains = <&sysc R8A7795_PD_CA53_CPU3>; | |
| 108 | next-level-cache = <&L2_CA53>; | |
| 109 | enable-method = "psci"; | |
| 110 | }; | |
| 111 | ||
| d165856d | 112 | L2_CA57: cache-controller-0 { |
| 6f7bf82c | 113 | compatible = "cache"; |
| 6f7bf82c GU |
114 | power-domains = <&sysc R8A7795_PD_CA57_SCU>; |
| 115 | cache-unified; | |
| 116 | cache-level = <2>; | |
| 117 | }; | |
| 7b337e61 | 118 | |
| d165856d | 119 | L2_CA53: cache-controller-1 { |
| 6f7bf82c | 120 | compatible = "cache"; |
| 6f7bf82c GU |
121 | power-domains = <&sysc R8A7795_PD_CA53_SCU>; |
| 122 | cache-unified; | |
| 123 | cache-level = <2>; | |
| 124 | }; | |
| 8e1c3aa3 GU |
125 | }; |
| 126 | ||
| 26a7e06d SH |
127 | extal_clk: extal { |
| 128 | compatible = "fixed-clock"; | |
| 129 | #clock-cells = <0>; | |
| 130 | /* This value must be overridden by the board */ | |
| 131 | clock-frequency = <0>; | |
| 132 | }; | |
| 133 | ||
| 134 | extalr_clk: extalr { | |
| 135 | compatible = "fixed-clock"; | |
| 136 | #clock-cells = <0>; | |
| 137 | /* This value must be overridden by the board */ | |
| 138 | clock-frequency = <0>; | |
| 139 | }; | |
| 140 | ||
| 623197b9 KM |
141 | /* |
| 142 | * The external audio clocks are configured as 0 Hz fixed frequency | |
| 143 | * clocks by default. | |
| 144 | * Boards that provide audio clocks should override them. | |
| 145 | */ | |
| 146 | audio_clk_a: audio_clk_a { | |
| 147 | compatible = "fixed-clock"; | |
| 148 | #clock-cells = <0>; | |
| 149 | clock-frequency = <0>; | |
| 150 | }; | |
| 151 | ||
| 152 | audio_clk_b: audio_clk_b { | |
| 153 | compatible = "fixed-clock"; | |
| 154 | #clock-cells = <0>; | |
| 155 | clock-frequency = <0>; | |
| 156 | }; | |
| 157 | ||
| 158 | audio_clk_c: audio_clk_c { | |
| 159 | compatible = "fixed-clock"; | |
| 160 | #clock-cells = <0>; | |
| 161 | clock-frequency = <0>; | |
| 162 | }; | |
| 163 | ||
| 7811482f RS |
164 | /* External CAN clock - to be overridden by boards that provide it */ |
| 165 | can_clk: can { | |
| 166 | compatible = "fixed-clock"; | |
| 167 | #clock-cells = <0>; | |
| 168 | clock-frequency = <0>; | |
| 7811482f RS |
169 | }; |
| 170 | ||
| 3da41e4c GU |
171 | /* External SCIF clock - to be overridden by boards that provide it */ |
| 172 | scif_clk: scif { | |
| 173 | compatible = "fixed-clock"; | |
| 174 | #clock-cells = <0>; | |
| 175 | clock-frequency = <0>; | |
| 3da41e4c GU |
176 | }; |
| 177 | ||
| 9251024a PE |
178 | /* External PCIe clock - can be overridden by the board */ |
| 179 | pcie_bus_clk: pcie_bus { | |
| 180 | compatible = "fixed-clock"; | |
| 181 | #clock-cells = <0>; | |
| 9f33a8a9 | 182 | clock-frequency = <0>; |
| 9251024a PE |
183 | }; |
| 184 | ||
| 291e0c49 | 185 | soc: soc { |
| 26a7e06d SH |
186 | compatible = "simple-bus"; |
| 187 | interrupt-parent = <&gic>; | |
| 0ed1a79e | 188 | |
| 26a7e06d SH |
189 | #address-cells = <2>; |
| 190 | #size-cells = <2>; | |
| 191 | ranges; | |
| 192 | ||
| 21cc405c | 193 | gic: interrupt-controller@f1010000 { |
| 26a7e06d SH |
194 | compatible = "arm,gic-400"; |
| 195 | #interrupt-cells = <3>; | |
| 196 | #address-cells = <0>; | |
| 197 | interrupt-controller; | |
| 198 | reg = <0x0 0xf1010000 0 0x1000>, | |
| 457f47b7 | 199 | <0x0 0xf1020000 0 0x20000>, |
| 4c811edf | 200 | <0x0 0xf1040000 0 0x20000>, |
| 457f47b7 | 201 | <0x0 0xf1060000 0 0x20000>; |
| 26a7e06d | 202 | interrupts = <GIC_PPI 9 |
| 799a75ab | 203 | (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; |
| b6e56e4c GU |
204 | clocks = <&cpg CPG_MOD 408>; |
| 205 | clock-names = "clk"; | |
| 206 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| dcccc132 | 207 | resets = <&cpg 408>; |
| 26a7e06d SH |
208 | }; |
| 209 | ||
| 3114815f WS |
210 | wdt0: watchdog@e6020000 { |
| 211 | compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; | |
| 212 | reg = <0 0xe6020000 0 0x0c>; | |
| 213 | clocks = <&cpg CPG_MOD 402>; | |
| b186fbb6 | 214 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 215 | resets = <&cpg 402>; |
| 3114815f WS |
216 | status = "disabled"; |
| 217 | }; | |
| 218 | ||
| 7b08623a TK |
219 | gpio0: gpio@e6050000 { |
| 220 | compatible = "renesas,gpio-r8a7795", | |
| 221 | "renesas,gpio-rcar"; | |
| 222 | reg = <0 0xe6050000 0 0x50>; | |
| 223 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | |
| 224 | #gpio-cells = <2>; | |
| 225 | gpio-controller; | |
| 226 | gpio-ranges = <&pfc 0 0 16>; | |
| 227 | #interrupt-cells = <2>; | |
| 228 | interrupt-controller; | |
| 229 | clocks = <&cpg CPG_MOD 912>; | |
| 38dbb45e | 230 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 231 | resets = <&cpg 912>; |
| 7b08623a TK |
232 | }; |
| 233 | ||
| 234 | gpio1: gpio@e6051000 { | |
| 235 | compatible = "renesas,gpio-r8a7795", | |
| 236 | "renesas,gpio-rcar"; | |
| 237 | reg = <0 0xe6051000 0 0x50>; | |
| 238 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
| 239 | #gpio-cells = <2>; | |
| 240 | gpio-controller; | |
| 241 | gpio-ranges = <&pfc 0 32 28>; | |
| 242 | #interrupt-cells = <2>; | |
| 243 | interrupt-controller; | |
| 244 | clocks = <&cpg CPG_MOD 911>; | |
| 38dbb45e | 245 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 246 | resets = <&cpg 911>; |
| 7b08623a TK |
247 | }; |
| 248 | ||
| 249 | gpio2: gpio@e6052000 { | |
| 250 | compatible = "renesas,gpio-r8a7795", | |
| 251 | "renesas,gpio-rcar"; | |
| 252 | reg = <0 0xe6052000 0 0x50>; | |
| 253 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
| 254 | #gpio-cells = <2>; | |
| 255 | gpio-controller; | |
| 256 | gpio-ranges = <&pfc 0 64 15>; | |
| 257 | #interrupt-cells = <2>; | |
| 258 | interrupt-controller; | |
| 259 | clocks = <&cpg CPG_MOD 910>; | |
| 38dbb45e | 260 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 261 | resets = <&cpg 910>; |
| 7b08623a TK |
262 | }; |
| 263 | ||
| 264 | gpio3: gpio@e6053000 { | |
| 265 | compatible = "renesas,gpio-r8a7795", | |
| 266 | "renesas,gpio-rcar"; | |
| 267 | reg = <0 0xe6053000 0 0x50>; | |
| 268 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
| 269 | #gpio-cells = <2>; | |
| 270 | gpio-controller; | |
| 271 | gpio-ranges = <&pfc 0 96 16>; | |
| 272 | #interrupt-cells = <2>; | |
| 273 | interrupt-controller; | |
| 274 | clocks = <&cpg CPG_MOD 909>; | |
| 38dbb45e | 275 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 276 | resets = <&cpg 909>; |
| 7b08623a TK |
277 | }; |
| 278 | ||
| 279 | gpio4: gpio@e6054000 { | |
| 280 | compatible = "renesas,gpio-r8a7795", | |
| 281 | "renesas,gpio-rcar"; | |
| 282 | reg = <0 0xe6054000 0 0x50>; | |
| 283 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
| 284 | #gpio-cells = <2>; | |
| 285 | gpio-controller; | |
| 286 | gpio-ranges = <&pfc 0 128 18>; | |
| 287 | #interrupt-cells = <2>; | |
| 288 | interrupt-controller; | |
| 289 | clocks = <&cpg CPG_MOD 908>; | |
| 38dbb45e | 290 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 291 | resets = <&cpg 908>; |
| 7b08623a TK |
292 | }; |
| 293 | ||
| 294 | gpio5: gpio@e6055000 { | |
| 295 | compatible = "renesas,gpio-r8a7795", | |
| 296 | "renesas,gpio-rcar"; | |
| 297 | reg = <0 0xe6055000 0 0x50>; | |
| 298 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
| 299 | #gpio-cells = <2>; | |
| 300 | gpio-controller; | |
| 301 | gpio-ranges = <&pfc 0 160 26>; | |
| 302 | #interrupt-cells = <2>; | |
| 303 | interrupt-controller; | |
| 304 | clocks = <&cpg CPG_MOD 907>; | |
| 38dbb45e | 305 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 306 | resets = <&cpg 907>; |
| 7b08623a TK |
307 | }; |
| 308 | ||
| 309 | gpio6: gpio@e6055400 { | |
| 310 | compatible = "renesas,gpio-r8a7795", | |
| 311 | "renesas,gpio-rcar"; | |
| 312 | reg = <0 0xe6055400 0 0x50>; | |
| 313 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
| 314 | #gpio-cells = <2>; | |
| 315 | gpio-controller; | |
| 316 | gpio-ranges = <&pfc 0 192 32>; | |
| 317 | #interrupt-cells = <2>; | |
| 318 | interrupt-controller; | |
| 319 | clocks = <&cpg CPG_MOD 906>; | |
| 38dbb45e | 320 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 321 | resets = <&cpg 906>; |
| 7b08623a TK |
322 | }; |
| 323 | ||
| 324 | gpio7: gpio@e6055800 { | |
| 325 | compatible = "renesas,gpio-r8a7795", | |
| 326 | "renesas,gpio-rcar"; | |
| 327 | reg = <0 0xe6055800 0 0x50>; | |
| 328 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
| 329 | #gpio-cells = <2>; | |
| 330 | gpio-controller; | |
| 331 | gpio-ranges = <&pfc 0 224 4>; | |
| 332 | #interrupt-cells = <2>; | |
| 333 | interrupt-controller; | |
| 334 | clocks = <&cpg CPG_MOD 905>; | |
| 38dbb45e | 335 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 336 | resets = <&cpg 905>; |
| 7b08623a TK |
337 | }; |
| 338 | ||
| 3d0cd468 DB |
339 | pmu_a57 { |
| 340 | compatible = "arm,cortex-a57-pmu"; | |
| a6b6b478 YH |
341 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, |
| 342 | <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, | |
| 343 | <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, | |
| 344 | <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
| 345 | interrupt-affinity = <&a57_0>, | |
| 346 | <&a57_1>, | |
| 347 | <&a57_2>, | |
| 348 | <&a57_3>; | |
| 349 | }; | |
| 350 | ||
| 9190748f GU |
351 | pmu_a53 { |
| 352 | compatible = "arm,cortex-a53-pmu"; | |
| 353 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, | |
| 354 | <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, | |
| 355 | <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, | |
| 356 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; | |
| 357 | interrupt-affinity = <&a53_0>, | |
| 358 | <&a53_1>, | |
| 359 | <&a53_2>, | |
| 360 | <&a53_3>; | |
| 361 | }; | |
| 362 | ||
| 26a7e06d SH |
363 | timer { |
| 364 | compatible = "arm,armv8-timer"; | |
| 365 | interrupts = <GIC_PPI 13 | |
| 799a75ab | 366 | (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| 26a7e06d | 367 | <GIC_PPI 14 |
| 799a75ab | 368 | (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| 26a7e06d | 369 | <GIC_PPI 11 |
| 799a75ab | 370 | (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, |
| 26a7e06d | 371 | <GIC_PPI 10 |
| 799a75ab | 372 | (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; |
| 26a7e06d SH |
373 | }; |
| 374 | ||
| 375 | cpg: clock-controller@e6150000 { | |
| 376 | compatible = "renesas,r8a7795-cpg-mssr"; | |
| 377 | reg = <0 0xe6150000 0 0x1000>; | |
| 378 | clocks = <&extal_clk>, <&extalr_clk>; | |
| 379 | clock-names = "extal", "extalr"; | |
| 380 | #clock-cells = <2>; | |
| 381 | #power-domain-cells = <0>; | |
| dcccc132 | 382 | #reset-cells = <1>; |
| 26a7e06d | 383 | }; |
| d9202126 | 384 | |
| 6ddbb4ce GU |
385 | rst: reset-controller@e6160000 { |
| 386 | compatible = "renesas,r8a7795-rst"; | |
| 387 | reg = <0 0xe6160000 0 0x0200>; | |
| 388 | }; | |
| 389 | ||
| bd6777f8 GU |
390 | prr: chipid@fff00044 { |
| 391 | compatible = "renesas,prr"; | |
| 392 | reg = <0 0xfff00044 0 4>; | |
| 393 | }; | |
| 394 | ||
| abbecab1 GU |
395 | sysc: system-controller@e6180000 { |
| 396 | compatible = "renesas,r8a7795-sysc"; | |
| 397 | reg = <0 0xe6180000 0 0x0400>; | |
| 398 | #power-domain-cells = <1>; | |
| 399 | }; | |
| 400 | ||
| 3e7a5b3c | 401 | pfc: pin-controller@e6060000 { |
| 9241844a KM |
402 | compatible = "renesas,pfc-r8a7795"; |
| 403 | reg = <0 0xe6060000 0 0x50c>; | |
| 404 | }; | |
| 405 | ||
| 9c6c053c MD |
406 | intc_ex: interrupt-controller@e61c0000 { |
| 407 | compatible = "renesas,intc-ex-r8a7795", "renesas,irqc"; | |
| 408 | #interrupt-cells = <2>; | |
| 409 | interrupt-controller; | |
| 410 | reg = <0 0xe61c0000 0 0x200>; | |
| 411 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH | |
| 412 | GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH | |
| 413 | GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH | |
| 414 | GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH | |
| 415 | GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH | |
| 416 | GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; | |
| 417 | clocks = <&cpg CPG_MOD 407>; | |
| 38dbb45e | 418 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 419 | resets = <&cpg 407>; |
| 9c6c053c MD |
420 | }; |
| 421 | ||
| d9202126 | 422 | dmac0: dma-controller@e6700000 { |
| e2102cea GU |
423 | compatible = "renesas,dmac-r8a7795", |
| 424 | "renesas,rcar-dmac"; | |
| 425 | reg = <0 0xe6700000 0 0x10000>; | |
| 426 | interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH | |
| 427 | GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH | |
| 428 | GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH | |
| 429 | GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH | |
| 430 | GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH | |
| 431 | GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH | |
| 432 | GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH | |
| 433 | GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH | |
| 434 | GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH | |
| 435 | GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH | |
| 436 | GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH | |
| 437 | GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH | |
| 438 | GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH | |
| 439 | GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH | |
| 440 | GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH | |
| 441 | GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH | |
| 442 | GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; | |
| 443 | interrupt-names = "error", | |
| 444 | "ch0", "ch1", "ch2", "ch3", | |
| 445 | "ch4", "ch5", "ch6", "ch7", | |
| 446 | "ch8", "ch9", "ch10", "ch11", | |
| 447 | "ch12", "ch13", "ch14", "ch15"; | |
| 448 | clocks = <&cpg CPG_MOD 219>; | |
| 449 | clock-names = "fck"; | |
| 38dbb45e | 450 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 451 | resets = <&cpg 219>; |
| e2102cea GU |
452 | #dma-cells = <1>; |
| 453 | dma-channels = <16>; | |
| d9202126 GU |
454 | }; |
| 455 | ||
| 456 | dmac1: dma-controller@e7300000 { | |
| e2102cea GU |
457 | compatible = "renesas,dmac-r8a7795", |
| 458 | "renesas,rcar-dmac"; | |
| 459 | reg = <0 0xe7300000 0 0x10000>; | |
| 460 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH | |
| 461 | GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH | |
| 462 | GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH | |
| 463 | GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH | |
| 464 | GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH | |
| 465 | GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH | |
| 466 | GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH | |
| 467 | GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH | |
| 468 | GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH | |
| 469 | GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH | |
| 470 | GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH | |
| 471 | GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH | |
| 472 | GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH | |
| 473 | GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH | |
| 474 | GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH | |
| 475 | GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH | |
| 476 | GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; | |
| 477 | interrupt-names = "error", | |
| 478 | "ch0", "ch1", "ch2", "ch3", | |
| 479 | "ch4", "ch5", "ch6", "ch7", | |
| 480 | "ch8", "ch9", "ch10", "ch11", | |
| 481 | "ch12", "ch13", "ch14", "ch15"; | |
| 482 | clocks = <&cpg CPG_MOD 218>; | |
| 483 | clock-names = "fck"; | |
| 38dbb45e | 484 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 485 | resets = <&cpg 218>; |
| e2102cea GU |
486 | #dma-cells = <1>; |
| 487 | dma-channels = <16>; | |
| d9202126 GU |
488 | }; |
| 489 | ||
| 490 | dmac2: dma-controller@e7310000 { | |
| e2102cea GU |
491 | compatible = "renesas,dmac-r8a7795", |
| 492 | "renesas,rcar-dmac"; | |
| 493 | reg = <0 0xe7310000 0 0x10000>; | |
| 494 | interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH | |
| 495 | GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH | |
| 496 | GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH | |
| 497 | GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH | |
| 498 | GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH | |
| 499 | GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH | |
| 500 | GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH | |
| 501 | GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH | |
| 502 | GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH | |
| 503 | GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH | |
| 504 | GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH | |
| 505 | GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH | |
| 506 | GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH | |
| 507 | GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH | |
| 508 | GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH | |
| 509 | GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH | |
| 510 | GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; | |
| 511 | interrupt-names = "error", | |
| 512 | "ch0", "ch1", "ch2", "ch3", | |
| 513 | "ch4", "ch5", "ch6", "ch7", | |
| 514 | "ch8", "ch9", "ch10", "ch11", | |
| 515 | "ch12", "ch13", "ch14", "ch15"; | |
| 516 | clocks = <&cpg CPG_MOD 217>; | |
| 517 | clock-names = "fck"; | |
| 38dbb45e | 518 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 519 | resets = <&cpg 217>; |
| 769fa836 KM |
520 | #dma-cells = <1>; |
| 521 | dma-channels = <16>; | |
| 522 | }; | |
| 523 | ||
| 524 | audma0: dma-controller@ec700000 { | |
| 525 | compatible = "renesas,dmac-r8a7795", | |
| 526 | "renesas,rcar-dmac"; | |
| 527 | reg = <0 0xec700000 0 0x10000>; | |
| 528 | interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH | |
| 529 | GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH | |
| 530 | GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH | |
| 531 | GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH | |
| 532 | GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH | |
| 533 | GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH | |
| 534 | GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH | |
| 535 | GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH | |
| 536 | GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH | |
| 537 | GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH | |
| 538 | GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH | |
| 539 | GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH | |
| 540 | GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH | |
| 541 | GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH | |
| 542 | GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH | |
| 543 | GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH | |
| 544 | GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; | |
| 545 | interrupt-names = "error", | |
| 546 | "ch0", "ch1", "ch2", "ch3", | |
| 547 | "ch4", "ch5", "ch6", "ch7", | |
| 548 | "ch8", "ch9", "ch10", "ch11", | |
| 549 | "ch12", "ch13", "ch14", "ch15"; | |
| 550 | clocks = <&cpg CPG_MOD 502>; | |
| 551 | clock-names = "fck"; | |
| 552 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| dcccc132 | 553 | resets = <&cpg 502>; |
| 769fa836 KM |
554 | #dma-cells = <1>; |
| 555 | dma-channels = <16>; | |
| 556 | }; | |
| 557 | ||
| 558 | audma1: dma-controller@ec720000 { | |
| 559 | compatible = "renesas,dmac-r8a7795", | |
| 560 | "renesas,rcar-dmac"; | |
| 561 | reg = <0 0xec720000 0 0x10000>; | |
| 562 | interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH | |
| 563 | GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH | |
| 564 | GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH | |
| 565 | GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH | |
| 566 | GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH | |
| 567 | GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH | |
| 568 | GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH | |
| 569 | GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH | |
| 570 | GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH | |
| 571 | GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH | |
| 572 | GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH | |
| 573 | GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH | |
| 574 | GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH | |
| 575 | GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH | |
| 576 | GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH | |
| 577 | GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH | |
| 578 | GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; | |
| 579 | interrupt-names = "error", | |
| 580 | "ch0", "ch1", "ch2", "ch3", | |
| 581 | "ch4", "ch5", "ch6", "ch7", | |
| 582 | "ch8", "ch9", "ch10", "ch11", | |
| 583 | "ch12", "ch13", "ch14", "ch15"; | |
| 584 | clocks = <&cpg CPG_MOD 501>; | |
| 585 | clock-names = "fck"; | |
| 586 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| dcccc132 | 587 | resets = <&cpg 501>; |
| e2102cea GU |
588 | #dma-cells = <1>; |
| 589 | dma-channels = <16>; | |
| d9202126 | 590 | }; |
| 49af46b4 | 591 | |
| a92843c8 | 592 | avb: ethernet@e6800000 { |
| 2b953ccd SH |
593 | compatible = "renesas,etheravb-r8a7795", |
| 594 | "renesas,etheravb-rcar-gen3"; | |
| a92843c8 KM |
595 | reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; |
| 596 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, | |
| 597 | <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, | |
| 598 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
| 599 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, | |
| 600 | <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, | |
| 601 | <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, | |
| 602 | <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, | |
| 603 | <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, | |
| 604 | <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, | |
| 605 | <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, | |
| 606 | <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, | |
| 607 | <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, | |
| 608 | <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, | |
| 609 | <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, | |
| 610 | <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, | |
| 611 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | |
| 612 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
| 613 | <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, | |
| 614 | <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, | |
| 615 | <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, | |
| 616 | <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, | |
| 617 | <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, | |
| 618 | <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, | |
| 619 | <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, | |
| 620 | <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | |
| 621 | interrupt-names = "ch0", "ch1", "ch2", "ch3", | |
| 622 | "ch4", "ch5", "ch6", "ch7", | |
| 623 | "ch8", "ch9", "ch10", "ch11", | |
| 624 | "ch12", "ch13", "ch14", "ch15", | |
| 625 | "ch16", "ch17", "ch18", "ch19", | |
| 626 | "ch20", "ch21", "ch22", "ch23", | |
| 627 | "ch24"; | |
| 628 | clocks = <&cpg CPG_MOD 812>; | |
| 38dbb45e | 629 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 630 | resets = <&cpg 812>; |
| dda38879 | 631 | phy-mode = "rgmii-txid"; |
| a92843c8 KM |
632 | #address-cells = <1>; |
| 633 | #size-cells = <0>; | |
| 0d1390ff | 634 | status = "disabled"; |
| a92843c8 KM |
635 | }; |
| 636 | ||
| 308b7e4b RS |
637 | can0: can@e6c30000 { |
| 638 | compatible = "renesas,can-r8a7795", | |
| 639 | "renesas,rcar-gen3-can"; | |
| 640 | reg = <0 0xe6c30000 0 0x1000>; | |
| 641 | interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; | |
| 642 | clocks = <&cpg CPG_MOD 916>, | |
| 643 | <&cpg CPG_CORE R8A7795_CLK_CANFD>, | |
| 644 | <&can_clk>; | |
| 645 | clock-names = "clkp1", "clkp2", "can_clk"; | |
| 646 | assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; | |
| 647 | assigned-clock-rates = <40000000>; | |
| 38dbb45e | 648 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 649 | resets = <&cpg 916>; |
| 308b7e4b RS |
650 | status = "disabled"; |
| 651 | }; | |
| 652 | ||
| 653 | can1: can@e6c38000 { | |
| 654 | compatible = "renesas,can-r8a7795", | |
| 655 | "renesas,rcar-gen3-can"; | |
| 656 | reg = <0 0xe6c38000 0 0x1000>; | |
| 657 | interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; | |
| 658 | clocks = <&cpg CPG_MOD 915>, | |
| 659 | <&cpg CPG_CORE R8A7795_CLK_CANFD>, | |
| 660 | <&can_clk>; | |
| 661 | clock-names = "clkp1", "clkp2", "can_clk"; | |
| 662 | assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; | |
| 663 | assigned-clock-rates = <40000000>; | |
| 38dbb45e | 664 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 665 | resets = <&cpg 915>; |
| 308b7e4b RS |
666 | status = "disabled"; |
| 667 | }; | |
| 668 | ||
| 162cd784 RS |
669 | canfd: can@e66c0000 { |
| 670 | compatible = "renesas,r8a7795-canfd", | |
| 671 | "renesas,rcar-gen3-canfd"; | |
| 672 | reg = <0 0xe66c0000 0 0x8000>; | |
| 673 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, | |
| 674 | <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
| 675 | clocks = <&cpg CPG_MOD 914>, | |
| 676 | <&cpg CPG_CORE R8A7795_CLK_CANFD>, | |
| 677 | <&can_clk>; | |
| 678 | clock-names = "fck", "canfd", "can_clk"; | |
| 679 | assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; | |
| 680 | assigned-clock-rates = <40000000>; | |
| 681 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| dcccc132 | 682 | resets = <&cpg 914>; |
| 162cd784 RS |
683 | status = "disabled"; |
| 684 | ||
| 685 | channel0 { | |
| 686 | status = "disabled"; | |
| 687 | }; | |
| 688 | ||
| 689 | channel1 { | |
| 690 | status = "disabled"; | |
| 691 | }; | |
| 692 | }; | |
| 693 | ||
| 4fa04299 | 694 | hscif0: serial@e6540000 { |
| 653f502d GU |
695 | compatible = "renesas,hscif-r8a7795", |
| 696 | "renesas,rcar-gen3-hscif", | |
| 697 | "renesas,hscif"; | |
| 4fa04299 GU |
698 | reg = <0 0xe6540000 0 96>; |
| 699 | interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; | |
| 3da41e4c GU |
700 | clocks = <&cpg CPG_MOD 520>, |
| 701 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
| 702 | <&scif_clk>; | |
| 703 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 4fa04299 GU |
704 | dmas = <&dmac1 0x31>, <&dmac1 0x30>; |
| 705 | dma-names = "tx", "rx"; | |
| 38dbb45e | 706 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 707 | resets = <&cpg 520>; |
| 4fa04299 GU |
708 | status = "disabled"; |
| 709 | }; | |
| 710 | ||
| 711 | hscif1: serial@e6550000 { | |
| 653f502d GU |
712 | compatible = "renesas,hscif-r8a7795", |
| 713 | "renesas,rcar-gen3-hscif", | |
| 714 | "renesas,hscif"; | |
| 4fa04299 GU |
715 | reg = <0 0xe6550000 0 96>; |
| 716 | interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; | |
| 3da41e4c GU |
717 | clocks = <&cpg CPG_MOD 519>, |
| 718 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
| 719 | <&scif_clk>; | |
| 720 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 4fa04299 GU |
721 | dmas = <&dmac1 0x33>, <&dmac1 0x32>; |
| 722 | dma-names = "tx", "rx"; | |
| 38dbb45e | 723 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 724 | resets = <&cpg 519>; |
| 4fa04299 GU |
725 | status = "disabled"; |
| 726 | }; | |
| 727 | ||
| 728 | hscif2: serial@e6560000 { | |
| 653f502d GU |
729 | compatible = "renesas,hscif-r8a7795", |
| 730 | "renesas,rcar-gen3-hscif", | |
| 731 | "renesas,hscif"; | |
| 4fa04299 GU |
732 | reg = <0 0xe6560000 0 96>; |
| 733 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; | |
| 3da41e4c GU |
734 | clocks = <&cpg CPG_MOD 518>, |
| 735 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
| 736 | <&scif_clk>; | |
| 737 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 4fa04299 GU |
738 | dmas = <&dmac1 0x35>, <&dmac1 0x34>; |
| 739 | dma-names = "tx", "rx"; | |
| 38dbb45e | 740 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 741 | resets = <&cpg 518>; |
| 4fa04299 GU |
742 | status = "disabled"; |
| 743 | }; | |
| 744 | ||
| 745 | hscif3: serial@e66a0000 { | |
| 653f502d GU |
746 | compatible = "renesas,hscif-r8a7795", |
| 747 | "renesas,rcar-gen3-hscif", | |
| 748 | "renesas,hscif"; | |
| 4fa04299 GU |
749 | reg = <0 0xe66a0000 0 96>; |
| 750 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; | |
| 3da41e4c GU |
751 | clocks = <&cpg CPG_MOD 517>, |
| 752 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
| 753 | <&scif_clk>; | |
| 754 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 4fa04299 GU |
755 | dmas = <&dmac0 0x37>, <&dmac0 0x36>; |
| 756 | dma-names = "tx", "rx"; | |
| 38dbb45e | 757 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 758 | resets = <&cpg 517>; |
| 4fa04299 GU |
759 | status = "disabled"; |
| 760 | }; | |
| 761 | ||
| 762 | hscif4: serial@e66b0000 { | |
| 653f502d GU |
763 | compatible = "renesas,hscif-r8a7795", |
| 764 | "renesas,rcar-gen3-hscif", | |
| 765 | "renesas,hscif"; | |
| 4fa04299 GU |
766 | reg = <0 0xe66b0000 0 96>; |
| 767 | interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; | |
| 3da41e4c GU |
768 | clocks = <&cpg CPG_MOD 516>, |
| 769 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
| 770 | <&scif_clk>; | |
| 771 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 4fa04299 GU |
772 | dmas = <&dmac0 0x39>, <&dmac0 0x38>; |
| 773 | dma-names = "tx", "rx"; | |
| 38dbb45e | 774 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 775 | resets = <&cpg 516>; |
| 4fa04299 GU |
776 | status = "disabled"; |
| 777 | }; | |
| 778 | ||
| 49af46b4 | 779 | scif0: serial@e6e60000 { |
| 653f502d GU |
780 | compatible = "renesas,scif-r8a7795", |
| 781 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
| 49af46b4 GU |
782 | reg = <0 0xe6e60000 0 64>; |
| 783 | interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; | |
| 3da41e4c GU |
784 | clocks = <&cpg CPG_MOD 207>, |
| 785 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
| 786 | <&scif_clk>; | |
| 787 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 49af46b4 GU |
788 | dmas = <&dmac1 0x51>, <&dmac1 0x50>; |
| 789 | dma-names = "tx", "rx"; | |
| 38dbb45e | 790 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 791 | resets = <&cpg 207>; |
| 49af46b4 GU |
792 | status = "disabled"; |
| 793 | }; | |
| 794 | ||
| 795 | scif1: serial@e6e68000 { | |
| 653f502d GU |
796 | compatible = "renesas,scif-r8a7795", |
| 797 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
| 49af46b4 GU |
798 | reg = <0 0xe6e68000 0 64>; |
| 799 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; | |
| 3da41e4c GU |
800 | clocks = <&cpg CPG_MOD 206>, |
| 801 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
| 802 | <&scif_clk>; | |
| 803 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 49af46b4 GU |
804 | dmas = <&dmac1 0x53>, <&dmac1 0x52>; |
| 805 | dma-names = "tx", "rx"; | |
| 38dbb45e | 806 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 807 | resets = <&cpg 206>; |
| 49af46b4 GU |
808 | status = "disabled"; |
| 809 | }; | |
| 810 | ||
| 811 | scif2: serial@e6e88000 { | |
| 653f502d GU |
812 | compatible = "renesas,scif-r8a7795", |
| 813 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
| 49af46b4 GU |
814 | reg = <0 0xe6e88000 0 64>; |
| 815 | interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; | |
| 3da41e4c GU |
816 | clocks = <&cpg CPG_MOD 310>, |
| 817 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
| 818 | <&scif_clk>; | |
| 819 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 49af46b4 GU |
820 | dmas = <&dmac1 0x13>, <&dmac1 0x12>; |
| 821 | dma-names = "tx", "rx"; | |
| 38dbb45e | 822 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 823 | resets = <&cpg 310>; |
| 49af46b4 GU |
824 | status = "disabled"; |
| 825 | }; | |
| 826 | ||
| 827 | scif3: serial@e6c50000 { | |
| 653f502d GU |
828 | compatible = "renesas,scif-r8a7795", |
| 829 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
| 49af46b4 GU |
830 | reg = <0 0xe6c50000 0 64>; |
| 831 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
| 3da41e4c GU |
832 | clocks = <&cpg CPG_MOD 204>, |
| 833 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
| 834 | <&scif_clk>; | |
| 835 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 49af46b4 GU |
836 | dmas = <&dmac0 0x57>, <&dmac0 0x56>; |
| 837 | dma-names = "tx", "rx"; | |
| 38dbb45e | 838 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 839 | resets = <&cpg 204>; |
| 49af46b4 GU |
840 | status = "disabled"; |
| 841 | }; | |
| 842 | ||
| 843 | scif4: serial@e6c40000 { | |
| 653f502d GU |
844 | compatible = "renesas,scif-r8a7795", |
| 845 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
| 49af46b4 GU |
846 | reg = <0 0xe6c40000 0 64>; |
| 847 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
| 3da41e4c GU |
848 | clocks = <&cpg CPG_MOD 203>, |
| 849 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
| 850 | <&scif_clk>; | |
| 851 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 49af46b4 GU |
852 | dmas = <&dmac0 0x59>, <&dmac0 0x58>; |
| 853 | dma-names = "tx", "rx"; | |
| 38dbb45e | 854 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 855 | resets = <&cpg 203>; |
| 49af46b4 GU |
856 | status = "disabled"; |
| 857 | }; | |
| 858 | ||
| 859 | scif5: serial@e6f30000 { | |
| 653f502d GU |
860 | compatible = "renesas,scif-r8a7795", |
| 861 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
| 49af46b4 GU |
862 | reg = <0 0xe6f30000 0 64>; |
| 863 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
| 3da41e4c GU |
864 | clocks = <&cpg CPG_MOD 202>, |
| 865 | <&cpg CPG_CORE R8A7795_CLK_S3D1>, | |
| 866 | <&scif_clk>; | |
| 867 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 49af46b4 GU |
868 | dmas = <&dmac1 0x5b>, <&dmac1 0x5a>; |
| 869 | dma-names = "tx", "rx"; | |
| 38dbb45e | 870 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 871 | resets = <&cpg 202>; |
| 49af46b4 GU |
872 | status = "disabled"; |
| 873 | }; | |
| 32bc0c51 | 874 | |
| d7e0d64a KK |
875 | i2c_dvfs: i2c@e60b0000 { |
| 876 | #address-cells = <1>; | |
| 877 | #size-cells = <0>; | |
| 878 | compatible = "renesas,iic-r8a7795", | |
| 879 | "renesas,rcar-gen3-iic", | |
| 880 | "renesas,rmobile-iic"; | |
| 881 | reg = <0 0xe60b0000 0 0x425>; | |
| 882 | interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; | |
| 883 | clocks = <&cpg CPG_MOD 926>; | |
| 884 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| dcccc132 | 885 | resets = <&cpg 926>; |
| 482e565f WS |
886 | dmas = <&dmac0 0x11>, <&dmac0 0x10>; |
| 887 | dma-names = "tx", "rx"; | |
| d7e0d64a KK |
888 | status = "disabled"; |
| 889 | }; | |
| 890 | ||
| 32bc0c51 KM |
891 | i2c0: i2c@e6500000 { |
| 892 | #address-cells = <1>; | |
| 893 | #size-cells = <0>; | |
| d8ebefc9 SH |
894 | compatible = "renesas,i2c-r8a7795", |
| 895 | "renesas,rcar-gen3-i2c"; | |
| 32bc0c51 KM |
896 | reg = <0 0xe6500000 0 0x40>; |
| 897 | interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; | |
| 898 | clocks = <&cpg CPG_MOD 931>; | |
| 38dbb45e | 899 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 900 | resets = <&cpg 931>; |
| d78a1cfa NS |
901 | dmas = <&dmac1 0x91>, <&dmac1 0x90>; |
| 902 | dma-names = "tx", "rx"; | |
| 9036a730 | 903 | i2c-scl-internal-delay-ns = <110>; |
| 32bc0c51 KM |
904 | status = "disabled"; |
| 905 | }; | |
| 906 | ||
| 907 | i2c1: i2c@e6508000 { | |
| 908 | #address-cells = <1>; | |
| 909 | #size-cells = <0>; | |
| d8ebefc9 SH |
910 | compatible = "renesas,i2c-r8a7795", |
| 911 | "renesas,rcar-gen3-i2c"; | |
| 32bc0c51 KM |
912 | reg = <0 0xe6508000 0 0x40>; |
| 913 | interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; | |
| 914 | clocks = <&cpg CPG_MOD 930>; | |
| 38dbb45e | 915 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 916 | resets = <&cpg 930>; |
| d78a1cfa NS |
917 | dmas = <&dmac1 0x93>, <&dmac1 0x92>; |
| 918 | dma-names = "tx", "rx"; | |
| 9036a730 | 919 | i2c-scl-internal-delay-ns = <6>; |
| 32bc0c51 KM |
920 | status = "disabled"; |
| 921 | }; | |
| 922 | ||
| 923 | i2c2: i2c@e6510000 { | |
| 924 | #address-cells = <1>; | |
| 925 | #size-cells = <0>; | |
| d8ebefc9 SH |
926 | compatible = "renesas,i2c-r8a7795", |
| 927 | "renesas,rcar-gen3-i2c"; | |
| 32bc0c51 KM |
928 | reg = <0 0xe6510000 0 0x40>; |
| 929 | interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; | |
| 930 | clocks = <&cpg CPG_MOD 929>; | |
| 38dbb45e | 931 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 932 | resets = <&cpg 929>; |
| d78a1cfa NS |
933 | dmas = <&dmac1 0x95>, <&dmac1 0x94>; |
| 934 | dma-names = "tx", "rx"; | |
| 9036a730 | 935 | i2c-scl-internal-delay-ns = <6>; |
| 32bc0c51 KM |
936 | status = "disabled"; |
| 937 | }; | |
| 938 | ||
| 939 | i2c3: i2c@e66d0000 { | |
| 940 | #address-cells = <1>; | |
| 941 | #size-cells = <0>; | |
| d8ebefc9 SH |
942 | compatible = "renesas,i2c-r8a7795", |
| 943 | "renesas,rcar-gen3-i2c"; | |
| 32bc0c51 KM |
944 | reg = <0 0xe66d0000 0 0x40>; |
| 945 | interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; | |
| 946 | clocks = <&cpg CPG_MOD 928>; | |
| 38dbb45e | 947 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 948 | resets = <&cpg 928>; |
| d78a1cfa NS |
949 | dmas = <&dmac0 0x97>, <&dmac0 0x96>; |
| 950 | dma-names = "tx", "rx"; | |
| 9036a730 | 951 | i2c-scl-internal-delay-ns = <110>; |
| 32bc0c51 KM |
952 | status = "disabled"; |
| 953 | }; | |
| 954 | ||
| 955 | i2c4: i2c@e66d8000 { | |
| 956 | #address-cells = <1>; | |
| 957 | #size-cells = <0>; | |
| d8ebefc9 SH |
958 | compatible = "renesas,i2c-r8a7795", |
| 959 | "renesas,rcar-gen3-i2c"; | |
| 32bc0c51 KM |
960 | reg = <0 0xe66d8000 0 0x40>; |
| 961 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; | |
| 962 | clocks = <&cpg CPG_MOD 927>; | |
| 38dbb45e | 963 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 964 | resets = <&cpg 927>; |
| d78a1cfa NS |
965 | dmas = <&dmac0 0x99>, <&dmac0 0x98>; |
| 966 | dma-names = "tx", "rx"; | |
| 9036a730 | 967 | i2c-scl-internal-delay-ns = <110>; |
| 32bc0c51 KM |
968 | status = "disabled"; |
| 969 | }; | |
| 970 | ||
| 971 | i2c5: i2c@e66e0000 { | |
| 972 | #address-cells = <1>; | |
| 973 | #size-cells = <0>; | |
| d8ebefc9 SH |
974 | compatible = "renesas,i2c-r8a7795", |
| 975 | "renesas,rcar-gen3-i2c"; | |
| 32bc0c51 KM |
976 | reg = <0 0xe66e0000 0 0x40>; |
| 977 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
| 978 | clocks = <&cpg CPG_MOD 919>; | |
| 38dbb45e | 979 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 980 | resets = <&cpg 919>; |
| d78a1cfa NS |
981 | dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; |
| 982 | dma-names = "tx", "rx"; | |
| 9036a730 | 983 | i2c-scl-internal-delay-ns = <110>; |
| 32bc0c51 KM |
984 | status = "disabled"; |
| 985 | }; | |
| 986 | ||
| 987 | i2c6: i2c@e66e8000 { | |
| 988 | #address-cells = <1>; | |
| 989 | #size-cells = <0>; | |
| d8ebefc9 SH |
990 | compatible = "renesas,i2c-r8a7795", |
| 991 | "renesas,rcar-gen3-i2c"; | |
| 32bc0c51 KM |
992 | reg = <0 0xe66e8000 0 0x40>; |
| 993 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
| 994 | clocks = <&cpg CPG_MOD 918>; | |
| 38dbb45e | 995 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 996 | resets = <&cpg 918>; |
| d78a1cfa NS |
997 | dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; |
| 998 | dma-names = "tx", "rx"; | |
| 9036a730 | 999 | i2c-scl-internal-delay-ns = <6>; |
| 32bc0c51 KM |
1000 | status = "disabled"; |
| 1001 | }; | |
| 623197b9 | 1002 | |
| b2b9443b LP |
1003 | pwm0: pwm@e6e30000 { |
| 1004 | compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; | |
| 1005 | reg = <0 0xe6e30000 0 0x8>; | |
| 1006 | clocks = <&cpg CPG_MOD 523>; | |
| 1007 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| dcccc132 | 1008 | resets = <&cpg 523>; |
| b2b9443b LP |
1009 | #pwm-cells = <2>; |
| 1010 | status = "disabled"; | |
| 1011 | }; | |
| 1012 | ||
| 1013 | pwm1: pwm@e6e31000 { | |
| 1014 | compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; | |
| 1015 | reg = <0 0xe6e31000 0 0x8>; | |
| 1016 | clocks = <&cpg CPG_MOD 523>; | |
| 1017 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| dcccc132 | 1018 | resets = <&cpg 523>; |
| b2b9443b LP |
1019 | #pwm-cells = <2>; |
| 1020 | status = "disabled"; | |
| 1021 | }; | |
| 1022 | ||
| 1023 | pwm2: pwm@e6e32000 { | |
| 1024 | compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; | |
| 1025 | reg = <0 0xe6e32000 0 0x8>; | |
| 1026 | clocks = <&cpg CPG_MOD 523>; | |
| 1027 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| dcccc132 | 1028 | resets = <&cpg 523>; |
| b2b9443b LP |
1029 | #pwm-cells = <2>; |
| 1030 | status = "disabled"; | |
| 1031 | }; | |
| 1032 | ||
| 1033 | pwm3: pwm@e6e33000 { | |
| 1034 | compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; | |
| 1035 | reg = <0 0xe6e33000 0 0x8>; | |
| 1036 | clocks = <&cpg CPG_MOD 523>; | |
| 1037 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| dcccc132 | 1038 | resets = <&cpg 523>; |
| b2b9443b LP |
1039 | #pwm-cells = <2>; |
| 1040 | status = "disabled"; | |
| 1041 | }; | |
| 1042 | ||
| 1043 | pwm4: pwm@e6e34000 { | |
| 1044 | compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; | |
| 1045 | reg = <0 0xe6e34000 0 0x8>; | |
| 1046 | clocks = <&cpg CPG_MOD 523>; | |
| 1047 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| dcccc132 | 1048 | resets = <&cpg 523>; |
| b2b9443b LP |
1049 | #pwm-cells = <2>; |
| 1050 | status = "disabled"; | |
| 1051 | }; | |
| 1052 | ||
| 1053 | pwm5: pwm@e6e35000 { | |
| 1054 | compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; | |
| 1055 | reg = <0 0xe6e35000 0 0x8>; | |
| 1056 | clocks = <&cpg CPG_MOD 523>; | |
| 1057 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| dcccc132 | 1058 | resets = <&cpg 523>; |
| b2b9443b LP |
1059 | #pwm-cells = <2>; |
| 1060 | status = "disabled"; | |
| 1061 | }; | |
| 1062 | ||
| 1063 | pwm6: pwm@e6e36000 { | |
| 1064 | compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; | |
| 1065 | reg = <0 0xe6e36000 0 0x8>; | |
| 1066 | clocks = <&cpg CPG_MOD 523>; | |
| 1067 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| dcccc132 | 1068 | resets = <&cpg 523>; |
| b2b9443b LP |
1069 | #pwm-cells = <2>; |
| 1070 | status = "disabled"; | |
| 1071 | }; | |
| 1072 | ||
| 623197b9 KM |
1073 | rcar_sound: sound@ec500000 { |
| 1074 | /* | |
| 1075 | * #sound-dai-cells is required | |
| 1076 | * | |
| 1077 | * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; | |
| 1078 | * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; | |
| 1079 | */ | |
| 1080 | /* | |
| 1081 | * #clock-cells is required for audio_clkout0/1/2/3 | |
| 1082 | * | |
| 1083 | * clkout : #clock-cells = <0>; <&rcar_sound>; | |
| 1084 | * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; | |
| 1085 | */ | |
| 1086 | compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3"; | |
| 1087 | reg = <0 0xec500000 0 0x1000>, /* SCU */ | |
| 1088 | <0 0xec5a0000 0 0x100>, /* ADG */ | |
| 1089 | <0 0xec540000 0 0x1000>, /* SSIU */ | |
| 1090 | <0 0xec541000 0 0x280>, /* SSI */ | |
| 1091 | <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ | |
| 1092 | reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; | |
| 1093 | ||
| 1094 | clocks = <&cpg CPG_MOD 1005>, | |
| 1095 | <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, | |
| 1096 | <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, | |
| 1097 | <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, | |
| 1098 | <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, | |
| 1099 | <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, | |
| b868ff51 KM |
1100 | <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, |
| 1101 | <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, | |
| 1102 | <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, | |
| 1103 | <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, | |
| 1104 | <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, | |
| c9293d78 | 1105 | <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, |
| ad5805f3 | 1106 | <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, |
| b9dd9450 | 1107 | <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, |
| 623197b9 KM |
1108 | <&audio_clk_a>, <&audio_clk_b>, |
| 1109 | <&audio_clk_c>, | |
| 1110 | <&cpg CPG_CORE R8A7795_CLK_S0D4>; | |
| 1111 | clock-names = "ssi-all", | |
| 1112 | "ssi.9", "ssi.8", "ssi.7", "ssi.6", | |
| 1113 | "ssi.5", "ssi.4", "ssi.3", "ssi.2", | |
| 1114 | "ssi.1", "ssi.0", | |
| b868ff51 KM |
1115 | "src.9", "src.8", "src.7", "src.6", |
| 1116 | "src.5", "src.4", "src.3", "src.2", | |
| 1117 | "src.1", "src.0", | |
| ad5805f3 | 1118 | "mix.1", "mix.0", |
| c9293d78 | 1119 | "ctu.1", "ctu.0", |
| b9dd9450 | 1120 | "dvc.0", "dvc.1", |
| 623197b9 | 1121 | "clk_a", "clk_b", "clk_c", "clk_i"; |
| 38dbb45e | 1122 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| 623197b9 KM |
1123 | status = "disabled"; |
| 1124 | ||
| b9dd9450 | 1125 | rcar_sound,dvc { |
| 6f7bf82c | 1126 | dvc0: dvc-0 { |
| b5a8ffad | 1127 | dmas = <&audma1 0xbc>; |
| b9dd9450 KM |
1128 | dma-names = "tx"; |
| 1129 | }; | |
| 6f7bf82c | 1130 | dvc1: dvc-1 { |
| b5a8ffad | 1131 | dmas = <&audma1 0xbe>; |
| b9dd9450 KM |
1132 | dma-names = "tx"; |
| 1133 | }; | |
| 1134 | }; | |
| 1135 | ||
| ad5805f3 KM |
1136 | rcar_sound,mix { |
| 1137 | mix0: mix-0 { }; | |
| 1138 | mix1: mix-1 { }; | |
| 1139 | }; | |
| 1140 | ||
| c9293d78 KM |
1141 | rcar_sound,ctu { |
| 1142 | ctu00: ctu-0 { }; | |
| 1143 | ctu01: ctu-1 { }; | |
| 1144 | ctu02: ctu-2 { }; | |
| 1145 | ctu03: ctu-3 { }; | |
| 1146 | ctu10: ctu-4 { }; | |
| 1147 | ctu11: ctu-5 { }; | |
| 1148 | ctu12: ctu-6 { }; | |
| 1149 | ctu13: ctu-7 { }; | |
| 1150 | }; | |
| 1151 | ||
| b868ff51 | 1152 | rcar_sound,src { |
| 6f7bf82c | 1153 | src0: src-0 { |
| 52b541ab | 1154 | interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; |
| b868ff51 KM |
1155 | dmas = <&audma0 0x85>, <&audma1 0x9a>; |
| 1156 | dma-names = "rx", "tx"; | |
| 1157 | }; | |
| 6f7bf82c | 1158 | src1: src-1 { |
| 52b541ab | 1159 | interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
| b868ff51 KM |
1160 | dmas = <&audma0 0x87>, <&audma1 0x9c>; |
| 1161 | dma-names = "rx", "tx"; | |
| 1162 | }; | |
| 6f7bf82c | 1163 | src2: src-2 { |
| 52b541ab | 1164 | interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
| b868ff51 KM |
1165 | dmas = <&audma0 0x89>, <&audma1 0x9e>; |
| 1166 | dma-names = "rx", "tx"; | |
| 1167 | }; | |
| 6f7bf82c | 1168 | src3: src-3 { |
| 52b541ab | 1169 | interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
| b868ff51 KM |
1170 | dmas = <&audma0 0x8b>, <&audma1 0xa0>; |
| 1171 | dma-names = "rx", "tx"; | |
| 1172 | }; | |
| 6f7bf82c | 1173 | src4: src-4 { |
| 52b541ab | 1174 | interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
| b868ff51 KM |
1175 | dmas = <&audma0 0x8d>, <&audma1 0xb0>; |
| 1176 | dma-names = "rx", "tx"; | |
| 1177 | }; | |
| 6f7bf82c | 1178 | src5: src-5 { |
| 52b541ab | 1179 | interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
| b868ff51 KM |
1180 | dmas = <&audma0 0x8f>, <&audma1 0xb2>; |
| 1181 | dma-names = "rx", "tx"; | |
| 1182 | }; | |
| 6f7bf82c | 1183 | src6: src-6 { |
| 52b541ab | 1184 | interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
| b868ff51 KM |
1185 | dmas = <&audma0 0x91>, <&audma1 0xb4>; |
| 1186 | dma-names = "rx", "tx"; | |
| 1187 | }; | |
| 6f7bf82c | 1188 | src7: src-7 { |
| 52b541ab | 1189 | interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; |
| b868ff51 KM |
1190 | dmas = <&audma0 0x93>, <&audma1 0xb6>; |
| 1191 | dma-names = "rx", "tx"; | |
| 1192 | }; | |
| 6f7bf82c | 1193 | src8: src-8 { |
| 52b541ab | 1194 | interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; |
| b868ff51 KM |
1195 | dmas = <&audma0 0x95>, <&audma1 0xb8>; |
| 1196 | dma-names = "rx", "tx"; | |
| 1197 | }; | |
| 6f7bf82c | 1198 | src9: src-9 { |
| 52b541ab | 1199 | interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; |
| b868ff51 KM |
1200 | dmas = <&audma0 0x97>, <&audma1 0xba>; |
| 1201 | dma-names = "rx", "tx"; | |
| 1202 | }; | |
| 1203 | }; | |
| 1204 | ||
| 623197b9 | 1205 | rcar_sound,ssi { |
| 6f7bf82c | 1206 | ssi0: ssi-0 { |
| 52b541ab | 1207 | interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; |
| 10d18ab8 KM |
1208 | dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; |
| 1209 | dma-names = "rx", "tx", "rxu", "txu"; | |
| 623197b9 | 1210 | }; |
| 6f7bf82c | 1211 | ssi1: ssi-1 { |
| 52b541ab | 1212 | interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; |
| 10d18ab8 KM |
1213 | dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; |
| 1214 | dma-names = "rx", "tx", "rxu", "txu"; | |
| 623197b9 | 1215 | }; |
| 6f7bf82c | 1216 | ssi2: ssi-2 { |
| 52b541ab | 1217 | interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; |
| 10d18ab8 KM |
1218 | dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; |
| 1219 | dma-names = "rx", "tx", "rxu", "txu"; | |
| 623197b9 | 1220 | }; |
| 6f7bf82c | 1221 | ssi3: ssi-3 { |
| 52b541ab | 1222 | interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; |
| 10d18ab8 KM |
1223 | dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; |
| 1224 | dma-names = "rx", "tx", "rxu", "txu"; | |
| 623197b9 | 1225 | }; |
| 6f7bf82c | 1226 | ssi4: ssi-4 { |
| 52b541ab | 1227 | interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; |
| 10d18ab8 KM |
1228 | dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; |
| 1229 | dma-names = "rx", "tx", "rxu", "txu"; | |
| 623197b9 | 1230 | }; |
| 6f7bf82c | 1231 | ssi5: ssi-5 { |
| 52b541ab | 1232 | interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; |
| 10d18ab8 KM |
1233 | dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; |
| 1234 | dma-names = "rx", "tx", "rxu", "txu"; | |
| 623197b9 | 1235 | }; |
| 6f7bf82c | 1236 | ssi6: ssi-6 { |
| 52b541ab | 1237 | interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; |
| 10d18ab8 KM |
1238 | dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; |
| 1239 | dma-names = "rx", "tx", "rxu", "txu"; | |
| 623197b9 | 1240 | }; |
| 6f7bf82c | 1241 | ssi7: ssi-7 { |
| 52b541ab | 1242 | interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; |
| 10d18ab8 KM |
1243 | dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; |
| 1244 | dma-names = "rx", "tx", "rxu", "txu"; | |
| 623197b9 | 1245 | }; |
| 6f7bf82c | 1246 | ssi8: ssi-8 { |
| 52b541ab | 1247 | interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; |
| 10d18ab8 KM |
1248 | dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; |
| 1249 | dma-names = "rx", "tx", "rxu", "txu"; | |
| 623197b9 | 1250 | }; |
| 6f7bf82c | 1251 | ssi9: ssi-9 { |
| 52b541ab | 1252 | interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; |
| 10d18ab8 KM |
1253 | dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; |
| 1254 | dma-names = "rx", "tx", "rxu", "txu"; | |
| 623197b9 KM |
1255 | }; |
| 1256 | }; | |
| 1257 | }; | |
| 4c13472b KA |
1258 | |
| 1259 | sata: sata@ee300000 { | |
| 1260 | compatible = "renesas,sata-r8a7795"; | |
| e9f0089b | 1261 | reg = <0 0xee300000 0 0x200000>; |
| 4c13472b | 1262 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
| 2eb2b506 | 1263 | clocks = <&cpg CPG_MOD 815>; |
| 2cab226c | 1264 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1265 | resets = <&cpg 815>; |
| 4c13472b KA |
1266 | status = "disabled"; |
| 1267 | }; | |
| 171f2ef8 YS |
1268 | |
| 1269 | xhci0: usb@ee000000 { | |
| 81ae0ac3 | 1270 | compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; |
| 171f2ef8 YS |
1271 | reg = <0 0xee000000 0 0xc00>; |
| 1272 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; | |
| 1273 | clocks = <&cpg CPG_MOD 328>; | |
| 38dbb45e | 1274 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1275 | resets = <&cpg 328>; |
| 171f2ef8 YS |
1276 | status = "disabled"; |
| 1277 | }; | |
| 1278 | ||
| 652a4306 YS |
1279 | usb_dmac0: dma-controller@e65a0000 { |
| 1280 | compatible = "renesas,r8a7795-usb-dmac", | |
| 1281 | "renesas,usb-dmac"; | |
| 1282 | reg = <0 0xe65a0000 0 0x100>; | |
| 1283 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH | |
| 1284 | GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; | |
| 1285 | interrupt-names = "ch0", "ch1"; | |
| 1286 | clocks = <&cpg CPG_MOD 330>; | |
| 38dbb45e | 1287 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1288 | resets = <&cpg 330>; |
| 652a4306 YS |
1289 | #dma-cells = <1>; |
| 1290 | dma-channels = <2>; | |
| 1291 | }; | |
| 1292 | ||
| 1293 | usb_dmac1: dma-controller@e65b0000 { | |
| 1294 | compatible = "renesas,r8a7795-usb-dmac", | |
| 1295 | "renesas,usb-dmac"; | |
| 1296 | reg = <0 0xe65b0000 0 0x100>; | |
| 1297 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH | |
| 1298 | GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; | |
| 1299 | interrupt-names = "ch0", "ch1"; | |
| 1300 | clocks = <&cpg CPG_MOD 331>; | |
| 38dbb45e | 1301 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1302 | resets = <&cpg 331>; |
| 652a4306 YS |
1303 | #dma-cells = <1>; |
| 1304 | dma-channels = <2>; | |
| 1305 | }; | |
| d9d67010 AK |
1306 | |
| 1307 | sdhi0: sd@ee100000 { | |
| 1308 | compatible = "renesas,sdhi-r8a7795"; | |
| 1309 | reg = <0 0xee100000 0 0x2000>; | |
| 1310 | interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; | |
| 1311 | clocks = <&cpg CPG_MOD 314>; | |
| dcdca4d5 | 1312 | max-frequency = <200000000>; |
| 38dbb45e | 1313 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1314 | resets = <&cpg 314>; |
| d9d67010 AK |
1315 | status = "disabled"; |
| 1316 | }; | |
| 1317 | ||
| 1318 | sdhi1: sd@ee120000 { | |
| 1319 | compatible = "renesas,sdhi-r8a7795"; | |
| 1320 | reg = <0 0xee120000 0 0x2000>; | |
| 1321 | interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; | |
| 1322 | clocks = <&cpg CPG_MOD 313>; | |
| dcdca4d5 | 1323 | max-frequency = <200000000>; |
| 38dbb45e | 1324 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1325 | resets = <&cpg 313>; |
| d9d67010 AK |
1326 | status = "disabled"; |
| 1327 | }; | |
| 1328 | ||
| 1329 | sdhi2: sd@ee140000 { | |
| 1330 | compatible = "renesas,sdhi-r8a7795"; | |
| 1331 | reg = <0 0xee140000 0 0x2000>; | |
| 1332 | interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; | |
| 1333 | clocks = <&cpg CPG_MOD 312>; | |
| dcdca4d5 | 1334 | max-frequency = <200000000>; |
| 38dbb45e | 1335 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1336 | resets = <&cpg 312>; |
| d9d67010 AK |
1337 | status = "disabled"; |
| 1338 | }; | |
| 1339 | ||
| 1340 | sdhi3: sd@ee160000 { | |
| 1341 | compatible = "renesas,sdhi-r8a7795"; | |
| 1342 | reg = <0 0xee160000 0 0x2000>; | |
| 1343 | interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; | |
| 1344 | clocks = <&cpg CPG_MOD 311>; | |
| dcdca4d5 | 1345 | max-frequency = <200000000>; |
| 38dbb45e | 1346 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1347 | resets = <&cpg 311>; |
| d9d67010 AK |
1348 | status = "disabled"; |
| 1349 | }; | |
| 5923bb52 YS |
1350 | |
| 1351 | usb2_phy0: usb-phy@ee080200 { | |
| 6695092b SH |
1352 | compatible = "renesas,usb2-phy-r8a7795", |
| 1353 | "renesas,rcar-gen3-usb2-phy"; | |
| 5923bb52 YS |
1354 | reg = <0 0xee080200 0 0x700>; |
| 1355 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; | |
| 1356 | clocks = <&cpg CPG_MOD 703>; | |
| 38dbb45e | 1357 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1358 | resets = <&cpg 703>; |
| 5923bb52 YS |
1359 | #phy-cells = <0>; |
| 1360 | status = "disabled"; | |
| 1361 | }; | |
| 1362 | ||
| 1363 | usb2_phy1: usb-phy@ee0a0200 { | |
| 6695092b SH |
1364 | compatible = "renesas,usb2-phy-r8a7795", |
| 1365 | "renesas,rcar-gen3-usb2-phy"; | |
| 5923bb52 YS |
1366 | reg = <0 0xee0a0200 0 0x700>; |
| 1367 | clocks = <&cpg CPG_MOD 702>; | |
| 38dbb45e | 1368 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1369 | resets = <&cpg 702>; |
| 5923bb52 YS |
1370 | #phy-cells = <0>; |
| 1371 | status = "disabled"; | |
| 1372 | }; | |
| 1373 | ||
| 1374 | usb2_phy2: usb-phy@ee0c0200 { | |
| 6695092b SH |
1375 | compatible = "renesas,usb2-phy-r8a7795", |
| 1376 | "renesas,rcar-gen3-usb2-phy"; | |
| 5923bb52 YS |
1377 | reg = <0 0xee0c0200 0 0x700>; |
| 1378 | clocks = <&cpg CPG_MOD 701>; | |
| 38dbb45e | 1379 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1380 | resets = <&cpg 701>; |
| 5923bb52 YS |
1381 | #phy-cells = <0>; |
| 1382 | status = "disabled"; | |
| 1383 | }; | |
| a2bcdc28 YS |
1384 | |
| 1385 | ehci0: usb@ee080100 { | |
| 1386 | compatible = "generic-ehci"; | |
| 1387 | reg = <0 0xee080100 0 0x100>; | |
| 1388 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; | |
| 1389 | clocks = <&cpg CPG_MOD 703>; | |
| 1390 | phys = <&usb2_phy0>; | |
| 1391 | phy-names = "usb"; | |
| 38dbb45e | 1392 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1393 | resets = <&cpg 703>; |
| a2bcdc28 YS |
1394 | status = "disabled"; |
| 1395 | }; | |
| 1396 | ||
| 1397 | ehci1: usb@ee0a0100 { | |
| 1398 | compatible = "generic-ehci"; | |
| 1399 | reg = <0 0xee0a0100 0 0x100>; | |
| 1400 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; | |
| 1401 | clocks = <&cpg CPG_MOD 702>; | |
| 1402 | phys = <&usb2_phy1>; | |
| 1403 | phy-names = "usb"; | |
| 38dbb45e | 1404 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1405 | resets = <&cpg 702>; |
| a2bcdc28 YS |
1406 | status = "disabled"; |
| 1407 | }; | |
| 1408 | ||
| 1409 | ehci2: usb@ee0c0100 { | |
| 1410 | compatible = "generic-ehci"; | |
| 1411 | reg = <0 0xee0c0100 0 0x100>; | |
| 1412 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; | |
| 1413 | clocks = <&cpg CPG_MOD 701>; | |
| 1414 | phys = <&usb2_phy2>; | |
| 1415 | phy-names = "usb"; | |
| 38dbb45e | 1416 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1417 | resets = <&cpg 701>; |
| a2bcdc28 YS |
1418 | status = "disabled"; |
| 1419 | }; | |
| 1420 | ||
| 1421 | ohci0: usb@ee080000 { | |
| 1422 | compatible = "generic-ohci"; | |
| 1423 | reg = <0 0xee080000 0 0x100>; | |
| 1424 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; | |
| 1425 | clocks = <&cpg CPG_MOD 703>; | |
| 1426 | phys = <&usb2_phy0>; | |
| 1427 | phy-names = "usb"; | |
| 38dbb45e | 1428 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1429 | resets = <&cpg 703>; |
| a2bcdc28 YS |
1430 | status = "disabled"; |
| 1431 | }; | |
| 1432 | ||
| 1433 | ohci1: usb@ee0a0000 { | |
| 1434 | compatible = "generic-ohci"; | |
| 1435 | reg = <0 0xee0a0000 0 0x100>; | |
| 1436 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; | |
| 1437 | clocks = <&cpg CPG_MOD 702>; | |
| 1438 | phys = <&usb2_phy1>; | |
| 1439 | phy-names = "usb"; | |
| 38dbb45e | 1440 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1441 | resets = <&cpg 702>; |
| a2bcdc28 YS |
1442 | status = "disabled"; |
| 1443 | }; | |
| 1444 | ||
| 1445 | ohci2: usb@ee0c0000 { | |
| 1446 | compatible = "generic-ohci"; | |
| 1447 | reg = <0 0xee0c0000 0 0x100>; | |
| 1448 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; | |
| 1449 | clocks = <&cpg CPG_MOD 701>; | |
| 1450 | phys = <&usb2_phy2>; | |
| 1451 | phy-names = "usb"; | |
| 38dbb45e | 1452 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1453 | resets = <&cpg 701>; |
| a2bcdc28 YS |
1454 | status = "disabled"; |
| 1455 | }; | |
| d2422e10 YS |
1456 | |
| 1457 | hsusb: usb@e6590000 { | |
| 1458 | compatible = "renesas,usbhs-r8a7795", | |
| 1459 | "renesas,rcar-gen3-usbhs"; | |
| 1460 | reg = <0 0xe6590000 0 0x100>; | |
| 1461 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; | |
| 1462 | clocks = <&cpg CPG_MOD 704>; | |
| 1463 | dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, | |
| 1464 | <&usb_dmac1 0>, <&usb_dmac1 1>; | |
| 1465 | dma-names = "ch0", "ch1", "ch2", "ch3"; | |
| 1466 | renesas,buswait = <11>; | |
| 1467 | phys = <&usb2_phy0>; | |
| 1468 | phy-names = "usb"; | |
| 1469 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| dcccc132 | 1470 | resets = <&cpg 704>; |
| d2422e10 YS |
1471 | status = "disabled"; |
| 1472 | }; | |
| 1473 | ||
| 9251024a | 1474 | pciec0: pcie@fe000000 { |
| fb04f4b8 SH |
1475 | compatible = "renesas,pcie-r8a7795", |
| 1476 | "renesas,pcie-rcar-gen3"; | |
| 9251024a PE |
1477 | reg = <0 0xfe000000 0 0x80000>; |
| 1478 | #address-cells = <3>; | |
| 1479 | #size-cells = <2>; | |
| 1480 | bus-range = <0x00 0xff>; | |
| 1481 | device_type = "pci"; | |
| 1482 | ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 | |
| 1483 | 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 | |
| 1484 | 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 | |
| 1485 | 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; | |
| 1486 | /* Map all possible DDR as inbound ranges */ | |
| 1487 | dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; | |
| 1488 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, | |
| 1489 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
| 1490 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; | |
| 1491 | #interrupt-cells = <1>; | |
| 1492 | interrupt-map-mask = <0 0 0 0>; | |
| 1493 | interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | |
| 1494 | clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; | |
| 1495 | clock-names = "pcie", "pcie_bus"; | |
| 38dbb45e | 1496 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1497 | resets = <&cpg 319>; |
| 9251024a PE |
1498 | status = "disabled"; |
| 1499 | }; | |
| 1500 | ||
| 1501 | pciec1: pcie@ee800000 { | |
| fb04f4b8 SH |
1502 | compatible = "renesas,pcie-r8a7795", |
| 1503 | "renesas,pcie-rcar-gen3"; | |
| 9251024a PE |
1504 | reg = <0 0xee800000 0 0x80000>; |
| 1505 | #address-cells = <3>; | |
| 1506 | #size-cells = <2>; | |
| 1507 | bus-range = <0x00 0xff>; | |
| 1508 | device_type = "pci"; | |
| 1509 | ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000 | |
| 1510 | 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000 | |
| 1511 | 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000 | |
| 1512 | 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; | |
| 1513 | /* Map all possible DDR as inbound ranges */ | |
| 1514 | dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; | |
| 1515 | interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, | |
| 1516 | <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, | |
| 1517 | <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; | |
| 1518 | #interrupt-cells = <1>; | |
| 1519 | interrupt-map-mask = <0 0 0 0>; | |
| 1520 | interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; | |
| 1521 | clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; | |
| 1522 | clock-names = "pcie", "pcie_bus"; | |
| 38dbb45e | 1523 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; |
| dcccc132 | 1524 | resets = <&cpg 318>; |
| 9251024a PE |
1525 | status = "disabled"; |
| 1526 | }; | |
| 28fc8131 | 1527 | |
| 9f8573e3 LP |
1528 | vspbc: vsp@fe920000 { |
| 1529 | compatible = "renesas,vsp2"; | |
| 1530 | reg = <0 0xfe920000 0 0x8000>; | |
| 1531 | interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; | |
| 1532 | clocks = <&cpg CPG_MOD 624>; | |
| 1533 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
| dcccc132 | 1534 | resets = <&cpg 624>; |
| 9f8573e3 LP |
1535 | |
| 1536 | renesas,fcp = <&fcpvb1>; | |
| 1537 | }; | |
| 1538 | ||
| 52cd0783 | 1539 | fcpvb1: fcp@fe92f000 { |
| ab33da0b | 1540 | compatible = "renesas,fcpv"; |
| 52cd0783 LP |
1541 | reg = <0 0xfe92f000 0 0x200>; |
| 1542 | clocks = <&cpg CPG_MOD 606>; | |
| 1543 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
| dcccc132 | 1544 | resets = <&cpg 606>; |
| 52cd0783 LP |
1545 | }; |
| 1546 | ||
| 28fc8131 | 1547 | fcpf0: fcp@fe950000 { |
| ab33da0b | 1548 | compatible = "renesas,fcpf"; |
| 28fc8131 KB |
1549 | reg = <0 0xfe950000 0 0x200>; |
| 1550 | clocks = <&cpg CPG_MOD 615>; | |
| 1551 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
| dcccc132 | 1552 | resets = <&cpg 615>; |
| 28fc8131 KB |
1553 | }; |
| 1554 | ||
| 1555 | fcpf1: fcp@fe951000 { | |
| ab33da0b | 1556 | compatible = "renesas,fcpf"; |
| 28fc8131 KB |
1557 | reg = <0 0xfe951000 0 0x200>; |
| 1558 | clocks = <&cpg CPG_MOD 614>; | |
| 1559 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
| dcccc132 | 1560 | resets = <&cpg 614>; |
| 28fc8131 KB |
1561 | }; |
| 1562 | ||
| 9f8573e3 LP |
1563 | vspbd: vsp@fe960000 { |
| 1564 | compatible = "renesas,vsp2"; | |
| 1565 | reg = <0 0xfe960000 0 0x8000>; | |
| 1566 | interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; | |
| 1567 | clocks = <&cpg CPG_MOD 626>; | |
| 1568 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
| dcccc132 | 1569 | resets = <&cpg 626>; |
| 9f8573e3 LP |
1570 | |
| 1571 | renesas,fcp = <&fcpvb0>; | |
| 1572 | }; | |
| 1573 | ||
| 52cd0783 | 1574 | fcpvb0: fcp@fe96f000 { |
| ab33da0b | 1575 | compatible = "renesas,fcpv"; |
| 52cd0783 LP |
1576 | reg = <0 0xfe96f000 0 0x200>; |
| 1577 | clocks = <&cpg CPG_MOD 607>; | |
| 1578 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
| dcccc132 | 1579 | resets = <&cpg 607>; |
| 52cd0783 LP |
1580 | }; |
| 1581 | ||
| 9f8573e3 LP |
1582 | vspi0: vsp@fe9a0000 { |
| 1583 | compatible = "renesas,vsp2"; | |
| 1584 | reg = <0 0xfe9a0000 0 0x8000>; | |
| 1585 | interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; | |
| 1586 | clocks = <&cpg CPG_MOD 631>; | |
| 1587 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
| dcccc132 | 1588 | resets = <&cpg 631>; |
| 9f8573e3 LP |
1589 | |
| 1590 | renesas,fcp = <&fcpvi0>; | |
| 1591 | }; | |
| 1592 | ||
| 52cd0783 | 1593 | fcpvi0: fcp@fe9af000 { |
| ab33da0b | 1594 | compatible = "renesas,fcpv"; |
| 52cd0783 LP |
1595 | reg = <0 0xfe9af000 0 0x200>; |
| 1596 | clocks = <&cpg CPG_MOD 611>; | |
| 1597 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
| dcccc132 | 1598 | resets = <&cpg 611>; |
| 52cd0783 LP |
1599 | }; |
| 1600 | ||
| 9f8573e3 LP |
1601 | vspi1: vsp@fe9b0000 { |
| 1602 | compatible = "renesas,vsp2"; | |
| 1603 | reg = <0 0xfe9b0000 0 0x8000>; | |
| 1604 | interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; | |
| 1605 | clocks = <&cpg CPG_MOD 630>; | |
| 1606 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
| dcccc132 | 1607 | resets = <&cpg 630>; |
| 9f8573e3 LP |
1608 | |
| 1609 | renesas,fcp = <&fcpvi1>; | |
| 1610 | }; | |
| 1611 | ||
| 52cd0783 | 1612 | fcpvi1: fcp@fe9bf000 { |
| ab33da0b | 1613 | compatible = "renesas,fcpv"; |
| 52cd0783 LP |
1614 | reg = <0 0xfe9bf000 0 0x200>; |
| 1615 | clocks = <&cpg CPG_MOD 610>; | |
| 1616 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
| dcccc132 | 1617 | resets = <&cpg 610>; |
| 52cd0783 LP |
1618 | }; |
| 1619 | ||
| 9f8573e3 LP |
1620 | vspd0: vsp@fea20000 { |
| 1621 | compatible = "renesas,vsp2"; | |
| 1622 | reg = <0 0xfea20000 0 0x4000>; | |
| 1623 | interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; | |
| 1624 | clocks = <&cpg CPG_MOD 623>; | |
| 1625 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| dcccc132 | 1626 | resets = <&cpg 623>; |
| 9f8573e3 LP |
1627 | |
| 1628 | renesas,fcp = <&fcpvd0>; | |
| 1629 | }; | |
| 1630 | ||
| 52cd0783 | 1631 | fcpvd0: fcp@fea27000 { |
| ab33da0b | 1632 | compatible = "renesas,fcpv"; |
| 52cd0783 LP |
1633 | reg = <0 0xfea27000 0 0x200>; |
| 1634 | clocks = <&cpg CPG_MOD 603>; | |
| 1635 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| dcccc132 | 1636 | resets = <&cpg 603>; |
| 52cd0783 LP |
1637 | }; |
| 1638 | ||
| 9f8573e3 LP |
1639 | vspd1: vsp@fea28000 { |
| 1640 | compatible = "renesas,vsp2"; | |
| 1641 | reg = <0 0xfea28000 0 0x4000>; | |
| 1642 | interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; | |
| 1643 | clocks = <&cpg CPG_MOD 622>; | |
| 1644 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| dcccc132 | 1645 | resets = <&cpg 622>; |
| 9f8573e3 LP |
1646 | |
| 1647 | renesas,fcp = <&fcpvd1>; | |
| 1648 | }; | |
| 1649 | ||
| 52cd0783 | 1650 | fcpvd1: fcp@fea2f000 { |
| ab33da0b | 1651 | compatible = "renesas,fcpv"; |
| 52cd0783 LP |
1652 | reg = <0 0xfea2f000 0 0x200>; |
| 1653 | clocks = <&cpg CPG_MOD 602>; | |
| 1654 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| dcccc132 | 1655 | resets = <&cpg 602>; |
| 52cd0783 LP |
1656 | }; |
| 1657 | ||
| 9f8573e3 LP |
1658 | vspd2: vsp@fea30000 { |
| 1659 | compatible = "renesas,vsp2"; | |
| 1660 | reg = <0 0xfea30000 0 0x4000>; | |
| 1661 | interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; | |
| 1662 | clocks = <&cpg CPG_MOD 621>; | |
| 1663 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| dcccc132 | 1664 | resets = <&cpg 621>; |
| 9f8573e3 LP |
1665 | |
| 1666 | renesas,fcp = <&fcpvd2>; | |
| 1667 | }; | |
| 1668 | ||
| 52cd0783 | 1669 | fcpvd2: fcp@fea37000 { |
| ab33da0b | 1670 | compatible = "renesas,fcpv"; |
| 52cd0783 LP |
1671 | reg = <0 0xfea37000 0 0x200>; |
| 1672 | clocks = <&cpg CPG_MOD 601>; | |
| 1673 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| dcccc132 | 1674 | resets = <&cpg 601>; |
| 52cd0783 LP |
1675 | }; |
| 1676 | ||
| bfb31459 KB |
1677 | fdp1@fe940000 { |
| 1678 | compatible = "renesas,fdp1"; | |
| 1679 | reg = <0 0xfe940000 0 0x2400>; | |
| 1680 | interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; | |
| 1681 | clocks = <&cpg CPG_MOD 119>; | |
| 1682 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
| dcccc132 | 1683 | resets = <&cpg 119>; |
| bfb31459 KB |
1684 | renesas,fcp = <&fcpf0>; |
| 1685 | }; | |
| 1686 | ||
| 1687 | fdp1@fe944000 { | |
| 1688 | compatible = "renesas,fdp1"; | |
| 1689 | reg = <0 0xfe944000 0 0x2400>; | |
| 1690 | interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; | |
| 1691 | clocks = <&cpg CPG_MOD 118>; | |
| 1692 | power-domains = <&sysc R8A7795_PD_A3VP>; | |
| dcccc132 | 1693 | resets = <&cpg 118>; |
| bfb31459 KB |
1694 | renesas,fcp = <&fcpf1>; |
| 1695 | }; | |
| 1696 | ||
| 12daaf78 UH |
1697 | hdmi0: hdmi0@fead0000 { |
| 1698 | compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; | |
| 1699 | reg = <0 0xfead0000 0 0x10000>; | |
| 1700 | interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; | |
| 1701 | clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7795_CLK_HDMI>; | |
| 1702 | clock-names = "iahb", "isfr"; | |
| 1703 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 1704 | resets = <&cpg 729>; | |
| 1705 | status = "disabled"; | |
| 1706 | ||
| 1707 | ports { | |
| 1708 | #address-cells = <1>; | |
| 1709 | #size-cells = <0>; | |
| 1710 | port@0 { | |
| 1711 | reg = <0>; | |
| 1712 | dw_hdmi0_in: endpoint { | |
| 1713 | remote-endpoint = <&du_out_hdmi0>; | |
| 1714 | }; | |
| 1715 | }; | |
| 1716 | port@1 { | |
| 1717 | reg = <1>; | |
| 1718 | }; | |
| 1719 | }; | |
| 1720 | }; | |
| 1721 | ||
| 1722 | hdmi1: hdmi1@feae0000 { | |
| 1723 | compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; | |
| 1724 | reg = <0 0xfeae0000 0 0x10000>; | |
| 1725 | interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>; | |
| 1726 | clocks = <&cpg CPG_MOD 728>, <&cpg CPG_CORE R8A7795_CLK_HDMI>; | |
| 1727 | clock-names = "iahb", "isfr"; | |
| 1728 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| 1729 | resets = <&cpg 728>; | |
| 1730 | status = "disabled"; | |
| 1731 | ||
| 1732 | ports { | |
| 1733 | #address-cells = <1>; | |
| 1734 | #size-cells = <0>; | |
| 1735 | port@0 { | |
| 1736 | reg = <0>; | |
| 1737 | dw_hdmi1_in: endpoint { | |
| 1738 | remote-endpoint = <&du_out_hdmi1>; | |
| 1739 | }; | |
| 1740 | }; | |
| 1741 | port@1 { | |
| 1742 | reg = <1>; | |
| 1743 | }; | |
| 1744 | }; | |
| 1745 | }; | |
| 1746 | ||
| a001a07f | 1747 | du: display@feb00000 { |
| a001a07f LP |
1748 | reg = <0 0xfeb00000 0 0x80000>, |
| 1749 | <0 0xfeb90000 0 0x14>; | |
| 1750 | reg-names = "du", "lvds.0"; | |
| 1751 | interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, | |
| 1752 | <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, | |
| 1753 | <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, | |
| 1754 | <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; | |
| 1755 | clocks = <&cpg CPG_MOD 724>, | |
| 1756 | <&cpg CPG_MOD 723>, | |
| 1757 | <&cpg CPG_MOD 722>, | |
| 1758 | <&cpg CPG_MOD 721>, | |
| 1759 | <&cpg CPG_MOD 727>; | |
| 1760 | clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0"; | |
| 1761 | status = "disabled"; | |
| 1762 | ||
| a001a07f LP |
1763 | ports { |
| 1764 | #address-cells = <1>; | |
| 1765 | #size-cells = <0>; | |
| 1766 | ||
| 1767 | port@0 { | |
| 1768 | reg = <0>; | |
| 1769 | du_out_rgb: endpoint { | |
| 1770 | }; | |
| 1771 | }; | |
| 1772 | port@1 { | |
| 1773 | reg = <1>; | |
| 1774 | du_out_hdmi0: endpoint { | |
| 12daaf78 | 1775 | remote-endpoint = <&dw_hdmi0_in>; |
| a001a07f LP |
1776 | }; |
| 1777 | }; | |
| 1778 | port@2 { | |
| 1779 | reg = <2>; | |
| 1780 | du_out_hdmi1: endpoint { | |
| 12daaf78 | 1781 | remote-endpoint = <&dw_hdmi1_in>; |
| a001a07f LP |
1782 | }; |
| 1783 | }; | |
| 1784 | port@3 { | |
| 1785 | reg = <3>; | |
| 1786 | du_out_lvds0: endpoint { | |
| 1787 | }; | |
| 1788 | }; | |
| 1789 | }; | |
| 1790 | }; | |
| b443cd17 WS |
1791 | |
| 1792 | tsc: thermal@e6198000 { | |
| 1793 | compatible = "renesas,r8a7795-thermal"; | |
| 1794 | reg = <0 0xe6198000 0 0x68>, | |
| 1795 | <0 0xe61a0000 0 0x5c>, | |
| 1796 | <0 0xe61a8000 0 0x5c>; | |
| 1797 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, | |
| 1798 | <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, | |
| 1799 | <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | |
| 1800 | clocks = <&cpg CPG_MOD 522>; | |
| 1801 | power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; | |
| dcccc132 | 1802 | resets = <&cpg 522>; |
| b443cd17 WS |
1803 | #thermal-sensor-cells = <1>; |
| 1804 | status = "okay"; | |
| 1805 | }; | |
| 1806 | ||
| 1807 | thermal-zones { | |
| 1808 | sensor_thermal1: sensor-thermal1 { | |
| 1809 | polling-delay-passive = <250>; | |
| 1810 | polling-delay = <1000>; | |
| 1811 | thermal-sensors = <&tsc 0>; | |
| 1812 | ||
| 1813 | trips { | |
| 1814 | sensor1_crit: sensor1-crit { | |
| 1815 | temperature = <120000>; | |
| 1816 | hysteresis = <2000>; | |
| 1817 | type = "critical"; | |
| 1818 | }; | |
| 1819 | }; | |
| 1820 | }; | |
| 1821 | ||
| 1822 | sensor_thermal2: sensor-thermal2 { | |
| 1823 | polling-delay-passive = <250>; | |
| 1824 | polling-delay = <1000>; | |
| 1825 | thermal-sensors = <&tsc 1>; | |
| 1826 | ||
| 1827 | trips { | |
| 1828 | sensor2_crit: sensor2-crit { | |
| 1829 | temperature = <120000>; | |
| 1830 | hysteresis = <2000>; | |
| 1831 | type = "critical"; | |
| 1832 | }; | |
| 1833 | }; | |
| 1834 | }; | |
| 1835 | ||
| 1836 | sensor_thermal3: sensor-thermal3 { | |
| 1837 | polling-delay-passive = <250>; | |
| 1838 | polling-delay = <1000>; | |
| 1839 | thermal-sensors = <&tsc 2>; | |
| 1840 | ||
| 1841 | trips { | |
| 1842 | sensor3_crit: sensor3-crit { | |
| 1843 | temperature = <120000>; | |
| 1844 | hysteresis = <2000>; | |
| 1845 | type = "critical"; | |
| 1846 | }; | |
| 1847 | }; | |
| 1848 | }; | |
| 1849 | }; | |
| 26a7e06d SH |
1850 | }; |
| 1851 | }; |