projects / mirror_ubuntu-focal-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| cba59c25 | 1 | // SPDX-License-Identifier: GPL-2.0 |
| d917e0b2 | 2 | /* |
| e18a31a7 | 3 | * Device Tree Source for the R-Car D3 (R8A77995) SoC |
| d917e0b2 GU |
4 | * |
| 5 | * Copyright (C) 2016 Renesas Electronics Corp. | |
| 6 | * Copyright (C) 2017 Glider bvba | |
| d917e0b2 GU |
7 | */ |
| 8 | ||
| 5889ded1 | 9 | #include <dt-bindings/clock/r8a77995-cpg-mssr.h> |
| d917e0b2 | 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 9066b042 | 11 | #include <dt-bindings/power/r8a77995-sysc.h> |
| d917e0b2 GU |
12 | |
| 13 | / { | |
| 14 | compatible = "renesas,r8a77995"; | |
| 15 | #address-cells = <2>; | |
| 16 | #size-cells = <2>; | |
| 17 | ||
| 21559e2b YK |
18 | /* External CAN clock - to be overridden by boards that provide it */ |
| 19 | can_clk: can { | |
| 20 | compatible = "fixed-clock"; | |
| 21 | #clock-cells = <0>; | |
| 22 | clock-frequency = <0>; | |
| d917e0b2 GU |
23 | }; |
| 24 | ||
| 25 | cpus { | |
| 26 | #address-cells = <1>; | |
| 27 | #size-cells = <0>; | |
| 28 | ||
| 29 | a53_0: cpu@0 { | |
| 30 | compatible = "arm,cortex-a53", "arm,armv8"; | |
| 31 | reg = <0x0>; | |
| 32 | device_type = "cpu"; | |
| 9066b042 | 33 | power-domains = <&sysc R8A77995_PD_CA53_CPU0>; |
| d917e0b2 GU |
34 | next-level-cache = <&L2_CA53>; |
| 35 | enable-method = "psci"; | |
| 36 | }; | |
| 37 | ||
| 38 | L2_CA53: cache-controller-1 { | |
| 39 | compatible = "cache"; | |
| 9066b042 | 40 | power-domains = <&sysc R8A77995_PD_CA53_SCU>; |
| d917e0b2 GU |
41 | cache-unified; |
| 42 | cache-level = <2>; | |
| 43 | }; | |
| 44 | }; | |
| 45 | ||
| 46 | extal_clk: extal { | |
| 47 | compatible = "fixed-clock"; | |
| 48 | #clock-cells = <0>; | |
| 49 | /* This value must be overridden by the board */ | |
| 50 | clock-frequency = <0>; | |
| 51 | }; | |
| 52 | ||
| f320eead SH |
53 | pmu_a53 { |
| 54 | compatible = "arm,cortex-a53-pmu"; | |
| 55 | interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; | |
| 56 | }; | |
| 57 | ||
| 21559e2b YK |
58 | psci { |
| 59 | compatible = "arm,psci-1.0", "arm,psci-0.2"; | |
| 60 | method = "smc"; | |
| 61 | }; | |
| 62 | ||
| d917e0b2 GU |
63 | scif_clk: scif { |
| 64 | compatible = "fixed-clock"; | |
| 65 | #clock-cells = <0>; | |
| 66 | clock-frequency = <0>; | |
| 67 | }; | |
| 68 | ||
| 69 | soc { | |
| 70 | compatible = "simple-bus"; | |
| 71 | interrupt-parent = <&gic>; | |
| 72 | #address-cells = <2>; | |
| 73 | #size-cells = <2>; | |
| 74 | ranges; | |
| 75 | ||
| d917e0b2 GU |
76 | rwdt: watchdog@e6020000 { |
| 77 | compatible = "renesas,r8a77995-wdt", | |
| 78 | "renesas,rcar-gen3-wdt"; | |
| 79 | reg = <0 0xe6020000 0 0x0c>; | |
| 80 | clocks = <&cpg CPG_MOD 402>; | |
| 9066b042 | 81 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; |
| d917e0b2 GU |
82 | resets = <&cpg 402>; |
| 83 | status = "disabled"; | |
| 84 | }; | |
| 85 | ||
| 7c55747f YK |
86 | gpio0: gpio@e6050000 { |
| 87 | compatible = "renesas,gpio-r8a77995", | |
| 341238b5 | 88 | "renesas,rcar-gen3-gpio"; |
| 7c55747f YK |
89 | reg = <0 0xe6050000 0 0x50>; |
| 90 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | |
| 91 | #gpio-cells = <2>; | |
| 92 | gpio-controller; | |
| 93 | gpio-ranges = <&pfc 0 0 9>; | |
| 94 | #interrupt-cells = <2>; | |
| 95 | interrupt-controller; | |
| 96 | clocks = <&cpg CPG_MOD 912>; | |
| 97 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 98 | resets = <&cpg 912>; | |
| a3901e73 SH |
99 | }; |
| 100 | ||
| 7c55747f YK |
101 | gpio1: gpio@e6051000 { |
| 102 | compatible = "renesas,gpio-r8a77995", | |
| 341238b5 | 103 | "renesas,rcar-gen3-gpio"; |
| 7c55747f YK |
104 | reg = <0 0xe6051000 0 0x50>; |
| 105 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
| 106 | #gpio-cells = <2>; | |
| 107 | gpio-controller; | |
| 108 | gpio-ranges = <&pfc 0 32 32>; | |
| 109 | #interrupt-cells = <2>; | |
| 110 | interrupt-controller; | |
| 111 | clocks = <&cpg CPG_MOD 911>; | |
| 112 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 113 | resets = <&cpg 911>; | |
| a3901e73 SH |
114 | }; |
| 115 | ||
| 7c55747f YK |
116 | gpio2: gpio@e6052000 { |
| 117 | compatible = "renesas,gpio-r8a77995", | |
| 341238b5 | 118 | "renesas,rcar-gen3-gpio"; |
| 7c55747f YK |
119 | reg = <0 0xe6052000 0 0x50>; |
| 120 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; | |
| 121 | #gpio-cells = <2>; | |
| 122 | gpio-controller; | |
| 123 | gpio-ranges = <&pfc 0 64 32>; | |
| 124 | #interrupt-cells = <2>; | |
| 125 | interrupt-controller; | |
| 126 | clocks = <&cpg CPG_MOD 910>; | |
| 127 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 128 | resets = <&cpg 910>; | |
| a3901e73 SH |
129 | }; |
| 130 | ||
| 7c55747f YK |
131 | gpio3: gpio@e6053000 { |
| 132 | compatible = "renesas,gpio-r8a77995", | |
| 341238b5 | 133 | "renesas,rcar-gen3-gpio"; |
| 7c55747f YK |
134 | reg = <0 0xe6053000 0 0x50>; |
| 135 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; | |
| 136 | #gpio-cells = <2>; | |
| 137 | gpio-controller; | |
| 138 | gpio-ranges = <&pfc 0 96 10>; | |
| 139 | #interrupt-cells = <2>; | |
| 140 | interrupt-controller; | |
| 141 | clocks = <&cpg CPG_MOD 909>; | |
| 142 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 143 | resets = <&cpg 909>; | |
| a3901e73 SH |
144 | }; |
| 145 | ||
| 7c55747f YK |
146 | gpio4: gpio@e6054000 { |
| 147 | compatible = "renesas,gpio-r8a77995", | |
| 341238b5 | 148 | "renesas,rcar-gen3-gpio"; |
| 7c55747f YK |
149 | reg = <0 0xe6054000 0 0x50>; |
| 150 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
| 151 | #gpio-cells = <2>; | |
| 152 | gpio-controller; | |
| 153 | gpio-ranges = <&pfc 0 128 32>; | |
| 154 | #interrupt-cells = <2>; | |
| 155 | interrupt-controller; | |
| 156 | clocks = <&cpg CPG_MOD 908>; | |
| 157 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 158 | resets = <&cpg 908>; | |
| a3901e73 SH |
159 | }; |
| 160 | ||
| 7c55747f YK |
161 | gpio5: gpio@e6055000 { |
| 162 | compatible = "renesas,gpio-r8a77995", | |
| 341238b5 | 163 | "renesas,rcar-gen3-gpio"; |
| 7c55747f YK |
164 | reg = <0 0xe6055000 0 0x50>; |
| 165 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
| 166 | #gpio-cells = <2>; | |
| 167 | gpio-controller; | |
| 168 | gpio-ranges = <&pfc 0 160 21>; | |
| 169 | #interrupt-cells = <2>; | |
| 170 | interrupt-controller; | |
| 171 | clocks = <&cpg CPG_MOD 907>; | |
| 172 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 173 | resets = <&cpg 907>; | |
| a3901e73 SH |
174 | }; |
| 175 | ||
| 7c55747f YK |
176 | gpio6: gpio@e6055400 { |
| 177 | compatible = "renesas,gpio-r8a77995", | |
| 341238b5 | 178 | "renesas,rcar-gen3-gpio"; |
| 7c55747f YK |
179 | reg = <0 0xe6055400 0 0x50>; |
| 180 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; | |
| 181 | #gpio-cells = <2>; | |
| 182 | gpio-controller; | |
| 183 | gpio-ranges = <&pfc 0 192 14>; | |
| 184 | #interrupt-cells = <2>; | |
| 185 | interrupt-controller; | |
| 186 | clocks = <&cpg CPG_MOD 906>; | |
| 187 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 188 | resets = <&cpg 906>; | |
| a3901e73 SH |
189 | }; |
| 190 | ||
| 7c55747f YK |
191 | pfc: pin-controller@e6060000 { |
| 192 | compatible = "renesas,pfc-r8a77995"; | |
| 193 | reg = <0 0xe6060000 0 0x508>; | |
| a3901e73 SH |
194 | }; |
| 195 | ||
| d917e0b2 GU |
196 | cpg: clock-controller@e6150000 { |
| 197 | compatible = "renesas,r8a77995-cpg-mssr"; | |
| 198 | reg = <0 0xe6150000 0 0x1000>; | |
| 199 | clocks = <&extal_clk>; | |
| 200 | clock-names = "extal"; | |
| 201 | #clock-cells = <2>; | |
| 202 | #power-domain-cells = <0>; | |
| 203 | #reset-cells = <1>; | |
| 204 | }; | |
| 205 | ||
| 206 | rst: reset-controller@e6160000 { | |
| 207 | compatible = "renesas,r8a77995-rst"; | |
| 208 | reg = <0 0xe6160000 0 0x0200>; | |
| 209 | }; | |
| 210 | ||
| d917e0b2 GU |
211 | sysc: system-controller@e6180000 { |
| 212 | compatible = "renesas,r8a77995-sysc"; | |
| 213 | reg = <0 0xe6180000 0 0x0400>; | |
| 214 | #power-domain-cells = <1>; | |
| 215 | }; | |
| 216 | ||
| 21bd0538 YK |
217 | thermal: thermal@e6190000 { |
| 218 | compatible = "renesas,thermal-r8a77995"; | |
| 219 | reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; | |
| 220 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, | |
| 221 | <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, | |
| 222 | <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | |
| 223 | clocks = <&cpg CPG_MOD 522>; | |
| 224 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 225 | resets = <&cpg 522>; | |
| 226 | #thermal-sensor-cells = <0>; | |
| 227 | }; | |
| 228 | ||
| eb5a5078 GU |
229 | intc_ex: interrupt-controller@e61c0000 { |
| 230 | compatible = "renesas,intc-ex-r8a77995", "renesas,irqc"; | |
| 231 | #interrupt-cells = <2>; | |
| 232 | interrupt-controller; | |
| 233 | reg = <0 0xe61c0000 0 0x200>; | |
| 234 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH | |
| 235 | GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH | |
| 236 | GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH | |
| 237 | GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH | |
| 238 | GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH | |
| 239 | GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; | |
| 240 | clocks = <&cpg CPG_MOD 407>; | |
| 241 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 242 | resets = <&cpg 407>; | |
| 243 | }; | |
| 244 | ||
| 30316c4f TK |
245 | hscif0: serial@e6540000 { |
| 246 | compatible = "renesas,hscif-r8a77995", | |
| 247 | "renesas,rcar-gen3-hscif", | |
| 248 | "renesas,hscif"; | |
| 249 | reg = <0 0xe6540000 0 0x60>; | |
| 250 | interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; | |
| 251 | clocks = <&cpg CPG_MOD 520>, | |
| 252 | <&cpg CPG_CORE R8A77995_CLK_S3D1C>, | |
| 253 | <&scif_clk>; | |
| 254 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 255 | dmas = <&dmac1 0x31>, <&dmac1 0x30>, | |
| 256 | <&dmac2 0x31>, <&dmac2 0x30>; | |
| 257 | dma-names = "tx", "rx", "tx", "rx"; | |
| 258 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 259 | resets = <&cpg 520>; | |
| 260 | status = "disabled"; | |
| 261 | }; | |
| 262 | ||
| 263 | hscif3: serial@e66a0000 { | |
| 264 | compatible = "renesas,hscif-r8a77995", | |
| 265 | "renesas,rcar-gen3-hscif", | |
| 266 | "renesas,hscif"; | |
| 267 | reg = <0 0xe66a0000 0 0x60>; | |
| 268 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; | |
| 269 | clocks = <&cpg CPG_MOD 517>, | |
| 270 | <&cpg CPG_CORE R8A77995_CLK_S3D1C>, | |
| 271 | <&scif_clk>; | |
| 272 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 273 | dmas = <&dmac0 0x37>, <&dmac0 0x36>; | |
| 274 | dma-names = "tx", "rx"; | |
| 275 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 276 | resets = <&cpg 517>; | |
| 277 | status = "disabled"; | |
| 278 | }; | |
| 279 | ||
| 7c55747f YK |
280 | i2c0: i2c@e6500000 { |
| 281 | #address-cells = <1>; | |
| 282 | #size-cells = <0>; | |
| 283 | compatible = "renesas,i2c-r8a77995", | |
| 284 | "renesas,rcar-gen3-i2c"; | |
| 285 | reg = <0 0xe6500000 0 0x40>; | |
| 286 | interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; | |
| 287 | clocks = <&cpg CPG_MOD 931>; | |
| 288 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 289 | resets = <&cpg 931>; | |
| 290 | dmas = <&dmac1 0x91>, <&dmac1 0x90>, | |
| 291 | <&dmac2 0x91>, <&dmac2 0x90>; | |
| 292 | dma-names = "tx", "rx", "tx", "rx"; | |
| 293 | i2c-scl-internal-delay-ns = <6>; | |
| 294 | status = "disabled"; | |
| 295 | }; | |
| 296 | ||
| 297 | i2c1: i2c@e6508000 { | |
| 298 | #address-cells = <1>; | |
| 299 | #size-cells = <0>; | |
| 300 | compatible = "renesas,i2c-r8a77995", | |
| 301 | "renesas,rcar-gen3-i2c"; | |
| 302 | reg = <0 0xe6508000 0 0x40>; | |
| 303 | interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; | |
| 304 | clocks = <&cpg CPG_MOD 930>; | |
| 305 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 306 | resets = <&cpg 930>; | |
| 307 | dmas = <&dmac1 0x93>, <&dmac1 0x92>, | |
| 308 | <&dmac2 0x93>, <&dmac2 0x92>; | |
| 309 | dma-names = "tx", "rx", "tx", "rx"; | |
| 310 | i2c-scl-internal-delay-ns = <6>; | |
| 311 | status = "disabled"; | |
| 312 | }; | |
| 313 | ||
| 314 | i2c2: i2c@e6510000 { | |
| 315 | #address-cells = <1>; | |
| 316 | #size-cells = <0>; | |
| 317 | compatible = "renesas,i2c-r8a77995", | |
| 318 | "renesas,rcar-gen3-i2c"; | |
| 319 | reg = <0 0xe6510000 0 0x40>; | |
| 320 | interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; | |
| 321 | clocks = <&cpg CPG_MOD 929>; | |
| 322 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 323 | resets = <&cpg 929>; | |
| 324 | dmas = <&dmac1 0x95>, <&dmac1 0x94>, | |
| 325 | <&dmac2 0x95>, <&dmac2 0x94>; | |
| 326 | dma-names = "tx", "rx", "tx", "rx"; | |
| 327 | i2c-scl-internal-delay-ns = <6>; | |
| 328 | status = "disabled"; | |
| 329 | }; | |
| 330 | ||
| 331 | i2c3: i2c@e66d0000 { | |
| 332 | #address-cells = <1>; | |
| 333 | #size-cells = <0>; | |
| 334 | compatible = "renesas,i2c-r8a77995", | |
| 335 | "renesas,rcar-gen3-i2c"; | |
| 336 | reg = <0 0xe66d0000 0 0x40>; | |
| 337 | interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; | |
| 338 | clocks = <&cpg CPG_MOD 928>; | |
| 339 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 340 | resets = <&cpg 928>; | |
| 341 | dmas = <&dmac0 0x97>, <&dmac0 0x96>; | |
| 342 | dma-names = "tx", "rx"; | |
| 343 | i2c-scl-internal-delay-ns = <6>; | |
| 344 | status = "disabled"; | |
| 345 | }; | |
| 346 | ||
| 347 | canfd: can@e66c0000 { | |
| 348 | compatible = "renesas,r8a77995-canfd", | |
| 349 | "renesas,rcar-gen3-canfd"; | |
| 350 | reg = <0 0xe66c0000 0 0x8000>; | |
| 351 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, | |
| 352 | <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
| 353 | clocks = <&cpg CPG_MOD 914>, | |
| 354 | <&cpg CPG_CORE R8A77995_CLK_CANFD>, | |
| 355 | <&can_clk>; | |
| 356 | clock-names = "fck", "canfd", "can_clk"; | |
| 357 | assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; | |
| 358 | assigned-clock-rates = <40000000>; | |
| 359 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 360 | resets = <&cpg 914>; | |
| 361 | status = "disabled"; | |
| 362 | ||
| 363 | channel0 { | |
| 364 | status = "disabled"; | |
| 365 | }; | |
| 366 | ||
| 367 | channel1 { | |
| 368 | status = "disabled"; | |
| 369 | }; | |
| 370 | }; | |
| 371 | ||
| 942164ca UH |
372 | dmac0: dma-controller@e6700000 { |
| 373 | compatible = "renesas,dmac-r8a77995", | |
| 374 | "renesas,rcar-dmac"; | |
| 375 | reg = <0 0xe6700000 0 0x10000>; | |
| 376 | interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH | |
| 377 | GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH | |
| 378 | GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH | |
| 379 | GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH | |
| 380 | GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH | |
| 381 | GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH | |
| 382 | GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH | |
| 383 | GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH | |
| 384 | GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; | |
| 385 | interrupt-names = "error", | |
| 386 | "ch0", "ch1", "ch2", "ch3", | |
| 387 | "ch4", "ch5", "ch6", "ch7"; | |
| 388 | clocks = <&cpg CPG_MOD 219>; | |
| 389 | clock-names = "fck"; | |
| 390 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 391 | resets = <&cpg 219>; | |
| 392 | #dma-cells = <1>; | |
| 393 | dma-channels = <8>; | |
| dc7a6bab MD |
394 | iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, |
| 395 | <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, | |
| 396 | <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, | |
| 397 | <&ipmmu_ds0 6>, <&ipmmu_ds0 7>; | |
| 942164ca UH |
398 | }; |
| 399 | ||
| 400 | dmac1: dma-controller@e7300000 { | |
| 401 | compatible = "renesas,dmac-r8a77995", | |
| 402 | "renesas,rcar-dmac"; | |
| 403 | reg = <0 0xe7300000 0 0x10000>; | |
| 404 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH | |
| 405 | GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH | |
| 406 | GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH | |
| 407 | GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH | |
| 408 | GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH | |
| 409 | GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH | |
| 410 | GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH | |
| 411 | GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH | |
| 412 | GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; | |
| 413 | interrupt-names = "error", | |
| 414 | "ch0", "ch1", "ch2", "ch3", | |
| 415 | "ch4", "ch5", "ch6", "ch7"; | |
| 416 | clocks = <&cpg CPG_MOD 218>; | |
| 417 | clock-names = "fck"; | |
| 418 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 419 | resets = <&cpg 218>; | |
| 420 | #dma-cells = <1>; | |
| 421 | dma-channels = <8>; | |
| dc7a6bab MD |
422 | iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, |
| 423 | <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, | |
| 424 | <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, | |
| 425 | <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; | |
| 942164ca UH |
426 | }; |
| 427 | ||
| 428 | dmac2: dma-controller@e7310000 { | |
| 429 | compatible = "renesas,dmac-r8a77995", | |
| 430 | "renesas,rcar-dmac"; | |
| 431 | reg = <0 0xe7310000 0 0x10000>; | |
| 432 | interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH | |
| 433 | GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH | |
| 434 | GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH | |
| 435 | GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH | |
| 436 | GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH | |
| 437 | GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH | |
| 438 | GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH | |
| 439 | GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH | |
| 440 | GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; | |
| 441 | interrupt-names = "error", | |
| 442 | "ch0", "ch1", "ch2", "ch3", | |
| 443 | "ch4", "ch5", "ch6", "ch7"; | |
| 444 | clocks = <&cpg CPG_MOD 217>; | |
| 445 | clock-names = "fck"; | |
| 446 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 447 | resets = <&cpg 217>; | |
| 448 | #dma-cells = <1>; | |
| 449 | dma-channels = <8>; | |
| dc7a6bab MD |
450 | iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, |
| 451 | <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, | |
| 452 | <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, | |
| 453 | <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; | |
| 942164ca UH |
454 | }; |
| 455 | ||
| 7c55747f YK |
456 | ipmmu_ds0: mmu@e6740000 { |
| 457 | compatible = "renesas,ipmmu-r8a77995"; | |
| 458 | reg = <0 0xe6740000 0 0x1000>; | |
| 459 | renesas,ipmmu-main = <&ipmmu_mm 0>; | |
| 7e26bd33 | 460 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; |
| 7c55747f | 461 | #iommu-cells = <1>; |
| 11581f5d YS |
462 | }; |
| 463 | ||
| 7c55747f YK |
464 | ipmmu_ds1: mmu@e7740000 { |
| 465 | compatible = "renesas,ipmmu-r8a77995"; | |
| 466 | reg = <0 0xe7740000 0 0x1000>; | |
| 467 | renesas,ipmmu-main = <&ipmmu_mm 1>; | |
| 7e26bd33 | 468 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; |
| 7c55747f | 469 | #iommu-cells = <1>; |
| 11581f5d YS |
470 | }; |
| 471 | ||
| 7c55747f YK |
472 | ipmmu_hc: mmu@e6570000 { |
| 473 | compatible = "renesas,ipmmu-r8a77995"; | |
| 474 | reg = <0 0xe6570000 0 0x1000>; | |
| 475 | renesas,ipmmu-main = <&ipmmu_mm 2>; | |
| 7e26bd33 | 476 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; |
| 7c55747f | 477 | #iommu-cells = <1>; |
| 11581f5d YS |
478 | }; |
| 479 | ||
| 7c55747f YK |
480 | ipmmu_mm: mmu@e67b0000 { |
| 481 | compatible = "renesas,ipmmu-r8a77995"; | |
| 482 | reg = <0 0xe67b0000 0 0x1000>; | |
| 483 | interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, | |
| 484 | <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; | |
| 7e26bd33 | 485 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; |
| 7c55747f | 486 | #iommu-cells = <1>; |
| 11581f5d YS |
487 | }; |
| 488 | ||
| 7c55747f YK |
489 | ipmmu_mp: mmu@ec670000 { |
| 490 | compatible = "renesas,ipmmu-r8a77995"; | |
| 491 | reg = <0 0xec670000 0 0x1000>; | |
| 492 | renesas,ipmmu-main = <&ipmmu_mm 4>; | |
| 7e26bd33 | 493 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; |
| 7c55747f | 494 | #iommu-cells = <1>; |
| 11581f5d YS |
495 | }; |
| 496 | ||
| 7c55747f YK |
497 | ipmmu_pv0: mmu@fd800000 { |
| 498 | compatible = "renesas,ipmmu-r8a77995"; | |
| 499 | reg = <0 0xfd800000 0 0x1000>; | |
| 500 | renesas,ipmmu-main = <&ipmmu_mm 6>; | |
| 7e26bd33 | 501 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; |
| 7c55747f | 502 | #iommu-cells = <1>; |
| 11581f5d YS |
503 | }; |
| 504 | ||
| 7c55747f YK |
505 | ipmmu_rt: mmu@ffc80000 { |
| 506 | compatible = "renesas,ipmmu-r8a77995"; | |
| 507 | reg = <0 0xffc80000 0 0x1000>; | |
| 508 | renesas,ipmmu-main = <&ipmmu_mm 10>; | |
| 7e26bd33 | 509 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; |
| 7c55747f | 510 | #iommu-cells = <1>; |
| acaa51a3 UH |
511 | }; |
| 512 | ||
| 7c55747f YK |
513 | ipmmu_vc0: mmu@fe6b0000 { |
| 514 | compatible = "renesas,ipmmu-r8a77995"; | |
| 515 | reg = <0 0xfe6b0000 0 0x1000>; | |
| 516 | renesas,ipmmu-main = <&ipmmu_mm 12>; | |
| 7e26bd33 | 517 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; |
| 7c55747f | 518 | #iommu-cells = <1>; |
| acaa51a3 UH |
519 | }; |
| 520 | ||
| 7c55747f YK |
521 | ipmmu_vi0: mmu@febd0000 { |
| 522 | compatible = "renesas,ipmmu-r8a77995"; | |
| 523 | reg = <0 0xfebd0000 0 0x1000>; | |
| 524 | renesas,ipmmu-main = <&ipmmu_mm 14>; | |
| 7e26bd33 | 525 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; |
| 7c55747f | 526 | #iommu-cells = <1>; |
| 7c55747f | 527 | }; |
| e2767b0f | 528 | |
| 7c55747f YK |
529 | ipmmu_vp0: mmu@fe990000 { |
| 530 | compatible = "renesas,ipmmu-r8a77995"; | |
| 531 | reg = <0 0xfe990000 0 0x1000>; | |
| 532 | renesas,ipmmu-main = <&ipmmu_mm 16>; | |
| 7e26bd33 | 533 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; |
| 7c55747f | 534 | #iommu-cells = <1>; |
| e2767b0f UH |
535 | }; |
| 536 | ||
| f9ba0c4c YS |
537 | avb: ethernet@e6800000 { |
| 538 | compatible = "renesas,etheravb-r8a77995", | |
| 539 | "renesas,etheravb-rcar-gen3"; | |
| fa3d4c67 | 540 | reg = <0 0xe6800000 0 0x800>; |
| f9ba0c4c YS |
541 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, |
| 542 | <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, | |
| 543 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
| 544 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, | |
| 545 | <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, | |
| 546 | <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, | |
| 547 | <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, | |
| 548 | <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, | |
| 549 | <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, | |
| 550 | <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, | |
| 551 | <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, | |
| 552 | <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, | |
| 553 | <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, | |
| 554 | <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, | |
| 555 | <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, | |
| 556 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | |
| 557 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
| 558 | <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, | |
| 559 | <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, | |
| 560 | <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, | |
| 561 | <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, | |
| 562 | <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, | |
| 563 | <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, | |
| 564 | <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, | |
| 565 | <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | |
| 566 | interrupt-names = "ch0", "ch1", "ch2", "ch3", | |
| 567 | "ch4", "ch5", "ch6", "ch7", | |
| 568 | "ch8", "ch9", "ch10", "ch11", | |
| 569 | "ch12", "ch13", "ch14", "ch15", | |
| 570 | "ch16", "ch17", "ch18", "ch19", | |
| 571 | "ch20", "ch21", "ch22", "ch23", | |
| 572 | "ch24"; | |
| 573 | clocks = <&cpg CPG_MOD 812>; | |
| 574 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 575 | resets = <&cpg 812>; | |
| e9131e54 | 576 | phy-mode = "rgmii"; |
| 2ebdfea2 | 577 | iommus = <&ipmmu_ds0 16>; |
| f9ba0c4c YS |
578 | #address-cells = <1>; |
| 579 | #size-cells = <0>; | |
| 580 | status = "disabled"; | |
| 581 | }; | |
| 582 | ||
| 7c55747f YK |
583 | can0: can@e6c30000 { |
| 584 | compatible = "renesas,can-r8a77995", | |
| 585 | "renesas,rcar-gen3-can"; | |
| 586 | reg = <0 0xe6c30000 0 0x1000>; | |
| 587 | interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; | |
| 588 | clocks = <&cpg CPG_MOD 916>, | |
| 589 | <&cpg CPG_CORE R8A77995_CLK_CANFD>, | |
| 590 | <&can_clk>; | |
| 591 | clock-names = "clkp1", "clkp2", "can_clk"; | |
| 592 | assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; | |
| 593 | assigned-clock-rates = <40000000>; | |
| ffcd060f | 594 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; |
| 7c55747f | 595 | resets = <&cpg 916>; |
| ffcd060f UH |
596 | status = "disabled"; |
| 597 | }; | |
| 598 | ||
| 7c55747f YK |
599 | can1: can@e6c38000 { |
| 600 | compatible = "renesas,can-r8a77995", | |
| 601 | "renesas,rcar-gen3-can"; | |
| 602 | reg = <0 0xe6c38000 0 0x1000>; | |
| 603 | interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; | |
| 604 | clocks = <&cpg CPG_MOD 915>, | |
| 605 | <&cpg CPG_CORE R8A77995_CLK_CANFD>, | |
| 606 | <&can_clk>; | |
| 607 | clock-names = "clkp1", "clkp2", "can_clk"; | |
| 608 | assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>; | |
| 609 | assigned-clock-rates = <40000000>; | |
| ffcd060f | 610 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; |
| 7c55747f | 611 | resets = <&cpg 915>; |
| ffcd060f UH |
612 | status = "disabled"; |
| 613 | }; | |
| 614 | ||
| d40a4347 YS |
615 | pwm0: pwm@e6e30000 { |
| 616 | compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; | |
| 617 | reg = <0 0xe6e30000 0 0x8>; | |
| 618 | #pwm-cells = <2>; | |
| 619 | clocks = <&cpg CPG_MOD 523>; | |
| 620 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 621 | resets = <&cpg 523>; | |
| 622 | status = "disabled"; | |
| 623 | }; | |
| 624 | ||
| 625 | pwm1: pwm@e6e31000 { | |
| 626 | compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; | |
| 627 | reg = <0 0xe6e31000 0 0x8>; | |
| 628 | #pwm-cells = <2>; | |
| 629 | clocks = <&cpg CPG_MOD 523>; | |
| 630 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 631 | resets = <&cpg 523>; | |
| 632 | status = "disabled"; | |
| 633 | }; | |
| 634 | ||
| 635 | pwm2: pwm@e6e32000 { | |
| 636 | compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; | |
| 637 | reg = <0 0xe6e32000 0 0x8>; | |
| 638 | #pwm-cells = <2>; | |
| 639 | clocks = <&cpg CPG_MOD 523>; | |
| 640 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 641 | resets = <&cpg 523>; | |
| 642 | status = "disabled"; | |
| 643 | }; | |
| 644 | ||
| 645 | pwm3: pwm@e6e33000 { | |
| 646 | compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar"; | |
| 647 | reg = <0 0xe6e33000 0 0x8>; | |
| 648 | #pwm-cells = <2>; | |
| 649 | clocks = <&cpg CPG_MOD 523>; | |
| 650 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 651 | resets = <&cpg 523>; | |
| 652 | status = "disabled"; | |
| 653 | }; | |
| 654 | ||
| 30316c4f TK |
655 | scif0: serial@e6e60000 { |
| 656 | compatible = "renesas,scif-r8a77995", | |
| 657 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
| 658 | reg = <0 0xe6e60000 0 64>; | |
| 659 | interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; | |
| 660 | clocks = <&cpg CPG_MOD 207>, | |
| 661 | <&cpg CPG_CORE R8A77995_CLK_S3D1C>, | |
| 662 | <&scif_clk>; | |
| 663 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 664 | dmas = <&dmac1 0x51>, <&dmac1 0x50>, | |
| 665 | <&dmac2 0x51>, <&dmac2 0x50>; | |
| 666 | dma-names = "tx", "rx", "tx", "rx"; | |
| 667 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 668 | resets = <&cpg 207>; | |
| 669 | status = "disabled"; | |
| 670 | }; | |
| 671 | ||
| 672 | scif1: serial@e6e68000 { | |
| 673 | compatible = "renesas,scif-r8a77995", | |
| 674 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
| 675 | reg = <0 0xe6e68000 0 64>; | |
| 676 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; | |
| 677 | clocks = <&cpg CPG_MOD 206>, | |
| 678 | <&cpg CPG_CORE R8A77995_CLK_S3D1C>, | |
| 679 | <&scif_clk>; | |
| 680 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 681 | dmas = <&dmac1 0x53>, <&dmac1 0x52>, | |
| 682 | <&dmac2 0x53>, <&dmac2 0x52>; | |
| 683 | dma-names = "tx", "rx", "tx", "rx"; | |
| 684 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 685 | resets = <&cpg 206>; | |
| 686 | status = "disabled"; | |
| 687 | }; | |
| 688 | ||
| 7c55747f YK |
689 | scif2: serial@e6e88000 { |
| 690 | compatible = "renesas,scif-r8a77995", | |
| 691 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
| 692 | reg = <0 0xe6e88000 0 64>; | |
| 693 | interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; | |
| 694 | clocks = <&cpg CPG_MOD 310>, | |
| 695 | <&cpg CPG_CORE R8A77995_CLK_S3D1C>, | |
| 696 | <&scif_clk>; | |
| 697 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 698 | dmas = <&dmac1 0x13>, <&dmac1 0x12>, | |
| 699 | <&dmac2 0x13>, <&dmac2 0x12>; | |
| 700 | dma-names = "tx", "rx", "tx", "rx"; | |
| 83f18749 | 701 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; |
| 7c55747f | 702 | resets = <&cpg 310>; |
| 83f18749 UH |
703 | status = "disabled"; |
| 704 | }; | |
| 6b284a81 | 705 | |
| 30316c4f TK |
706 | scif3: serial@e6c50000 { |
| 707 | compatible = "renesas,scif-r8a77995", | |
| 708 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
| 709 | reg = <0 0xe6c50000 0 64>; | |
| 710 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
| 711 | clocks = <&cpg CPG_MOD 204>, | |
| 712 | <&cpg CPG_CORE R8A77995_CLK_S3D1C>, | |
| 713 | <&scif_clk>; | |
| 714 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 715 | dmas = <&dmac0 0x57>, <&dmac0 0x56>; | |
| 716 | dma-names = "tx", "rx"; | |
| 717 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 718 | resets = <&cpg 204>; | |
| 719 | status = "disabled"; | |
| 720 | }; | |
| 721 | ||
| 722 | scif4: serial@e6c40000 { | |
| 723 | compatible = "renesas,scif-r8a77995", | |
| 724 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
| 725 | reg = <0 0xe6c40000 0 64>; | |
| 726 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
| 727 | clocks = <&cpg CPG_MOD 203>, | |
| 728 | <&cpg CPG_CORE R8A77995_CLK_S3D1C>, | |
| 729 | <&scif_clk>; | |
| 730 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 731 | dmas = <&dmac0 0x59>, <&dmac0 0x58>; | |
| 732 | dma-names = "tx", "rx"; | |
| 733 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 734 | resets = <&cpg 203>; | |
| 735 | status = "disabled"; | |
| 736 | }; | |
| 737 | ||
| 738 | scif5: serial@e6f30000 { | |
| 739 | compatible = "renesas,scif-r8a77995", | |
| 740 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
| 741 | reg = <0 0xe6f30000 0 64>; | |
| 742 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
| 743 | clocks = <&cpg CPG_MOD 202>, | |
| 744 | <&cpg CPG_CORE R8A77995_CLK_S3D1C>, | |
| 745 | <&scif_clk>; | |
| 746 | clock-names = "fck", "brg_int", "scif_clk"; | |
| 747 | dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, | |
| 748 | <&dmac2 0x5b>, <&dmac2 0x5a>; | |
| 749 | dma-names = "tx", "rx", "tx", "rx"; | |
| 750 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 751 | resets = <&cpg 202>; | |
| 752 | status = "disabled"; | |
| 753 | }; | |
| 754 | ||
| 6b284a81 HY |
755 | msiof0: spi@e6e90000 { |
| 756 | compatible = "renesas,msiof-r8a77995", | |
| 757 | "renesas,rcar-gen3-msiof"; | |
| 758 | reg = <0 0xe6e90000 0 0x64>; | |
| 759 | interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; | |
| 760 | clocks = <&cpg CPG_MOD 211>; | |
| 761 | dmas = <&dmac1 0x41>, <&dmac1 0x40>, | |
| 762 | <&dmac2 0x41>, <&dmac2 0x40>; | |
| 763 | dma-names = "tx", "rx", "tx", "rx"; | |
| 764 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 765 | resets = <&cpg 211>; | |
| 766 | #address-cells = <1>; | |
| 767 | #size-cells = <0>; | |
| 768 | status = "disabled"; | |
| 769 | }; | |
| 770 | ||
| 771 | msiof1: spi@e6ea0000 { | |
| 772 | compatible = "renesas,msiof-r8a77995", | |
| 773 | "renesas,rcar-gen3-msiof"; | |
| 774 | reg = <0 0xe6ea0000 0 0x64>; | |
| 775 | interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; | |
| 776 | clocks = <&cpg CPG_MOD 210>; | |
| 777 | dmas = <&dmac1 0x43>, <&dmac1 0x42>, | |
| 778 | <&dmac2 0x43>, <&dmac2 0x42>; | |
| 779 | dma-names = "tx", "rx", "tx", "rx"; | |
| 780 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 781 | resets = <&cpg 210>; | |
| 782 | #address-cells = <1>; | |
| 783 | #size-cells = <0>; | |
| 784 | status = "disabled"; | |
| 785 | }; | |
| 786 | ||
| 787 | msiof2: spi@e6c00000 { | |
| 788 | compatible = "renesas,msiof-r8a77995", | |
| 789 | "renesas,rcar-gen3-msiof"; | |
| 790 | reg = <0 0xe6c00000 0 0x64>; | |
| 791 | interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; | |
| 792 | clocks = <&cpg CPG_MOD 209>; | |
| 793 | dmas = <&dmac0 0x45>, <&dmac0 0x44>; | |
| 794 | dma-names = "tx", "rx"; | |
| 795 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 796 | resets = <&cpg 209>; | |
| 797 | #address-cells = <1>; | |
| 798 | #size-cells = <0>; | |
| 799 | status = "disabled"; | |
| 800 | }; | |
| 801 | ||
| 802 | msiof3: spi@e6c10000 { | |
| 803 | compatible = "renesas,msiof-r8a77995", | |
| 804 | "renesas,rcar-gen3-msiof"; | |
| 805 | reg = <0 0xe6c10000 0 0x64>; | |
| 806 | interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; | |
| 807 | clocks = <&cpg CPG_MOD 208>; | |
| 808 | dmas = <&dmac0 0x47>, <&dmac0 0x46>; | |
| 809 | dma-names = "tx", "rx"; | |
| 810 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 811 | resets = <&cpg 208>; | |
| 812 | #address-cells = <1>; | |
| 813 | #size-cells = <0>; | |
| 814 | status = "disabled"; | |
| 815 | }; | |
| 83f18749 | 816 | |
| d86bd47f JM |
817 | vin4: video@e6ef4000 { |
| 818 | compatible = "renesas,vin-r8a77995"; | |
| 819 | reg = <0 0xe6ef4000 0 0x1000>; | |
| 820 | interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; | |
| 821 | clocks = <&cpg CPG_MOD 807>; | |
| 822 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 823 | resets = <&cpg 807>; | |
| 824 | renesas,id = <4>; | |
| 825 | status = "disabled"; | |
| 826 | }; | |
| 827 | ||
| 7c55747f YK |
828 | ohci0: usb@ee080000 { |
| 829 | compatible = "generic-ohci"; | |
| 830 | reg = <0 0xee080000 0 0x100>; | |
| 423254a1 | 831 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| 737e05bf | 832 | clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; |
| 423254a1 YS |
833 | phys = <&usb2_phy0>; |
| 834 | phy-names = "usb"; | |
| 423254a1 | 835 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; |
| 737e05bf | 836 | resets = <&cpg 703>, <&cpg 704>; |
| 423254a1 YS |
837 | status = "disabled"; |
| 838 | }; | |
| 839 | ||
| 7c55747f YK |
840 | ehci0: usb@ee080100 { |
| 841 | compatible = "generic-ehci"; | |
| 842 | reg = <0 0xee080100 0 0x100>; | |
| 423254a1 | 843 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| 737e05bf | 844 | clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; |
| 423254a1 YS |
845 | phys = <&usb2_phy0>; |
| 846 | phy-names = "usb"; | |
| 7c55747f | 847 | companion = <&ohci0>; |
| 423254a1 | 848 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; |
| 737e05bf | 849 | resets = <&cpg 703>, <&cpg 704>; |
| 423254a1 YS |
850 | status = "disabled"; |
| 851 | }; | |
| 852 | ||
| a0ea7fe8 YS |
853 | usb2_phy0: usb-phy@ee080200 { |
| 854 | compatible = "renesas,usb2-phy-r8a77995", | |
| 855 | "renesas,rcar-gen3-usb2-phy"; | |
| 856 | reg = <0 0xee080200 0 0x700>; | |
| 857 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; | |
| 737e05bf | 858 | clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; |
| a0ea7fe8 | 859 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; |
| 737e05bf | 860 | resets = <&cpg 703>, <&cpg 704>; |
| a0ea7fe8 YS |
861 | #phy-cells = <0>; |
| 862 | status = "disabled"; | |
| 863 | }; | |
| d7ef367b | 864 | |
| 7c55747f YK |
865 | sdhi2: sd@ee140000 { |
| 866 | compatible = "renesas,sdhi-r8a77995", | |
| 867 | "renesas,rcar-gen3-sdhi"; | |
| 868 | reg = <0 0xee140000 0 0x2000>; | |
| 869 | interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; | |
| 870 | clocks = <&cpg CPG_MOD 312>; | |
| 871 | max-frequency = <200000000>; | |
| 872 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 873 | resets = <&cpg 312>; | |
| 874 | status = "disabled"; | |
| 875 | }; | |
| 876 | ||
| 877 | gic: interrupt-controller@f1010000 { | |
| 878 | compatible = "arm,gic-400"; | |
| 879 | #interrupt-cells = <3>; | |
| 880 | #address-cells = <0>; | |
| 881 | interrupt-controller; | |
| 882 | reg = <0x0 0xf1010000 0 0x1000>, | |
| 883 | <0x0 0xf1020000 0 0x20000>, | |
| 884 | <0x0 0xf1040000 0 0x20000>, | |
| 885 | <0x0 0xf1060000 0 0x20000>; | |
| 886 | interrupts = <GIC_PPI 9 | |
| 887 | (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; | |
| 888 | clocks = <&cpg CPG_MOD 408>; | |
| 889 | clock-names = "clk"; | |
| 890 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 891 | resets = <&cpg 408>; | |
| 892 | }; | |
| 893 | ||
| 295952a1 KB |
894 | vspbs: vsp@fe960000 { |
| 895 | compatible = "renesas,vsp2"; | |
| 896 | reg = <0 0xfe960000 0 0x8000>; | |
| 897 | interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; | |
| 898 | clocks = <&cpg CPG_MOD 627>; | |
| 899 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 900 | resets = <&cpg 627>; | |
| 901 | renesas,fcp = <&fcpvb0>; | |
| 902 | }; | |
| 903 | ||
| 295952a1 KB |
904 | vspd0: vsp@fea20000 { |
| 905 | compatible = "renesas,vsp2"; | |
| e21adc78 | 906 | reg = <0 0xfea20000 0 0x5000>; |
| 295952a1 KB |
907 | interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; |
| 908 | clocks = <&cpg CPG_MOD 623>; | |
| 909 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 910 | resets = <&cpg 623>; | |
| 911 | renesas,fcp = <&fcpvd0>; | |
| 912 | }; | |
| 913 | ||
| 295952a1 KB |
914 | vspd1: vsp@fea28000 { |
| 915 | compatible = "renesas,vsp2"; | |
| e21adc78 | 916 | reg = <0 0xfea28000 0 0x5000>; |
| 295952a1 KB |
917 | interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; |
| 918 | clocks = <&cpg CPG_MOD 622>; | |
| 919 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 920 | resets = <&cpg 622>; | |
| 921 | renesas,fcp = <&fcpvd1>; | |
| 922 | }; | |
| 923 | ||
| 7c55747f YK |
924 | fcpvb0: fcp@fe96f000 { |
| 925 | compatible = "renesas,fcpv"; | |
| 926 | reg = <0 0xfe96f000 0 0x200>; | |
| 927 | clocks = <&cpg CPG_MOD 607>; | |
| 928 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 929 | resets = <&cpg 607>; | |
| 930 | iommus = <&ipmmu_vp0 5>; | |
| 931 | }; | |
| 932 | ||
| 933 | fcpvd0: fcp@fea27000 { | |
| 934 | compatible = "renesas,fcpv"; | |
| 935 | reg = <0 0xfea27000 0 0x200>; | |
| 936 | clocks = <&cpg CPG_MOD 603>; | |
| 937 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 938 | resets = <&cpg 603>; | |
| 939 | iommus = <&ipmmu_vi0 8>; | |
| 940 | }; | |
| 941 | ||
| d7ef367b KB |
942 | fcpvd1: fcp@fea2f000 { |
| 943 | compatible = "renesas,fcpv"; | |
| 944 | reg = <0 0xfea2f000 0 0x200>; | |
| 945 | clocks = <&cpg CPG_MOD 602>; | |
| 946 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 947 | resets = <&cpg 602>; | |
| 948 | iommus = <&ipmmu_vi0 9>; | |
| 949 | }; | |
| 18f1a773 KB |
950 | |
| 951 | du: display@feb00000 { | |
| 952 | compatible = "renesas,du-r8a77995"; | |
| 953 | reg = <0 0xfeb00000 0 0x80000>; | |
| 954 | interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, | |
| 955 | <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; | |
| 956 | clocks = <&cpg CPG_MOD 724>, | |
| 957 | <&cpg CPG_MOD 723>; | |
| 958 | clock-names = "du.0", "du.1"; | |
| 959 | vsps = <&vspd0 0 &vspd1 0>; | |
| 960 | status = "disabled"; | |
| 961 | ||
| 962 | ports { | |
| 963 | #address-cells = <1>; | |
| 964 | #size-cells = <0>; | |
| 965 | ||
| 966 | port@0 { | |
| 967 | reg = <0>; | |
| 968 | du_out_rgb: endpoint { | |
| 969 | }; | |
| 970 | }; | |
| 971 | ||
| 972 | port@1 { | |
| 973 | reg = <1>; | |
| 974 | du_out_lvds0: endpoint { | |
| 0dc73398 | 975 | remote-endpoint = <&lvds0_in>; |
| 18f1a773 KB |
976 | }; |
| 977 | }; | |
| 978 | ||
| 979 | port@2 { | |
| 980 | reg = <2>; | |
| 981 | du_out_lvds1: endpoint { | |
| 0dc73398 KB |
982 | remote-endpoint = <&lvds1_in>; |
| 983 | }; | |
| 984 | }; | |
| 985 | }; | |
| 986 | }; | |
| 987 | ||
| 988 | lvds0: lvds-encoder@feb90000 { | |
| 989 | compatible = "renesas,r8a77995-lvds"; | |
| 990 | reg = <0 0xfeb90000 0 0x20>; | |
| 991 | clocks = <&cpg CPG_MOD 727>; | |
| 992 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 993 | resets = <&cpg 727>; | |
| 994 | status = "disabled"; | |
| 995 | ||
| 996 | ports { | |
| 997 | #address-cells = <1>; | |
| 998 | #size-cells = <0>; | |
| 999 | ||
| 1000 | port@0 { | |
| 1001 | reg = <0>; | |
| 1002 | lvds0_in: endpoint { | |
| 1003 | remote-endpoint = <&du_out_lvds0>; | |
| 1004 | }; | |
| 1005 | }; | |
| 1006 | ||
| 1007 | port@1 { | |
| 1008 | reg = <1>; | |
| 1009 | lvds0_out: endpoint { | |
| 1010 | }; | |
| 1011 | }; | |
| 1012 | }; | |
| 1013 | }; | |
| 1014 | ||
| 1015 | lvds1: lvds-encoder@feb90100 { | |
| 1016 | compatible = "renesas,r8a77995-lvds"; | |
| 1017 | reg = <0 0xfeb90100 0 0x20>; | |
| 1018 | clocks = <&cpg CPG_MOD 727>; | |
| 1019 | power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; | |
| 1020 | resets = <&cpg 726>; | |
| 1021 | status = "disabled"; | |
| 1022 | ||
| 1023 | ports { | |
| 1024 | #address-cells = <1>; | |
| 1025 | #size-cells = <0>; | |
| 1026 | ||
| 1027 | port@0 { | |
| 1028 | reg = <0>; | |
| 1029 | lvds1_in: endpoint { | |
| 1030 | remote-endpoint = <&du_out_lvds1>; | |
| 1031 | }; | |
| 1032 | }; | |
| 1033 | ||
| 1034 | port@1 { | |
| 1035 | reg = <1>; | |
| 1036 | lvds1_out: endpoint { | |
| 18f1a773 KB |
1037 | }; |
| 1038 | }; | |
| 1039 | }; | |
| 1040 | }; | |
| 7c55747f YK |
1041 | |
| 1042 | prr: chipid@fff00044 { | |
| 1043 | compatible = "renesas,prr"; | |
| 1044 | reg = <0 0xfff00044 0 4>; | |
| 1045 | }; | |
| d917e0b2 | 1046 | }; |
| f320eead | 1047 | |
| 21bd0538 YK |
1048 | thermal-zones { |
| 1049 | cpu_thermal: cpu-thermal { | |
| 1050 | polling-delay-passive = <250>; | |
| 1051 | polling-delay = <1000>; | |
| 1052 | thermal-sensors = <&thermal>; | |
| 1053 | ||
| 1054 | trips { | |
| 1055 | cpu-crit { | |
| 1056 | temperature = <120000>; | |
| 1057 | hysteresis = <2000>; | |
| 1058 | type = "critical"; | |
| 1059 | }; | |
| 1060 | }; | |
| 1061 | ||
| 1062 | cooling-maps { | |
| 1063 | }; | |
| 1064 | }; | |
| 1065 | }; | |
| 1066 | ||
| f320eead SH |
1067 | timer { |
| 1068 | compatible = "arm,armv8-timer"; | |
| 1069 | interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, | |
| 1070 | <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, | |
| 1071 | <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, | |
| 1072 | <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; | |
| 1073 | }; | |
| d917e0b2 | 1074 | }; |