projects / mirror_ubuntu-focal-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 270e0c3e MY |
1 | /* |
| 2 | * Device Tree Source for UniPhier LD11 SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2016 Socionext Inc. | |
| 5 | * Author: Masahiro Yamada <yamada.masahiro@socionext.com> | |
| 6 | * | |
| 12301cff | 7 | * SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 270e0c3e MY |
8 | */ |
| 9 | ||
| 79d4be39 | 10 | /memreserve/ 0x80000000 0x02000000; |
| 270e0c3e MY |
11 | |
| 12 | / { | |
| 13 | compatible = "socionext,uniphier-ld11"; | |
| 14 | #address-cells = <2>; | |
| 15 | #size-cells = <2>; | |
| 16 | interrupt-parent = <&gic>; | |
| 17 | ||
| 18 | cpus { | |
| 19 | #address-cells = <2>; | |
| 20 | #size-cells = <0>; | |
| 21 | ||
| 22 | cpu-map { | |
| 23 | cluster0 { | |
| 24 | core0 { | |
| 25 | cpu = <&cpu0>; | |
| 26 | }; | |
| 27 | core1 { | |
| 28 | cpu = <&cpu1>; | |
| 29 | }; | |
| 30 | }; | |
| 31 | }; | |
| 32 | ||
| 33 | cpu0: cpu@0 { | |
| 34 | device_type = "cpu"; | |
| 35 | compatible = "arm,cortex-a53", "arm,armv8"; | |
| 36 | reg = <0 0x000>; | |
| bdb81836 | 37 | clocks = <&sys_clk 33>; |
| 2f81137f | 38 | enable-method = "psci"; |
| bdb81836 | 39 | operating-points-v2 = <&cluster0_opp>; |
| 270e0c3e MY |
40 | }; |
| 41 | ||
| 42 | cpu1: cpu@1 { | |
| 43 | device_type = "cpu"; | |
| 44 | compatible = "arm,cortex-a53", "arm,armv8"; | |
| 45 | reg = <0 0x001>; | |
| bdb81836 | 46 | clocks = <&sys_clk 33>; |
| 2f81137f | 47 | enable-method = "psci"; |
| bdb81836 MY |
48 | operating-points-v2 = <&cluster0_opp>; |
| 49 | }; | |
| 50 | }; | |
| 51 | ||
| 52 | cluster0_opp: opp_table { | |
| 53 | compatible = "operating-points-v2"; | |
| 54 | opp-shared; | |
| 55 | ||
| 3fc9a121 | 56 | opp-245000000 { |
| bdb81836 MY |
57 | opp-hz = /bits/ 64 <245000000>; |
| 58 | clock-latency-ns = <300>; | |
| 59 | }; | |
| 3fc9a121 | 60 | opp-250000000 { |
| bdb81836 MY |
61 | opp-hz = /bits/ 64 <250000000>; |
| 62 | clock-latency-ns = <300>; | |
| 63 | }; | |
| 3fc9a121 | 64 | opp-490000000 { |
| bdb81836 MY |
65 | opp-hz = /bits/ 64 <490000000>; |
| 66 | clock-latency-ns = <300>; | |
| 67 | }; | |
| 3fc9a121 | 68 | opp-500000000 { |
| bdb81836 MY |
69 | opp-hz = /bits/ 64 <500000000>; |
| 70 | clock-latency-ns = <300>; | |
| 71 | }; | |
| 3fc9a121 | 72 | opp-653334000 { |
| bdb81836 MY |
73 | opp-hz = /bits/ 64 <653334000>; |
| 74 | clock-latency-ns = <300>; | |
| 75 | }; | |
| 3fc9a121 | 76 | opp-666667000 { |
| bdb81836 MY |
77 | opp-hz = /bits/ 64 <666667000>; |
| 78 | clock-latency-ns = <300>; | |
| 79 | }; | |
| 3fc9a121 | 80 | opp-980000000 { |
| bdb81836 MY |
81 | opp-hz = /bits/ 64 <980000000>; |
| 82 | clock-latency-ns = <300>; | |
| 270e0c3e MY |
83 | }; |
| 84 | }; | |
| 85 | ||
| 2f81137f MY |
86 | psci { |
| 87 | compatible = "arm,psci-1.0"; | |
| 88 | method = "smc"; | |
| 89 | }; | |
| 90 | ||
| 270e0c3e MY |
91 | clocks { |
| 92 | refclk: ref { | |
| 93 | compatible = "fixed-clock"; | |
| 94 | #clock-cells = <0>; | |
| 95 | clock-frequency = <25000000>; | |
| 96 | }; | |
| 97 | }; | |
| 98 | ||
| 99 | timer { | |
| 100 | compatible = "arm,armv8-timer"; | |
| 101 | interrupts = <1 13 4>, | |
| 102 | <1 14 4>, | |
| 103 | <1 11 4>, | |
| 104 | <1 10 4>; | |
| 105 | }; | |
| 106 | ||
| b5027603 | 107 | soc@0 { |
| 270e0c3e MY |
108 | compatible = "simple-bus"; |
| 109 | #address-cells = <1>; | |
| 110 | #size-cells = <1>; | |
| 111 | ranges = <0 0 0 0xffffffff>; | |
| 112 | ||
| 113 | serial0: serial@54006800 { | |
| 114 | compatible = "socionext,uniphier-uart"; | |
| 115 | status = "disabled"; | |
| 116 | reg = <0x54006800 0x40>; | |
| 117 | interrupts = <0 33 4>; | |
| 118 | pinctrl-names = "default"; | |
| 119 | pinctrl-0 = <&pinctrl_uart0>; | |
| 120 | clocks = <&peri_clk 0>; | |
| 121 | }; | |
| 122 | ||
| 123 | serial1: serial@54006900 { | |
| 124 | compatible = "socionext,uniphier-uart"; | |
| 125 | status = "disabled"; | |
| 126 | reg = <0x54006900 0x40>; | |
| 127 | interrupts = <0 35 4>; | |
| 128 | pinctrl-names = "default"; | |
| 129 | pinctrl-0 = <&pinctrl_uart1>; | |
| 130 | clocks = <&peri_clk 1>; | |
| 131 | }; | |
| 132 | ||
| 133 | serial2: serial@54006a00 { | |
| 134 | compatible = "socionext,uniphier-uart"; | |
| 135 | status = "disabled"; | |
| 136 | reg = <0x54006a00 0x40>; | |
| 137 | interrupts = <0 37 4>; | |
| 138 | pinctrl-names = "default"; | |
| 139 | pinctrl-0 = <&pinctrl_uart2>; | |
| 140 | clocks = <&peri_clk 2>; | |
| 141 | }; | |
| 142 | ||
| 143 | serial3: serial@54006b00 { | |
| 144 | compatible = "socionext,uniphier-uart"; | |
| 145 | status = "disabled"; | |
| 146 | reg = <0x54006b00 0x40>; | |
| 147 | interrupts = <0 177 4>; | |
| 148 | pinctrl-names = "default"; | |
| 149 | pinctrl-0 = <&pinctrl_uart3>; | |
| 150 | clocks = <&peri_clk 3>; | |
| 151 | }; | |
| 152 | ||
| 178b3568 KS |
153 | adamv@57920000 { |
| 154 | compatible = "socionext,uniphier-ld11-adamv", | |
| 155 | "simple-mfd", "syscon"; | |
| 156 | reg = <0x57920000 0x1000>; | |
| 157 | ||
| 158 | adamv_rst: reset { | |
| 159 | compatible = "socionext,uniphier-ld11-adamv-reset"; | |
| 160 | #reset-cells = <1>; | |
| 161 | }; | |
| 162 | }; | |
| 163 | ||
| 270e0c3e MY |
164 | i2c0: i2c@58780000 { |
| 165 | compatible = "socionext,uniphier-fi2c"; | |
| 166 | status = "disabled"; | |
| 167 | reg = <0x58780000 0x80>; | |
| 168 | #address-cells = <1>; | |
| 169 | #size-cells = <0>; | |
| 170 | interrupts = <0 41 4>; | |
| 171 | pinctrl-names = "default"; | |
| 172 | pinctrl-0 = <&pinctrl_i2c0>; | |
| 173 | clocks = <&peri_clk 4>; | |
| 174 | clock-frequency = <100000>; | |
| 175 | }; | |
| 176 | ||
| 177 | i2c1: i2c@58781000 { | |
| 178 | compatible = "socionext,uniphier-fi2c"; | |
| 179 | status = "disabled"; | |
| 180 | reg = <0x58781000 0x80>; | |
| 181 | #address-cells = <1>; | |
| 182 | #size-cells = <0>; | |
| 183 | interrupts = <0 42 4>; | |
| 184 | pinctrl-names = "default"; | |
| 185 | pinctrl-0 = <&pinctrl_i2c1>; | |
| 186 | clocks = <&peri_clk 5>; | |
| 187 | clock-frequency = <100000>; | |
| 188 | }; | |
| 189 | ||
| 190 | i2c2: i2c@58782000 { | |
| 191 | compatible = "socionext,uniphier-fi2c"; | |
| 192 | reg = <0x58782000 0x80>; | |
| 193 | #address-cells = <1>; | |
| 194 | #size-cells = <0>; | |
| 195 | interrupts = <0 43 4>; | |
| 196 | clocks = <&peri_clk 6>; | |
| 197 | clock-frequency = <400000>; | |
| 198 | }; | |
| 199 | ||
| 200 | i2c3: i2c@58783000 { | |
| 201 | compatible = "socionext,uniphier-fi2c"; | |
| 202 | status = "disabled"; | |
| 203 | reg = <0x58783000 0x80>; | |
| 204 | #address-cells = <1>; | |
| 205 | #size-cells = <0>; | |
| 206 | interrupts = <0 44 4>; | |
| 207 | pinctrl-names = "default"; | |
| 208 | pinctrl-0 = <&pinctrl_i2c3>; | |
| 209 | clocks = <&peri_clk 7>; | |
| 210 | clock-frequency = <100000>; | |
| 211 | }; | |
| 212 | ||
| 213 | i2c4: i2c@58784000 { | |
| 214 | compatible = "socionext,uniphier-fi2c"; | |
| 215 | status = "disabled"; | |
| 216 | reg = <0x58784000 0x80>; | |
| 217 | #address-cells = <1>; | |
| 218 | #size-cells = <0>; | |
| 219 | interrupts = <0 45 4>; | |
| 220 | pinctrl-names = "default"; | |
| 221 | pinctrl-0 = <&pinctrl_i2c4>; | |
| 222 | clocks = <&peri_clk 8>; | |
| 223 | clock-frequency = <100000>; | |
| 224 | }; | |
| 225 | ||
| 226 | i2c5: i2c@58785000 { | |
| 227 | compatible = "socionext,uniphier-fi2c"; | |
| 228 | reg = <0x58785000 0x80>; | |
| 229 | #address-cells = <1>; | |
| 230 | #size-cells = <0>; | |
| 231 | interrupts = <0 25 4>; | |
| 232 | clocks = <&peri_clk 9>; | |
| 233 | clock-frequency = <400000>; | |
| 234 | }; | |
| 235 | ||
| 236 | system_bus: system-bus@58c00000 { | |
| 237 | compatible = "socionext,uniphier-system-bus"; | |
| 238 | status = "disabled"; | |
| 239 | reg = <0x58c00000 0x400>; | |
| 240 | #address-cells = <2>; | |
| 241 | #size-cells = <1>; | |
| 242 | pinctrl-names = "default"; | |
| 243 | pinctrl-0 = <&pinctrl_system_bus>; | |
| 244 | }; | |
| 245 | ||
| b10ee7e3 | 246 | smpctrl@59801000 { |
| 270e0c3e MY |
247 | compatible = "socionext,uniphier-smpctrl"; |
| 248 | reg = <0x59801000 0x400>; | |
| 249 | }; | |
| 250 | ||
| 8f32b812 MY |
251 | sdctrl@59810000 { |
| 252 | compatible = "socionext,uniphier-ld11-sdctrl", | |
| 253 | "simple-mfd", "syscon"; | |
| 254 | reg = <0x59810000 0x400>; | |
| 255 | ||
| 256 | sd_rst: reset { | |
| 257 | compatible = "socionext,uniphier-ld11-sd-reset"; | |
| 258 | #reset-cells = <1>; | |
| 259 | }; | |
| 260 | }; | |
| 261 | ||
| 270e0c3e | 262 | perictrl@59820000 { |
| fb28cef0 | 263 | compatible = "socionext,uniphier-ld11-perictrl", |
| 270e0c3e MY |
264 | "simple-mfd", "syscon"; |
| 265 | reg = <0x59820000 0x200>; | |
| 266 | ||
| 267 | peri_clk: clock { | |
| 268 | compatible = "socionext,uniphier-ld11-peri-clock"; | |
| 269 | #clock-cells = <1>; | |
| 270 | }; | |
| 271 | ||
| 272 | peri_rst: reset { | |
| 273 | compatible = "socionext,uniphier-ld11-peri-reset"; | |
| 274 | #reset-cells = <1>; | |
| 275 | }; | |
| 276 | }; | |
| 277 | ||
| 3a93cc26 MY |
278 | emmc: sdhc@5a000000 { |
| 279 | compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; | |
| 280 | reg = <0x5a000000 0x400>; | |
| 281 | interrupts = <0 78 4>; | |
| 9c0a9700 MY |
282 | pinctrl-names = "default"; |
| 283 | pinctrl-0 = <&pinctrl_emmc>; | |
| 3a93cc26 MY |
284 | clocks = <&sys_clk 4>; |
| 285 | bus-width = <8>; | |
| 286 | mmc-ddr-1_8v; | |
| 287 | mmc-hs200-1_8v; | |
| ba6f7011 MY |
288 | cdns,phy-input-delay-legacy = <4>; |
| 289 | cdns,phy-input-delay-mmc-highspeed = <2>; | |
| 290 | cdns,phy-input-delay-mmc-ddr = <3>; | |
| e345eded MY |
291 | cdns,phy-dll-delay-sdclk = <21>; |
| 292 | cdns,phy-dll-delay-sdclk-hsmmc = <21>; | |
| 3a93cc26 MY |
293 | }; |
| 294 | ||
| 270e0c3e MY |
295 | usb0: usb@5a800100 { |
| 296 | compatible = "socionext,uniphier-ehci", "generic-ehci"; | |
| 297 | status = "disabled"; | |
| 298 | reg = <0x5a800100 0x100>; | |
| 299 | interrupts = <0 243 4>; | |
| 300 | pinctrl-names = "default"; | |
| 301 | pinctrl-0 = <&pinctrl_usb0>; | |
| deaa5519 MY |
302 | clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, |
| 303 | <&mio_clk 12>; | |
| 7a201e31 MY |
304 | resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, |
| 305 | <&mio_rst 12>; | |
| 270e0c3e MY |
306 | }; |
| 307 | ||
| 308 | usb1: usb@5a810100 { | |
| 309 | compatible = "socionext,uniphier-ehci", "generic-ehci"; | |
| 310 | status = "disabled"; | |
| 311 | reg = <0x5a810100 0x100>; | |
| 312 | interrupts = <0 244 4>; | |
| 313 | pinctrl-names = "default"; | |
| 314 | pinctrl-0 = <&pinctrl_usb1>; | |
| deaa5519 MY |
315 | clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, |
| 316 | <&mio_clk 13>; | |
| 7a201e31 MY |
317 | resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, |
| 318 | <&mio_rst 13>; | |
| 270e0c3e MY |
319 | }; |
| 320 | ||
| 321 | usb2: usb@5a820100 { | |
| 322 | compatible = "socionext,uniphier-ehci", "generic-ehci"; | |
| 323 | status = "disabled"; | |
| 324 | reg = <0x5a820100 0x100>; | |
| 325 | interrupts = <0 245 4>; | |
| 326 | pinctrl-names = "default"; | |
| 327 | pinctrl-0 = <&pinctrl_usb2>; | |
| deaa5519 MY |
328 | clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, |
| 329 | <&mio_clk 14>; | |
| 7a201e31 MY |
330 | resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, |
| 331 | <&mio_rst 14>; | |
| 270e0c3e MY |
332 | }; |
| 333 | ||
| 334 | mioctrl@5b3e0000 { | |
| fb28cef0 | 335 | compatible = "socionext,uniphier-ld11-mioctrl", |
| 270e0c3e MY |
336 | "simple-mfd", "syscon"; |
| 337 | reg = <0x5b3e0000 0x800>; | |
| 338 | ||
| 339 | mio_clk: clock { | |
| 340 | compatible = "socionext,uniphier-ld11-mio-clock"; | |
| 341 | #clock-cells = <1>; | |
| 342 | }; | |
| 343 | ||
| 344 | mio_rst: reset { | |
| 345 | compatible = "socionext,uniphier-ld11-mio-reset"; | |
| 346 | #reset-cells = <1>; | |
| 347 | resets = <&sys_rst 7>; | |
| 348 | }; | |
| 349 | }; | |
| 350 | ||
| 351 | soc-glue@5f800000 { | |
| fb28cef0 | 352 | compatible = "socionext,uniphier-ld11-soc-glue", |
| 270e0c3e MY |
353 | "simple-mfd", "syscon"; |
| 354 | reg = <0x5f800000 0x2000>; | |
| 355 | ||
| 356 | pinctrl: pinctrl { | |
| 357 | compatible = "socionext,uniphier-ld11-pinctrl"; | |
| 358 | }; | |
| 359 | }; | |
| 360 | ||
| 3dfc6e98 MY |
361 | aidet: aidet@5fc20000 { |
| 362 | compatible = "socionext,uniphier-ld11-aidet"; | |
| 363 | reg = <0x5fc20000 0x200>; | |
| 364 | interrupt-controller; | |
| 365 | #interrupt-cells = <2>; | |
| 366 | }; | |
| 367 | ||
| 270e0c3e MY |
368 | gic: interrupt-controller@5fe00000 { |
| 369 | compatible = "arm,gic-v3"; | |
| 370 | reg = <0x5fe00000 0x10000>, /* GICD */ | |
| 371 | <0x5fe40000 0x80000>; /* GICR */ | |
| 372 | interrupt-controller; | |
| 373 | #interrupt-cells = <3>; | |
| 374 | interrupts = <1 9 4>; | |
| 375 | }; | |
| 376 | ||
| 377 | sysctrl@61840000 { | |
| 378 | compatible = "socionext,uniphier-ld11-sysctrl", | |
| 379 | "simple-mfd", "syscon"; | |
| 1ef64af8 | 380 | reg = <0x61840000 0x10000>; |
| 270e0c3e MY |
381 | |
| 382 | sys_clk: clock { | |
| 383 | compatible = "socionext,uniphier-ld11-clock"; | |
| 384 | #clock-cells = <1>; | |
| 385 | }; | |
| 386 | ||
| 387 | sys_rst: reset { | |
| 388 | compatible = "socionext,uniphier-ld11-reset"; | |
| 389 | #reset-cells = <1>; | |
| 390 | }; | |
| 4c4c960a KH |
391 | |
| 392 | watchdog { | |
| 393 | compatible = "socionext,uniphier-wdt"; | |
| 394 | }; | |
| 270e0c3e | 395 | }; |
| e5aefb38 MY |
396 | |
| 397 | nand: nand@68000000 { | |
| 398 | compatible = "socionext,uniphier-denali-nand-v5b"; | |
| 399 | status = "disabled"; | |
| 400 | reg-names = "nand_data", "denali_reg"; | |
| 401 | reg = <0x68000000 0x20>, <0x68100000 0x1000>; | |
| 402 | interrupts = <0 65 4>; | |
| 403 | pinctrl-names = "default"; | |
| 404 | pinctrl-0 = <&pinctrl_nand>; | |
| 405 | clocks = <&sys_clk 2>; | |
| 406 | }; | |
| 270e0c3e MY |
407 | }; |
| 408 | }; | |
| 409 | ||
| 5740ea4e | 410 | #include "uniphier-pinctrl.dtsi" |