[mirror_ubuntu-bionic-kernel.git] / arch / arm64 / boot / dts / socionext / uniphier-ld20.dtsi

/*
 * Device Tree Source for UniPhier LD20 SoC
 *
 * Copyright (C) 2015-2016 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 */

/memreserve/ 0x80000000 0x02000000;

/ {
	compatible = "socionext,uniphier-ld20";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&cpu2>;
				};
				core1 {
					cpu = <&cpu3>;
				};
			};
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0 0x000>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			operating-points-v2 = <&cluster0_opp>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0 0x001>;
			clocks = <&sys_clk 32>;
			enable-method = "psci";
			operating-points-v2 = <&cluster0_opp>;
		};

		cpu2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0 0x100>;
			clocks = <&sys_clk 33>;
			enable-method = "psci";
			operating-points-v2 = <&cluster1_opp>;
		};

		cpu3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0 0x101>;
			clocks = <&sys_clk 33>;
			enable-method = "psci";
			operating-points-v2 = <&cluster1_opp>;
		};
	};

	cluster0_opp: opp_table0 {
		compatible = "operating-points-v2";
		opp-shared;

		opp-250000000 {
			opp-hz = /bits/ 64 <250000000>;
			clock-latency-ns = <300>;
		};
		opp-275000000 {
			opp-hz = /bits/ 64 <275000000>;
			clock-latency-ns = <300>;
		};
		opp-500000000 {
			opp-hz = /bits/ 64 <500000000>;
			clock-latency-ns = <300>;
		};
		opp-550000000 {
			opp-hz = /bits/ 64 <550000000>;
			clock-latency-ns = <300>;
		};
		opp-666667000 {
			opp-hz = /bits/ 64 <666667000>;
			clock-latency-ns = <300>;
		};
		opp-733334000 {
			opp-hz = /bits/ 64 <733334000>;
			clock-latency-ns = <300>;
		};
		opp-1000000000 {
			opp-hz = /bits/ 64 <1000000000>;
			clock-latency-ns = <300>;
		};
		opp-1100000000 {
			opp-hz = /bits/ 64 <1100000000>;
			clock-latency-ns = <300>;
		};
	};

	cluster1_opp: opp_table1 {
		compatible = "operating-points-v2";
		opp-shared;

		opp-250000000 {
			opp-hz = /bits/ 64 <250000000>;
			clock-latency-ns = <300>;
		};
		opp-275000000 {
			opp-hz = /bits/ 64 <275000000>;
			clock-latency-ns = <300>;
		};
		opp-500000000 {
			opp-hz = /bits/ 64 <500000000>;
			clock-latency-ns = <300>;
		};
		opp-550000000 {
			opp-hz = /bits/ 64 <550000000>;
			clock-latency-ns = <300>;
		};
		opp-666667000 {
			opp-hz = /bits/ 64 <666667000>;
			clock-latency-ns = <300>;
		};
		opp-733334000 {
			opp-hz = /bits/ 64 <733334000>;
			clock-latency-ns = <300>;
		};
		opp-1000000000 {
			opp-hz = /bits/ 64 <1000000000>;
			clock-latency-ns = <300>;
		};
		opp-1100000000 {
			opp-hz = /bits/ 64 <1100000000>;
			clock-latency-ns = <300>;
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	clocks {
		refclk: ref {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <1 13 4>,
			     <1 14 4>,
			     <1 11 4>,
			     <1 10 4>;
	};

	soc@0 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0xffffffff>;

		serial0: serial@54006800 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006800 0x40>;
			interrupts = <0 33 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart0>;
			clocks = <&peri_clk 0>;
		};

		serial1: serial@54006900 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006900 0x40>;
			interrupts = <0 35 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart1>;
			clocks = <&peri_clk 1>;
		};

		serial2: serial@54006a00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006a00 0x40>;
			interrupts = <0 37 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart2>;
			clocks = <&peri_clk 2>;
		};

		serial3: serial@54006b00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006b00 0x40>;
			interrupts = <0 177 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_uart3>;
			clocks = <&peri_clk 3>;
		};

		i2c0: i2c@58780000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58780000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 41 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c0>;
			clocks = <&peri_clk 4>;
			clock-frequency = <100000>;
		};

		i2c1: i2c@58781000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58781000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 42 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c1>;
			clocks = <&peri_clk 5>;
			clock-frequency = <100000>;
		};

		i2c2: i2c@58782000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58782000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 43 4>;
			clocks = <&peri_clk 6>;
			clock-frequency = <400000>;
		};

		i2c3: i2c@58783000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58783000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 44 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c3>;
			clocks = <&peri_clk 7>;
			clock-frequency = <100000>;
		};

		i2c4: i2c@58784000 {
			compatible = "socionext,uniphier-fi2c";
			status = "disabled";
			reg = <0x58784000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 45 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_i2c4>;
			clocks = <&peri_clk 8>;
			clock-frequency = <100000>;
		};

		i2c5: i2c@58785000 {
			compatible = "socionext,uniphier-fi2c";
			reg = <0x58785000 0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 25 4>;
			clocks = <&peri_clk 9>;
			clock-frequency = <400000>;
		};

		system_bus: system-bus@58c00000 {
			compatible = "socionext,uniphier-system-bus";
			status = "disabled";
			reg = <0x58c00000 0x400>;
			#address-cells = <2>;
			#size-cells = <1>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_system_bus>;
		};

		smpctrl@59801000 {
			compatible = "socionext,uniphier-smpctrl";
			reg = <0x59801000 0x400>;
		};

		sdctrl@59810000 {
			compatible = "socionext,uniphier-ld20-sdctrl",
				     "simple-mfd", "syscon";
			reg = <0x59810000 0x800>;

			sd_clk: clock {
				compatible = "socionext,uniphier-ld20-sd-clock";
				#clock-cells = <1>;
			};

			sd_rst: reset {
				compatible = "socionext,uniphier-ld20-sd-reset";
				#reset-cells = <1>;
			};
		};

		perictrl@59820000 {
			compatible = "socionext,uniphier-ld20-perictrl",
				     "simple-mfd", "syscon";
			reg = <0x59820000 0x200>;

			peri_clk: clock {
				compatible = "socionext,uniphier-ld20-peri-clock";
				#clock-cells = <1>;
			};

			peri_rst: reset {
				compatible = "socionext,uniphier-ld20-peri-reset";
				#reset-cells = <1>;
			};
		};

		emmc: sdhc@5a000000 {
			compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
			reg = <0x5a000000 0x400>;
			interrupts = <0 78 4>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_emmc>;
			clocks = <&sys_clk 4>;
			bus-width = <8>;
			mmc-ddr-1_8v;
			mmc-hs200-1_8v;
			cdns,phy-input-delay-legacy = <4>;
			cdns,phy-input-delay-mmc-highspeed = <2>;
			cdns,phy-input-delay-mmc-ddr = <3>;
			cdns,phy-dll-delay-sdclk = <21>;
			cdns,phy-dll-delay-sdclk-hsmmc = <21>;
		};

		soc-glue@5f800000 {
			compatible = "socionext,uniphier-ld20-soc-glue",
				     "simple-mfd", "syscon";
			reg = <0x5f800000 0x2000>;

			pinctrl: pinctrl {
				compatible = "socionext,uniphier-ld20-pinctrl";
			};
		};

		gic: interrupt-controller@5fe00000 {
			compatible = "arm,gic-v3";
			reg = <0x5fe00000 0x10000>,	/* GICD */
			      <0x5fe80000 0x80000>;	/* GICR */
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <1 9 4>;
		};

		sysctrl@61840000 {
			compatible = "socionext,uniphier-ld20-sysctrl",
				     "simple-mfd", "syscon";
			reg = <0x61840000 0x10000>;

			sys_clk: clock {
				compatible = "socionext,uniphier-ld20-clock";
				#clock-cells = <1>;
			};

			sys_rst: reset {
				compatible = "socionext,uniphier-ld20-reset";
				#reset-cells = <1>;
			};
		};
	};
};

/include/ "uniphier-pinctrl.dtsi"
Commit	Line	Data
e1a0ebc8	1	/*
cea59bd0	2	* Device Tree Source for UniPhier LD20 SoC
e1a0ebc8	3	*
cea59bd0 MY	4	* Copyright (C) 2015-2016 Socionext Inc.
cea59bd0 MY	5	* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
e1a0ebc8	6	*
12301cff	7	* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
e1a0ebc8 MY	8	*/
e1a0ebc8 MY	9
79d4be39	10	/memreserve/ 0x80000000 0x02000000;
ffd8a5ed	11
e1a0ebc8	12	/ {
cea59bd0	13	compatible = "socionext,uniphier-ld20";
e1a0ebc8 MY	14	#address-cells = <2>;
	15	#size-cells = <2>;
	16	interrupt-parent = <&gic>;
	17
	18	cpus {
	19	#address-cells = <2>;
	20	#size-cells = <0>;
	21
	22	cpu-map {
	23	cluster0 {
	24	core0 {
	25	cpu = <&cpu0>;
	26	};
	27	core1 {
	28	cpu = <&cpu1>;
	29	};
	30	};
	31
	32	cluster1 {
	33	core0 {
	34	cpu = <&cpu2>;
	35	};
	36	core1 {
	37	cpu = <&cpu3>;
	38	};
	39	};
	40	};
	41
	42	cpu0: cpu@0 {
	43	device_type = "cpu";
	44	compatible = "arm,cortex-a72", "arm,armv8";
	45	reg = <0 0x000>;
183ad366	46	clocks = <&sys_clk 32>;
2f81137f	47	enable-method = "psci";
183ad366	48	operating-points-v2 = <&cluster0_opp>;
e1a0ebc8 MY	49	};
	50
	51	cpu1: cpu@1 {
	52	device_type = "cpu";
	53	compatible = "arm,cortex-a72", "arm,armv8";
	54	reg = <0 0x001>;
183ad366	55	clocks = <&sys_clk 32>;
2f81137f	56	enable-method = "psci";
183ad366	57	operating-points-v2 = <&cluster0_opp>;
e1a0ebc8 MY	58	};
	59
	60	cpu2: cpu@100 {
	61	device_type = "cpu";
	62	compatible = "arm,cortex-a53", "arm,armv8";
	63	reg = <0 0x100>;
183ad366	64	clocks = <&sys_clk 33>;
2f81137f	65	enable-method = "psci";
183ad366	66	operating-points-v2 = <&cluster1_opp>;
e1a0ebc8 MY	67	};
	68
	69	cpu3: cpu@101 {
	70	device_type = "cpu";
	71	compatible = "arm,cortex-a53", "arm,armv8";
	72	reg = <0 0x101>;
183ad366	73	clocks = <&sys_clk 33>;
2f81137f	74	enable-method = "psci";
183ad366 MY	75	operating-points-v2 = <&cluster1_opp>;
	76	};
	77	};
	78
	79	cluster0_opp: opp_table0 {
	80	compatible = "operating-points-v2";
	81	opp-shared;
	82
3fc9a121	83	opp-250000000 {
183ad366 MY	84	opp-hz = /bits/ 64 <250000000>;
	85	clock-latency-ns = <300>;
	86	};
3fc9a121	87	opp-275000000 {
183ad366 MY	88	opp-hz = /bits/ 64 <275000000>;
	89	clock-latency-ns = <300>;
	90	};
3fc9a121	91	opp-500000000 {
183ad366 MY	92	opp-hz = /bits/ 64 <500000000>;
	93	clock-latency-ns = <300>;
	94	};
3fc9a121	95	opp-550000000 {
183ad366 MY	96	opp-hz = /bits/ 64 <550000000>;
	97	clock-latency-ns = <300>;
	98	};
3fc9a121	99	opp-666667000 {
183ad366 MY	100	opp-hz = /bits/ 64 <666667000>;
	101	clock-latency-ns = <300>;
	102	};
3fc9a121	103	opp-733334000 {
183ad366 MY	104	opp-hz = /bits/ 64 <733334000>;
	105	clock-latency-ns = <300>;
	106	};
3fc9a121	107	opp-1000000000 {
183ad366 MY	108	opp-hz = /bits/ 64 <1000000000>;
	109	clock-latency-ns = <300>;
	110	};
3fc9a121	111	opp-1100000000 {
183ad366 MY	112	opp-hz = /bits/ 64 <1100000000>;
	113	clock-latency-ns = <300>;
	114	};
	115	};
	116
	117	cluster1_opp: opp_table1 {
	118	compatible = "operating-points-v2";
	119	opp-shared;
	120
3fc9a121	121	opp-250000000 {
183ad366 MY	122	opp-hz = /bits/ 64 <250000000>;
	123	clock-latency-ns = <300>;
	124	};
3fc9a121	125	opp-275000000 {
183ad366 MY	126	opp-hz = /bits/ 64 <275000000>;
	127	clock-latency-ns = <300>;
	128	};
3fc9a121	129	opp-500000000 {
183ad366 MY	130	opp-hz = /bits/ 64 <500000000>;
	131	clock-latency-ns = <300>;
	132	};
3fc9a121	133	opp-550000000 {
183ad366 MY	134	opp-hz = /bits/ 64 <550000000>;
	135	clock-latency-ns = <300>;
	136	};
3fc9a121	137	opp-666667000 {
183ad366 MY	138	opp-hz = /bits/ 64 <666667000>;
	139	clock-latency-ns = <300>;
	140	};
3fc9a121	141	opp-733334000 {
183ad366 MY	142	opp-hz = /bits/ 64 <733334000>;
	143	clock-latency-ns = <300>;
	144	};
3fc9a121	145	opp-1000000000 {
183ad366 MY	146	opp-hz = /bits/ 64 <1000000000>;
	147	clock-latency-ns = <300>;
	148	};
3fc9a121	149	opp-1100000000 {
183ad366 MY	150	opp-hz = /bits/ 64 <1100000000>;
183ad366 MY	151	clock-latency-ns = <300>;
e1a0ebc8 MY	152	};
	153	};
	154
2f81137f MY	155	psci {
	156	compatible = "arm,psci-1.0";
	157	method = "smc";
	158	};
	159
e1a0ebc8	160	clocks {
fb89cf36 MY	161	refclk: ref {
	162	compatible = "fixed-clock";
	163	#clock-cells = <0>;
	164	clock-frequency = <25000000>;
	165	};
e1a0ebc8 MY	166	};
	167
	168	timer {
	169	compatible = "arm,armv8-timer";
f2a89d3b MZ	170	interrupts = <1 13 4>,
	171	<1 14 4>,
	172	<1 11 4>,
	173	<1 10 4>;
e1a0ebc8 MY	174	};
e1a0ebc8 MY	175
b5027603	176	soc@0 {
e1a0ebc8 MY	177	compatible = "simple-bus";
	178	#address-cells = <1>;
	179	#size-cells = <1>;
	180	ranges = <0 0 0 0xffffffff>;
	181
e1a0ebc8 MY	182	serial0: serial@54006800 {
	183	compatible = "socionext,uniphier-uart";
	184	status = "disabled";
	185	reg = <0x54006800 0x40>;
	186	interrupts = <0 33 4>;
	187	pinctrl-names = "default";
	188	pinctrl-0 = <&pinctrl_uart0>;
42aee275	189	clocks = <&peri_clk 0>;
e1a0ebc8 MY	190	};
	191
	192	serial1: serial@54006900 {
	193	compatible = "socionext,uniphier-uart";
	194	status = "disabled";
	195	reg = <0x54006900 0x40>;
	196	interrupts = <0 35 4>;
	197	pinctrl-names = "default";
	198	pinctrl-0 = <&pinctrl_uart1>;
42aee275	199	clocks = <&peri_clk 1>;
e1a0ebc8 MY	200	};
	201
	202	serial2: serial@54006a00 {
	203	compatible = "socionext,uniphier-uart";
	204	status = "disabled";
	205	reg = <0x54006a00 0x40>;
	206	interrupts = <0 37 4>;
	207	pinctrl-names = "default";
	208	pinctrl-0 = <&pinctrl_uart2>;
42aee275	209	clocks = <&peri_clk 2>;
e1a0ebc8 MY	210	};
	211
	212	serial3: serial@54006b00 {
	213	compatible = "socionext,uniphier-uart";
	214	status = "disabled";
	215	reg = <0x54006b00 0x40>;
	216	interrupts = <0 177 4>;
	217	pinctrl-names = "default";
	218	pinctrl-0 = <&pinctrl_uart3>;
42aee275	219	clocks = <&peri_clk 3>;
e1a0ebc8 MY	220	};
	221
	222	i2c0: i2c@58780000 {
	223	compatible = "socionext,uniphier-fi2c";
	224	status = "disabled";
	225	reg = <0x58780000 0x80>;
	226	#address-cells = <1>;
	227	#size-cells = <0>;
	228	interrupts = <0 41 4>;
	229	pinctrl-names = "default";
	230	pinctrl-0 = <&pinctrl_i2c0>;
42aee275	231	clocks = <&peri_clk 4>;
e1a0ebc8 MY	232	clock-frequency = <100000>;
	233	};
	234
	235	i2c1: i2c@58781000 {
	236	compatible = "socionext,uniphier-fi2c";
	237	status = "disabled";
	238	reg = <0x58781000 0x80>;
	239	#address-cells = <1>;
	240	#size-cells = <0>;
	241	interrupts = <0 42 4>;
	242	pinctrl-names = "default";
	243	pinctrl-0 = <&pinctrl_i2c1>;
42aee275	244	clocks = <&peri_clk 5>;
e1a0ebc8 MY	245	clock-frequency = <100000>;
	246	};
	247
	248	i2c2: i2c@58782000 {
	249	compatible = "socionext,uniphier-fi2c";
e1a0ebc8 MY	250	reg = <0x58782000 0x80>;
	251	#address-cells = <1>;
	252	#size-cells = <0>;
	253	interrupts = <0 43 4>;
42aee275	254	clocks = <&peri_clk 6>;
56896ef5	255	clock-frequency = <400000>;
e1a0ebc8 MY	256	};
	257
	258	i2c3: i2c@58783000 {
	259	compatible = "socionext,uniphier-fi2c";
	260	status = "disabled";
	261	reg = <0x58783000 0x80>;
	262	#address-cells = <1>;
	263	#size-cells = <0>;
	264	interrupts = <0 44 4>;
	265	pinctrl-names = "default";
	266	pinctrl-0 = <&pinctrl_i2c3>;
42aee275	267	clocks = <&peri_clk 7>;
e1a0ebc8 MY	268	clock-frequency = <100000>;
	269	};
	270
	271	i2c4: i2c@58784000 {
	272	compatible = "socionext,uniphier-fi2c";
56896ef5	273	status = "disabled";
e1a0ebc8 MY	274	reg = <0x58784000 0x80>;
	275	#address-cells = <1>;
	276	#size-cells = <0>;
	277	interrupts = <0 45 4>;
56896ef5 MY	278	pinctrl-names = "default";
56896ef5 MY	279	pinctrl-0 = <&pinctrl_i2c4>;
42aee275	280	clocks = <&peri_clk 8>;
56896ef5	281	clock-frequency = <100000>;
e1a0ebc8 MY	282	};
	283
	284	i2c5: i2c@58785000 {
	285	compatible = "socionext,uniphier-fi2c";
	286	reg = <0x58785000 0x80>;
	287	#address-cells = <1>;
	288	#size-cells = <0>;
	289	interrupts = <0 25 4>;
42aee275	290	clocks = <&peri_clk 9>;
e1a0ebc8 MY	291	clock-frequency = <400000>;
	292	};
	293
14bae133 MY	294	system_bus: system-bus@58c00000 {
	295	compatible = "socionext,uniphier-system-bus";
	296	status = "disabled";
	297	reg = <0x58c00000 0x400>;
	298	#address-cells = <2>;
	299	#size-cells = <1>;
5d9a83c9 MY	300	pinctrl-names = "default";
5d9a83c9 MY	301	pinctrl-0 = <&pinctrl_system_bus>;
14bae133 MY	302	};
14bae133 MY	303
b10ee7e3	304	smpctrl@59801000 {
14bae133 MY	305	compatible = "socionext,uniphier-smpctrl";
	306	reg = <0x59801000 0x400>;
	307	};
	308
8e68c65d MY	309	sdctrl@59810000 {
8e68c65d MY	310	compatible = "socionext,uniphier-ld20-sdctrl",
42aee275 MY	311	"simple-mfd", "syscon";
	312	reg = <0x59810000 0x800>;
	313
8e68c65d MY	314	sd_clk: clock {
8e68c65d MY	315	compatible = "socionext,uniphier-ld20-sd-clock";
42aee275 MY	316	#clock-cells = <1>;
	317	};
	318
8e68c65d MY	319	sd_rst: reset {
8e68c65d MY	320	compatible = "socionext,uniphier-ld20-sd-reset";
42aee275 MY	321	#reset-cells = <1>;
	322	};
	323	};
	324
	325	perictrl@59820000 {
fb28cef0	326	compatible = "socionext,uniphier-ld20-perictrl",
42aee275 MY	327	"simple-mfd", "syscon";
	328	reg = <0x59820000 0x200>;
	329
	330	peri_clk: clock {
	331	compatible = "socionext,uniphier-ld20-peri-clock";
	332	#clock-cells = <1>;
	333	};
	334
	335	peri_rst: reset {
	336	compatible = "socionext,uniphier-ld20-peri-reset";
	337	#reset-cells = <1>;
	338	};
	339	};
	340
3a93cc26 MY	341	emmc: sdhc@5a000000 {
	342	compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
	343	reg = <0x5a000000 0x400>;
	344	interrupts = <0 78 4>;
9c0a9700 MY	345	pinctrl-names = "default";
9c0a9700 MY	346	pinctrl-0 = <&pinctrl_emmc>;
3a93cc26 MY	347	clocks = <&sys_clk 4>;
	348	bus-width = <8>;
	349	mmc-ddr-1_8v;
	350	mmc-hs200-1_8v;
ba6f7011 MY	351	cdns,phy-input-delay-legacy = <4>;
	352	cdns,phy-input-delay-mmc-highspeed = <2>;
	353	cdns,phy-input-delay-mmc-ddr = <3>;
e345eded MY	354	cdns,phy-dll-delay-sdclk = <21>;
e345eded MY	355	cdns,phy-dll-delay-sdclk-hsmmc = <21>;
3a93cc26 MY	356	};
3a93cc26 MY	357
ed6cca5f	358	soc-glue@5f800000 {
fb28cef0	359	compatible = "socionext,uniphier-ld20-soc-glue",
9d4f5505	360	"simple-mfd", "syscon";
ed6cca5f MY	361	reg = <0x5f800000 0x2000>;
	362
	363	pinctrl: pinctrl {
cea59bd0	364	compatible = "socionext,uniphier-ld20-pinctrl";
ed6cca5f	365	};
e1a0ebc8 MY	366	};
	367
	368	gic: interrupt-controller@5fe00000 {
	369	compatible = "arm,gic-v3";
	370	reg = <0x5fe00000 0x10000>, /* GICD */
	371	<0x5fe80000 0x80000>; /* GICR */
	372	interrupt-controller;
	373	#interrupt-cells = <3>;
	374	interrupts = <1 9 4>;
	375	};
42aee275 MY	376
42aee275 MY	377	sysctrl@61840000 {
fb28cef0	378	compatible = "socionext,uniphier-ld20-sysctrl",
42aee275	379	"simple-mfd", "syscon";
1ef64af8	380	reg = <0x61840000 0x10000>;
42aee275 MY	381
	382	sys_clk: clock {
	383	compatible = "socionext,uniphier-ld20-clock";
	384	#clock-cells = <1>;
	385	};
	386
	387	sys_rst: reset {
	388	compatible = "socionext,uniphier-ld20-reset";
	389	#reset-cells = <1>;
	390	};
	391	};
e1a0ebc8 MY	392	};
	393	};
	394
	395	/include/ "uniphier-pinctrl.dtsi"