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9243d4d3 MS |
1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* | |
3 | * dts file for Xilinx ZynqMP ZCU106 | |
4 | * | |
5 | * (C) Copyright 2016, Xilinx, Inc. | |
6 | * | |
7 | * Michal Simek <michal.simek@xilinx.com> | |
8 | */ | |
9 | ||
10 | /dts-v1/; | |
11 | ||
12 | #include "zynqmp.dtsi" | |
13 | #include "zynqmp-clk.dtsi" | |
14 | #include <dt-bindings/input/input.h> | |
15 | #include <dt-bindings/gpio/gpio.h> | |
16 | ||
17 | / { | |
18 | model = "ZynqMP ZCU106 RevA"; | |
19 | compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp"; | |
20 | ||
21 | aliases { | |
22 | ethernet0 = &gem3; | |
23 | i2c0 = &i2c0; | |
24 | i2c1 = &i2c1; | |
25 | mmc0 = &sdhci1; | |
26 | rtc0 = &rtc; | |
27 | serial0 = &uart0; | |
28 | serial1 = &uart1; | |
29 | serial2 = &dcc; | |
30 | }; | |
31 | ||
32 | chosen { | |
33 | bootargs = "earlycon"; | |
34 | stdout-path = "serial0:115200n8"; | |
35 | }; | |
36 | ||
37 | memory@0 { | |
38 | device_type = "memory"; | |
39 | reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; | |
40 | }; | |
41 | ||
42 | gpio-keys { | |
43 | compatible = "gpio-keys"; | |
9243d4d3 MS |
44 | autorepeat; |
45 | sw19 { | |
46 | label = "sw19"; | |
47 | gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; | |
48 | linux,code = <KEY_DOWN>; | |
1696acf4 | 49 | wakeup-source; |
9243d4d3 MS |
50 | autorepeat; |
51 | }; | |
52 | }; | |
53 | ||
54 | leds { | |
55 | compatible = "gpio-leds"; | |
d1d4445a | 56 | heartbeat-led { |
9243d4d3 MS |
57 | label = "heartbeat"; |
58 | gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; | |
59 | linux,default-trigger = "heartbeat"; | |
60 | }; | |
61 | }; | |
62 | }; | |
63 | ||
64 | &can1 { | |
65 | status = "okay"; | |
66 | }; | |
67 | ||
68 | &dcc { | |
69 | status = "okay"; | |
70 | }; | |
71 | ||
72 | /* fpd_dma clk 667MHz, lpd_dma 500MHz */ | |
73 | &fpd_dma_chan1 { | |
74 | status = "okay"; | |
75 | }; | |
76 | ||
77 | &fpd_dma_chan2 { | |
78 | status = "okay"; | |
79 | }; | |
80 | ||
81 | &fpd_dma_chan3 { | |
82 | status = "okay"; | |
83 | }; | |
84 | ||
85 | &fpd_dma_chan4 { | |
86 | status = "okay"; | |
87 | }; | |
88 | ||
89 | &fpd_dma_chan5 { | |
90 | status = "okay"; | |
91 | }; | |
92 | ||
93 | &fpd_dma_chan6 { | |
94 | status = "okay"; | |
95 | }; | |
96 | ||
97 | &fpd_dma_chan7 { | |
98 | status = "okay"; | |
99 | }; | |
100 | ||
101 | &fpd_dma_chan8 { | |
102 | status = "okay"; | |
103 | }; | |
104 | ||
105 | &gem3 { | |
106 | status = "okay"; | |
107 | phy-handle = <&phy0>; | |
108 | phy-mode = "rgmii-id"; | |
109 | phy0: phy@c { | |
110 | reg = <0xc>; | |
111 | ti,rx-internal-delay = <0x8>; | |
112 | ti,tx-internal-delay = <0xa>; | |
113 | ti,fifo-depth = <0x1>; | |
78c484a5 | 114 | ti,dp83867-rxctrl-strap-quirk; |
9243d4d3 MS |
115 | }; |
116 | }; | |
117 | ||
118 | &gpio { | |
119 | status = "okay"; | |
120 | }; | |
121 | ||
122 | &i2c0 { | |
123 | status = "okay"; | |
124 | clock-frequency = <400000>; | |
125 | ||
126 | tca6416_u97: gpio@20 { | |
127 | compatible = "ti,tca6416"; | |
128 | reg = <0x20>; | |
129 | gpio-controller; /* interrupt not connected */ | |
130 | #gpio-cells = <2>; | |
131 | /* | |
132 | * IRQ not connected | |
133 | * Lines: | |
134 | * 0 - SFP_SI5328_INT_ALM | |
135 | * 1 - HDMI_SI5328_INT_ALM | |
136 | * 5 - IIC_MUX_RESET_B | |
137 | * 6 - GEM3_EXP_RESET_B | |
138 | * 10 - FMC_HPC0_PRSNT_M2C_B | |
139 | * 11 - FMC_HPC1_PRSNT_M2C_B | |
140 | * 2-4, 7, 12-17 - not connected | |
141 | */ | |
142 | }; | |
143 | ||
144 | tca6416_u61: gpio@21 { | |
145 | compatible = "ti,tca6416"; | |
146 | reg = <0x21>; | |
147 | gpio-controller; | |
148 | #gpio-cells = <2>; | |
149 | /* | |
150 | * IRQ not connected | |
151 | * Lines: | |
152 | * 0 - VCCPSPLL_EN | |
153 | * 1 - MGTRAVCC_EN | |
154 | * 2 - MGTRAVTT_EN | |
155 | * 3 - VCCPSDDRPLL_EN | |
156 | * 4 - MIO26_PMU_INPUT_LS | |
157 | * 5 - PL_PMBUS_ALERT | |
158 | * 6 - PS_PMBUS_ALERT | |
159 | * 7 - MAXIM_PMBUS_ALERT | |
160 | * 10 - PL_DDR4_VTERM_EN | |
161 | * 11 - PL_DDR4_VPP_2V5_EN | |
162 | * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON | |
163 | * 13 - PS_DIMM_SUSPEND_EN | |
164 | * 14 - PS_DDR4_VTERM_EN | |
165 | * 15 - PS_DDR4_VPP_2V5_EN | |
166 | * 16 - 17 - not connected | |
167 | */ | |
168 | }; | |
169 | ||
170 | i2c-mux@75 { /* u60 */ | |
171 | compatible = "nxp,pca9544"; | |
172 | #address-cells = <1>; | |
173 | #size-cells = <0>; | |
174 | reg = <0x75>; | |
175 | i2c@0 { | |
176 | #address-cells = <1>; | |
177 | #size-cells = <0>; | |
178 | reg = <0>; | |
179 | /* PS_PMBUS */ | |
180 | ina226@40 { /* u76 */ | |
181 | compatible = "ti,ina226"; | |
182 | reg = <0x40>; | |
183 | shunt-resistor = <5000>; | |
184 | }; | |
185 | ina226@41 { /* u77 */ | |
186 | compatible = "ti,ina226"; | |
187 | reg = <0x41>; | |
188 | shunt-resistor = <5000>; | |
189 | }; | |
190 | ina226@42 { /* u78 */ | |
191 | compatible = "ti,ina226"; | |
192 | reg = <0x42>; | |
193 | shunt-resistor = <5000>; | |
194 | }; | |
195 | ina226@43 { /* u87 */ | |
196 | compatible = "ti,ina226"; | |
197 | reg = <0x43>; | |
198 | shunt-resistor = <5000>; | |
199 | }; | |
200 | ina226@44 { /* u85 */ | |
201 | compatible = "ti,ina226"; | |
202 | reg = <0x44>; | |
203 | shunt-resistor = <5000>; | |
204 | }; | |
205 | ina226@45 { /* u86 */ | |
206 | compatible = "ti,ina226"; | |
207 | reg = <0x45>; | |
208 | shunt-resistor = <5000>; | |
209 | }; | |
210 | ina226@46 { /* u93 */ | |
211 | compatible = "ti,ina226"; | |
212 | reg = <0x46>; | |
213 | shunt-resistor = <5000>; | |
214 | }; | |
215 | ina226@47 { /* u88 */ | |
216 | compatible = "ti,ina226"; | |
217 | reg = <0x47>; | |
218 | shunt-resistor = <5000>; | |
219 | }; | |
220 | ina226@4a { /* u15 */ | |
221 | compatible = "ti,ina226"; | |
222 | reg = <0x4a>; | |
223 | shunt-resistor = <5000>; | |
224 | }; | |
225 | ina226@4b { /* u92 */ | |
226 | compatible = "ti,ina226"; | |
227 | reg = <0x4b>; | |
228 | shunt-resistor = <5000>; | |
229 | }; | |
230 | }; | |
231 | i2c@1 { | |
232 | #address-cells = <1>; | |
233 | #size-cells = <0>; | |
234 | reg = <1>; | |
235 | /* PL_PMBUS */ | |
236 | ina226@40 { /* u79 */ | |
237 | compatible = "ti,ina226"; | |
238 | reg = <0x40>; | |
239 | shunt-resistor = <2000>; | |
240 | }; | |
241 | ina226@41 { /* u81 */ | |
242 | compatible = "ti,ina226"; | |
243 | reg = <0x41>; | |
244 | shunt-resistor = <5000>; | |
245 | }; | |
246 | ina226@42 { /* u80 */ | |
247 | compatible = "ti,ina226"; | |
248 | reg = <0x42>; | |
249 | shunt-resistor = <5000>; | |
250 | }; | |
251 | ina226@43 { /* u84 */ | |
252 | compatible = "ti,ina226"; | |
253 | reg = <0x43>; | |
254 | shunt-resistor = <5000>; | |
255 | }; | |
256 | ina226@44 { /* u16 */ | |
257 | compatible = "ti,ina226"; | |
258 | reg = <0x44>; | |
259 | shunt-resistor = <5000>; | |
260 | }; | |
261 | ina226@45 { /* u65 */ | |
262 | compatible = "ti,ina226"; | |
263 | reg = <0x45>; | |
264 | shunt-resistor = <5000>; | |
265 | }; | |
266 | ina226@46 { /* u74 */ | |
267 | compatible = "ti,ina226"; | |
268 | reg = <0x46>; | |
269 | shunt-resistor = <5000>; | |
270 | }; | |
271 | ina226@47 { /* u75 */ | |
272 | compatible = "ti,ina226"; | |
273 | reg = <0x47>; | |
274 | shunt-resistor = <5000>; | |
275 | }; | |
276 | }; | |
277 | i2c@2 { | |
278 | #address-cells = <1>; | |
279 | #size-cells = <0>; | |
280 | reg = <2>; | |
281 | /* MAXIM_PMBUS - 00 */ | |
282 | max15301@a { /* u46 */ | |
283 | compatible = "maxim,max15301"; | |
284 | reg = <0xa>; | |
285 | }; | |
286 | max15303@b { /* u4 */ | |
287 | compatible = "maxim,max15303"; | |
288 | reg = <0xb>; | |
289 | }; | |
290 | max15303@10 { /* u13 */ | |
291 | compatible = "maxim,max15303"; | |
292 | reg = <0x10>; | |
293 | }; | |
294 | max15301@13 { /* u47 */ | |
295 | compatible = "maxim,max15301"; | |
296 | reg = <0x13>; | |
297 | }; | |
298 | max15303@14 { /* u7 */ | |
299 | compatible = "maxim,max15303"; | |
300 | reg = <0x14>; | |
301 | }; | |
302 | max15303@15 { /* u6 */ | |
303 | compatible = "maxim,max15303"; | |
304 | reg = <0x15>; | |
305 | }; | |
306 | max15303@16 { /* u10 */ | |
307 | compatible = "maxim,max15303"; | |
308 | reg = <0x16>; | |
309 | }; | |
310 | max15303@17 { /* u9 */ | |
311 | compatible = "maxim,max15303"; | |
312 | reg = <0x17>; | |
313 | }; | |
314 | max15301@18 { /* u63 */ | |
315 | compatible = "maxim,max15301"; | |
316 | reg = <0x18>; | |
317 | }; | |
318 | max15303@1a { /* u49 */ | |
319 | compatible = "maxim,max15303"; | |
320 | reg = <0x1a>; | |
321 | }; | |
322 | max15303@1b { /* u8 */ | |
323 | compatible = "maxim,max15303"; | |
324 | reg = <0x1b>; | |
325 | }; | |
326 | max15303@1d { /* u18 */ | |
327 | compatible = "maxim,max15303"; | |
328 | reg = <0x1d>; | |
329 | }; | |
330 | ||
331 | max20751@72 { /* u95 */ | |
332 | compatible = "maxim,max20751"; | |
333 | reg = <0x72>; | |
334 | }; | |
335 | max20751@73 { /* u96 */ | |
336 | compatible = "maxim,max20751"; | |
337 | reg = <0x73>; | |
338 | }; | |
339 | }; | |
340 | /* Bus 3 is not connected */ | |
341 | }; | |
342 | }; | |
343 | ||
344 | &i2c1 { | |
345 | status = "okay"; | |
346 | clock-frequency = <400000>; | |
347 | ||
348 | /* PL i2c via PCA9306 - u45 */ | |
349 | i2c-mux@74 { /* u34 */ | |
350 | compatible = "nxp,pca9548"; | |
351 | #address-cells = <1>; | |
352 | #size-cells = <0>; | |
353 | reg = <0x74>; | |
354 | i2c@0 { | |
355 | #address-cells = <1>; | |
356 | #size-cells = <0>; | |
357 | reg = <0>; | |
358 | /* | |
359 | * IIC_EEPROM 1kB memory which uses 256B blocks | |
360 | * where every block has different address. | |
361 | * 0 - 256B address 0x54 | |
362 | * 256B - 512B address 0x55 | |
363 | * 512B - 768B address 0x56 | |
364 | * 768B - 1024B address 0x57 | |
365 | */ | |
366 | eeprom: eeprom@54 { /* u23 */ | |
367 | compatible = "atmel,24c08"; | |
368 | reg = <0x54>; | |
369 | }; | |
370 | }; | |
371 | i2c@1 { | |
372 | #address-cells = <1>; | |
373 | #size-cells = <0>; | |
374 | reg = <1>; | |
375 | si5341: clock-generator@36 { /* SI5341 - u69 */ | |
376 | reg = <0x36>; | |
377 | }; | |
378 | ||
379 | }; | |
380 | i2c@2 { | |
381 | #address-cells = <1>; | |
382 | #size-cells = <0>; | |
383 | reg = <2>; | |
384 | si570_1: clock-generator@5d { /* USER SI570 - u42 */ | |
385 | #clock-cells = <0>; | |
386 | compatible = "silabs,si570"; | |
387 | reg = <0x5d>; | |
388 | temperature-stability = <50>; | |
389 | factory-fout = <300000000>; | |
390 | clock-frequency = <300000000>; | |
391 | }; | |
392 | }; | |
393 | i2c@3 { | |
394 | #address-cells = <1>; | |
395 | #size-cells = <0>; | |
396 | reg = <3>; | |
397 | si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */ | |
398 | #clock-cells = <0>; | |
399 | compatible = "silabs,si570"; | |
400 | reg = <0x5d>; | |
401 | temperature-stability = <50>; /* copy from zc702 */ | |
402 | factory-fout = <156250000>; | |
403 | clock-frequency = <148500000>; | |
404 | }; | |
405 | }; | |
406 | i2c@4 { | |
407 | #address-cells = <1>; | |
408 | #size-cells = <0>; | |
409 | reg = <4>; | |
410 | si5328: clock-generator@69 {/* SI5328 - u20 */ | |
411 | reg = <0x69>; | |
412 | }; | |
413 | }; | |
414 | i2c@5 { | |
415 | #address-cells = <1>; | |
416 | #size-cells = <0>; | |
417 | reg = <5>; /* FAN controller */ | |
418 | temp@4c {/* lm96163 - u128 */ | |
419 | compatible = "national,lm96163"; | |
420 | reg = <0x4c>; | |
421 | }; | |
422 | }; | |
423 | /* 6 - 7 unconnected */ | |
424 | }; | |
425 | ||
426 | i2c-mux@75 { | |
427 | compatible = "nxp,pca9548"; /* u135 */ | |
428 | #address-cells = <1>; | |
429 | #size-cells = <0>; | |
430 | reg = <0x75>; | |
431 | ||
432 | i2c@0 { | |
433 | #address-cells = <1>; | |
434 | #size-cells = <0>; | |
435 | reg = <0>; | |
436 | /* HPC0_IIC */ | |
437 | }; | |
438 | i2c@1 { | |
439 | #address-cells = <1>; | |
440 | #size-cells = <0>; | |
441 | reg = <1>; | |
442 | /* HPC1_IIC */ | |
443 | }; | |
444 | i2c@2 { | |
445 | #address-cells = <1>; | |
446 | #size-cells = <0>; | |
447 | reg = <2>; | |
448 | /* SYSMON */ | |
449 | }; | |
450 | i2c@3 { | |
451 | #address-cells = <1>; | |
452 | #size-cells = <0>; | |
453 | reg = <3>; | |
454 | /* DDR4 SODIMM */ | |
455 | }; | |
456 | i2c@4 { | |
457 | #address-cells = <1>; | |
458 | #size-cells = <0>; | |
459 | reg = <4>; | |
460 | /* SEP 3 */ | |
461 | }; | |
462 | i2c@5 { | |
463 | #address-cells = <1>; | |
464 | #size-cells = <0>; | |
465 | reg = <5>; | |
466 | /* SEP 2 */ | |
467 | }; | |
468 | i2c@6 { | |
469 | #address-cells = <1>; | |
470 | #size-cells = <0>; | |
471 | reg = <6>; | |
472 | /* SEP 1 */ | |
473 | }; | |
474 | i2c@7 { | |
475 | #address-cells = <1>; | |
476 | #size-cells = <0>; | |
477 | reg = <7>; | |
478 | /* SEP 0 */ | |
479 | }; | |
480 | }; | |
481 | }; | |
482 | ||
483 | &rtc { | |
484 | status = "okay"; | |
485 | }; | |
486 | ||
487 | &sata { | |
488 | status = "okay"; | |
489 | /* SATA OOB timing settings */ | |
490 | ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; | |
491 | ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; | |
492 | ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; | |
493 | ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; | |
494 | ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; | |
495 | ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; | |
496 | ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; | |
497 | ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; | |
498 | }; | |
499 | ||
500 | /* SD1 with level shifter */ | |
501 | &sdhci1 { | |
502 | status = "okay"; | |
503 | no-1-8-v; | |
504 | }; | |
505 | ||
506 | &uart0 { | |
507 | status = "okay"; | |
508 | }; | |
509 | ||
510 | &uart1 { | |
511 | status = "okay"; | |
512 | }; | |
513 | ||
514 | /* ULPI SMSC USB3320 */ | |
515 | &usb0 { | |
516 | status = "okay"; | |
517 | }; | |
518 | ||
519 | &watchdog0 { | |
520 | status = "okay"; | |
521 | }; |