projects / mirror_ubuntu-zesty-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 7936e914 JPB |
1 | /* |
| 2 | * arch/arm64/include/asm/arch_gicv3.h | |
| 3 | * | |
| 4 | * Copyright (C) 2015 ARM Ltd. | |
| 5 | * | |
| 6 | * This program is free software: you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License version 2 as | |
| 8 | * published by the Free Software Foundation. | |
| 9 | * | |
| 10 | * This program is distributed in the hope that it will be useful, | |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | * GNU General Public License for more details. | |
| 14 | * | |
| 15 | * You should have received a copy of the GNU General Public License | |
| 16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
| 17 | */ | |
| 18 | #ifndef __ASM_ARCH_GICV3_H | |
| 19 | #define __ASM_ARCH_GICV3_H | |
| 20 | ||
| 21 | #include <asm/sysreg.h> | |
| 22 | ||
| 23 | #define ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) | |
| 24 | #define ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1) | |
| 25 | #define ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) | |
| 26 | #define ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) | |
| 27 | #define ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) | |
| 28 | #define ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) | |
| 29 | #define ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) | |
| 30 | #define ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) | |
| 31 | ||
| 32 | #define ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) | |
| 33 | ||
| 34 | /* | |
| 35 | * System register definitions | |
| 36 | */ | |
| 37 | #define ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) | |
| 38 | #define ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0) | |
| 39 | #define ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1) | |
| 40 | #define ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2) | |
| 41 | #define ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) | |
| 42 | #define ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5) | |
| 43 | #define ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) | |
| 44 | ||
| 45 | #define __LR0_EL2(x) sys_reg(3, 4, 12, 12, x) | |
| 46 | #define __LR8_EL2(x) sys_reg(3, 4, 12, 13, x) | |
| 47 | ||
| 48 | #define ICH_LR0_EL2 __LR0_EL2(0) | |
| 49 | #define ICH_LR1_EL2 __LR0_EL2(1) | |
| 50 | #define ICH_LR2_EL2 __LR0_EL2(2) | |
| 51 | #define ICH_LR3_EL2 __LR0_EL2(3) | |
| 52 | #define ICH_LR4_EL2 __LR0_EL2(4) | |
| 53 | #define ICH_LR5_EL2 __LR0_EL2(5) | |
| 54 | #define ICH_LR6_EL2 __LR0_EL2(6) | |
| 55 | #define ICH_LR7_EL2 __LR0_EL2(7) | |
| 56 | #define ICH_LR8_EL2 __LR8_EL2(0) | |
| 57 | #define ICH_LR9_EL2 __LR8_EL2(1) | |
| 58 | #define ICH_LR10_EL2 __LR8_EL2(2) | |
| 59 | #define ICH_LR11_EL2 __LR8_EL2(3) | |
| 60 | #define ICH_LR12_EL2 __LR8_EL2(4) | |
| 61 | #define ICH_LR13_EL2 __LR8_EL2(5) | |
| 62 | #define ICH_LR14_EL2 __LR8_EL2(6) | |
| 63 | #define ICH_LR15_EL2 __LR8_EL2(7) | |
| 64 | ||
| 65 | #define __AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) | |
| 66 | #define ICH_AP0R0_EL2 __AP0Rx_EL2(0) | |
| 67 | #define ICH_AP0R1_EL2 __AP0Rx_EL2(1) | |
| 68 | #define ICH_AP0R2_EL2 __AP0Rx_EL2(2) | |
| 69 | #define ICH_AP0R3_EL2 __AP0Rx_EL2(3) | |
| 70 | ||
| 71 | #define __AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x) | |
| 72 | #define ICH_AP1R0_EL2 __AP1Rx_EL2(0) | |
| 73 | #define ICH_AP1R1_EL2 __AP1Rx_EL2(1) | |
| 74 | #define ICH_AP1R2_EL2 __AP1Rx_EL2(2) | |
| 75 | #define ICH_AP1R3_EL2 __AP1Rx_EL2(3) | |
| 76 | ||
| 77 | #ifndef __ASSEMBLY__ | |
| 78 | ||
| 79 | #include <linux/stringify.h> | |
| 80 | ||
| 81 | /* Low level accessors */ | |
| 82 | ||
| 83 | static inline void gic_write_eoir(u64 irq) | |
| 84 | { | |
| 85 | asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" (irq)); | |
| 86 | isb(); | |
| 87 | } | |
| 88 | ||
| 89 | static inline void gic_write_dir(u64 irq) | |
| 90 | { | |
| 91 | asm volatile("msr_s " __stringify(ICC_DIR_EL1) ", %0" : : "r" (irq)); | |
| 92 | isb(); | |
| 93 | } | |
| 94 | ||
| 95 | static inline u64 gic_read_iar_common(void) | |
| 96 | { | |
| 97 | u64 irqstat; | |
| 98 | ||
| 99 | asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat)); | |
| 100 | return irqstat; | |
| 101 | } | |
| 102 | ||
| 103 | /* | |
| 104 | * Cavium ThunderX erratum 23154 | |
| 105 | * | |
| 106 | * The gicv3 of ThunderX requires a modified version for reading the | |
| 107 | * IAR status to ensure data synchronization (access to icc_iar1_el1 | |
| 108 | * is not sync'ed before and after). | |
| 109 | */ | |
| 110 | static inline u64 gic_read_iar_cavium_thunderx(void) | |
| 111 | { | |
| 112 | u64 irqstat; | |
| 113 | ||
| 114 | asm volatile( | |
| 115 | "nop;nop;nop;nop\n\t" | |
| 116 | "nop;nop;nop;nop\n\t" | |
| 117 | "mrs_s %0, " __stringify(ICC_IAR1_EL1) "\n\t" | |
| 118 | "nop;nop;nop;nop" | |
| 119 | : "=r" (irqstat)); | |
| 120 | mb(); | |
| 121 | ||
| 122 | return irqstat; | |
| 123 | } | |
| 124 | ||
| 125 | static inline void gic_write_pmr(u64 val) | |
| 126 | { | |
| 127 | asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val)); | |
| 128 | } | |
| 129 | ||
| 130 | static inline void gic_write_ctlr(u64 val) | |
| 131 | { | |
| 132 | asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val)); | |
| 133 | isb(); | |
| 134 | } | |
| 135 | ||
| 136 | static inline void gic_write_grpen1(u64 val) | |
| 137 | { | |
| 138 | asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val)); | |
| 139 | isb(); | |
| 140 | } | |
| 141 | ||
| 142 | static inline void gic_write_sgi1r(u64 val) | |
| 143 | { | |
| 144 | asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val)); | |
| 145 | } | |
| 146 | ||
| 147 | static inline u64 gic_read_sre(void) | |
| 148 | { | |
| 149 | u64 val; | |
| 150 | ||
| 151 | asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); | |
| 152 | return val; | |
| 153 | } | |
| 154 | ||
| 155 | static inline void gic_write_sre(u64 val) | |
| 156 | { | |
| 157 | asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val)); | |
| 158 | isb(); | |
| 159 | } | |
| 160 | ||
| 161 | #endif /* __ASSEMBLY__ */ | |
| 162 | #endif /* __ASM_ARCH_GICV3_H */ |