[mirror_ubuntu-zesty-kernel.git] / arch / arm64 / include / asm / arch_gicv3.h

/*
 * arch/arm64/include/asm/arch_gicv3.h
 *
 * Copyright (C) 2015 ARM Ltd.
 *
 * This program is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __ASM_ARCH_GICV3_H
#define __ASM_ARCH_GICV3_H

#include <asm/sysreg.h>

#define ICC_EOIR1_EL1			sys_reg(3, 0, 12, 12, 1)
#define ICC_DIR_EL1			sys_reg(3, 0, 12, 11, 1)
#define ICC_IAR1_EL1			sys_reg(3, 0, 12, 12, 0)
#define ICC_SGI1R_EL1			sys_reg(3, 0, 12, 11, 5)
#define ICC_PMR_EL1			sys_reg(3, 0, 4, 6, 0)
#define ICC_CTLR_EL1			sys_reg(3, 0, 12, 12, 4)
#define ICC_SRE_EL1			sys_reg(3, 0, 12, 12, 5)
#define ICC_GRPEN1_EL1			sys_reg(3, 0, 12, 12, 7)

#define ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)

/*
 * System register definitions
 */
#define ICH_VSEIR_EL2			sys_reg(3, 4, 12, 9, 4)
#define ICH_HCR_EL2			sys_reg(3, 4, 12, 11, 0)
#define ICH_VTR_EL2			sys_reg(3, 4, 12, 11, 1)
#define ICH_MISR_EL2			sys_reg(3, 4, 12, 11, 2)
#define ICH_EISR_EL2			sys_reg(3, 4, 12, 11, 3)
#define ICH_ELSR_EL2			sys_reg(3, 4, 12, 11, 5)
#define ICH_VMCR_EL2			sys_reg(3, 4, 12, 11, 7)

#define __LR0_EL2(x)			sys_reg(3, 4, 12, 12, x)
#define __LR8_EL2(x)			sys_reg(3, 4, 12, 13, x)

#define ICH_LR0_EL2			__LR0_EL2(0)
#define ICH_LR1_EL2			__LR0_EL2(1)
#define ICH_LR2_EL2			__LR0_EL2(2)
#define ICH_LR3_EL2			__LR0_EL2(3)
#define ICH_LR4_EL2			__LR0_EL2(4)
#define ICH_LR5_EL2			__LR0_EL2(5)
#define ICH_LR6_EL2			__LR0_EL2(6)
#define ICH_LR7_EL2			__LR0_EL2(7)
#define ICH_LR8_EL2			__LR8_EL2(0)
#define ICH_LR9_EL2			__LR8_EL2(1)
#define ICH_LR10_EL2			__LR8_EL2(2)
#define ICH_LR11_EL2			__LR8_EL2(3)
#define ICH_LR12_EL2			__LR8_EL2(4)
#define ICH_LR13_EL2			__LR8_EL2(5)
#define ICH_LR14_EL2			__LR8_EL2(6)
#define ICH_LR15_EL2			__LR8_EL2(7)

#define __AP0Rx_EL2(x)			sys_reg(3, 4, 12, 8, x)
#define ICH_AP0R0_EL2			__AP0Rx_EL2(0)
#define ICH_AP0R1_EL2			__AP0Rx_EL2(1)
#define ICH_AP0R2_EL2			__AP0Rx_EL2(2)
#define ICH_AP0R3_EL2			__AP0Rx_EL2(3)

#define __AP1Rx_EL2(x)			sys_reg(3, 4, 12, 9, x)
#define ICH_AP1R0_EL2			__AP1Rx_EL2(0)
#define ICH_AP1R1_EL2			__AP1Rx_EL2(1)
#define ICH_AP1R2_EL2			__AP1Rx_EL2(2)
#define ICH_AP1R3_EL2			__AP1Rx_EL2(3)

#ifndef __ASSEMBLY__

#include <linux/stringify.h>

/*
 * Low-level accessors
 *
 * These system registers are 32 bits, but we make sure that the compiler
 * sets the GP register's most significant bits to 0 with an explicit cast.
 */

static inline void gic_write_eoir(u32 irq)
{
	asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" ((u64)irq));
	isb();
}

static inline void gic_write_dir(u32 irq)
{
	asm volatile("msr_s " __stringify(ICC_DIR_EL1) ", %0" : : "r" ((u64)irq));
	isb();
}

static inline u64 gic_read_iar_common(void)
{
	u64 irqstat;

	asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
	return irqstat;
}

/*
 * Cavium ThunderX erratum 23154
 *
 * The gicv3 of ThunderX requires a modified version for reading the
 * IAR status to ensure data synchronization (access to icc_iar1_el1
 * is not sync'ed before and after).
 */
static inline u64 gic_read_iar_cavium_thunderx(void)
{
	u64 irqstat;

	asm volatile(
		"nop;nop;nop;nop\n\t"
		"nop;nop;nop;nop\n\t"
		"mrs_s %0, " __stringify(ICC_IAR1_EL1) "\n\t"
		"nop;nop;nop;nop"
		: "=r" (irqstat));
	mb();

	return irqstat;
}

static inline void gic_write_pmr(u32 val)
{
	asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" ((u64)val));
}

static inline void gic_write_ctlr(u32 val)
{
	asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" ((u64)val));
	isb();
}

static inline void gic_write_grpen1(u32 val)
{
	asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" ((u64)val));
	isb();
}

static inline void gic_write_sgi1r(u64 val)
{
	asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));
}

static inline u32 gic_read_sre(void)
{
	u64 val;

	asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
	return val;
}

static inline void gic_write_sre(u32 val)
{
	asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" ((u64)val));
	isb();
}

#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARCH_GICV3_H */
Commit	Line	Data
7936e914 JPB	1	/*
	2	* arch/arm64/include/asm/arch_gicv3.h
	3	*
	4	* Copyright (C) 2015 ARM Ltd.
	5	*
	6	* This program is free software: you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	17	*/
	18	#ifndef __ASM_ARCH_GICV3_H
	19	#define __ASM_ARCH_GICV3_H
	20
	21	#include <asm/sysreg.h>
	22
	23	#define ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
	24	#define ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
	25	#define ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
	26	#define ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
	27	#define ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
	28	#define ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
	29	#define ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
	30	#define ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
	31
	32	#define ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
	33
	34	/*
	35	* System register definitions
	36	*/
	37	#define ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
	38	#define ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
	39	#define ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
	40	#define ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
	41	#define ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
	42	#define ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5)
	43	#define ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
	44
	45	#define __LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
	46	#define __LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
	47
	48	#define ICH_LR0_EL2 __LR0_EL2(0)
	49	#define ICH_LR1_EL2 __LR0_EL2(1)
	50	#define ICH_LR2_EL2 __LR0_EL2(2)
	51	#define ICH_LR3_EL2 __LR0_EL2(3)
	52	#define ICH_LR4_EL2 __LR0_EL2(4)
	53	#define ICH_LR5_EL2 __LR0_EL2(5)
	54	#define ICH_LR6_EL2 __LR0_EL2(6)
	55	#define ICH_LR7_EL2 __LR0_EL2(7)
	56	#define ICH_LR8_EL2 __LR8_EL2(0)
	57	#define ICH_LR9_EL2 __LR8_EL2(1)
	58	#define ICH_LR10_EL2 __LR8_EL2(2)
	59	#define ICH_LR11_EL2 __LR8_EL2(3)
	60	#define ICH_LR12_EL2 __LR8_EL2(4)
	61	#define ICH_LR13_EL2 __LR8_EL2(5)
	62	#define ICH_LR14_EL2 __LR8_EL2(6)
	63	#define ICH_LR15_EL2 __LR8_EL2(7)
	64
65	#define __AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
66	#define ICH_AP0R0_EL2 __AP0Rx_EL2(0)
67	#define ICH_AP0R1_EL2 __AP0Rx_EL2(1)
68	#define ICH_AP0R2_EL2 __AP0Rx_EL2(2)
69	#define ICH_AP0R3_EL2 __AP0Rx_EL2(3)
70
71	#define __AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
72	#define ICH_AP1R0_EL2 __AP1Rx_EL2(0)
73	#define ICH_AP1R1_EL2 __AP1Rx_EL2(1)
74	#define ICH_AP1R2_EL2 __AP1Rx_EL2(2)
75	#define ICH_AP1R3_EL2 __AP1Rx_EL2(3)
76
77	#ifndef __ASSEMBLY__
78
79	#include <linux/stringify.h>
80
f6c86a41 JPB	81	/*
	82	* Low-level accessors
	83	*
	84	* These system registers are 32 bits, but we make sure that the compiler
	85	* sets the GP register's most significant bits to 0 with an explicit cast.
	86	*/
7936e914	87
f6c86a41	88	static inline void gic_write_eoir(u32 irq)
7936e914	89	{
f6c86a41	90	asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" ((u64)irq));
7936e914 JPB	91	isb();
	92	}
	93
f6c86a41	94	static inline void gic_write_dir(u32 irq)
7936e914	95	{
f6c86a41	96	asm volatile("msr_s " __stringify(ICC_DIR_EL1) ", %0" : : "r" ((u64)irq));
7936e914 JPB	97	isb();
	98	}
	99
	100	static inline u64 gic_read_iar_common(void)
	101	{
	102	u64 irqstat;
	103
	104	asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));
	105	return irqstat;
	106	}
	107
	108	/*
	109	* Cavium ThunderX erratum 23154
	110	*
	111	* The gicv3 of ThunderX requires a modified version for reading the
	112	* IAR status to ensure data synchronization (access to icc_iar1_el1
	113	* is not sync'ed before and after).
	114	*/
	115	static inline u64 gic_read_iar_cavium_thunderx(void)
	116	{
	117	u64 irqstat;
	118
	119	asm volatile(
	120	"nop;nop;nop;nop\n\t"
	121	"nop;nop;nop;nop\n\t"
	122	"mrs_s %0, " __stringify(ICC_IAR1_EL1) "\n\t"
	123	"nop;nop;nop;nop"
	124	: "=r" (irqstat));
	125	mb();
	126
	127	return irqstat;
	128	}
	129
f6c86a41	130	static inline void gic_write_pmr(u32 val)
7936e914	131	{
f6c86a41	132	asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" ((u64)val));
7936e914 JPB	133	}
7936e914 JPB	134
f6c86a41	135	static inline void gic_write_ctlr(u32 val)
7936e914	136	{
f6c86a41	137	asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" ((u64)val));
7936e914 JPB	138	isb();
	139	}
	140
f6c86a41	141	static inline void gic_write_grpen1(u32 val)
7936e914	142	{
f6c86a41	143	asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" ((u64)val));
7936e914 JPB	144	isb();
	145	}
	146
	147	static inline void gic_write_sgi1r(u64 val)
	148	{
	149	asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));
	150	}
	151
f6c86a41	152	static inline u32 gic_read_sre(void)
7936e914 JPB	153	{
	154	u64 val;
	155
	156	asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));
	157	return val;
	158	}
	159
f6c86a41	160	static inline void gic_write_sre(u32 val)
7936e914	161	{
f6c86a41	162	asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" ((u64)val));
7936e914 JPB	163	isb();
	164	}
	165
	166	#endif /* __ASSEMBLY__ */
	167	#endif /* __ASM_ARCH_GICV3_H */