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caab277b | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
272d01bd CM |
2 | /* |
3 | * arch/arm64/include/asm/cpucaps.h | |
4 | * | |
5 | * Copyright (C) 2016 ARM Ltd. | |
272d01bd CM |
6 | */ |
7 | #ifndef __ASM_CPUCAPS_H | |
8 | #define __ASM_CPUCAPS_H | |
9 | ||
10 | #define ARM64_WORKAROUND_CLEAN_CACHE 0 | |
11 | #define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE 1 | |
12 | #define ARM64_WORKAROUND_845719 2 | |
13 | #define ARM64_HAS_SYSREG_GIC_CPUIF 3 | |
14 | #define ARM64_HAS_PAN 4 | |
15 | #define ARM64_HAS_LSE_ATOMICS 5 | |
16 | #define ARM64_WORKAROUND_CAVIUM_23154 6 | |
17 | #define ARM64_WORKAROUND_834220 7 | |
18 | #define ARM64_HAS_NO_HW_PREFETCH 8 | |
272d01bd CM |
19 | #define ARM64_HAS_VIRT_HOST_EXTN 11 |
20 | #define ARM64_WORKAROUND_CAVIUM_27456 12 | |
21 | #define ARM64_HAS_32BIT_EL0 13 | |
c4792b6d | 22 | #define ARM64_SPECTRE_V3A 14 |
880f7cc4 | 23 | #define ARM64_HAS_CNP 15 |
f4000cd9 | 24 | #define ARM64_HAS_NO_FPSIMD 16 |
d9ff80f8 | 25 | #define ARM64_WORKAROUND_REPEAT_TLBI 17 |
38fd94b0 | 26 | #define ARM64_WORKAROUND_QCOM_FALKOR_E1003 18 |
eeb1efbc | 27 | #define ARM64_WORKAROUND_858921 19 |
690a3415 | 28 | #define ARM64_WORKAROUND_CAVIUM_30115 20 |
d50e071f | 29 | #define ARM64_HAS_DCPOP 21 |
43994d82 | 30 | #define ARM64_SVE 22 |
ea1e3de8 | 31 | #define ARM64_UNMAP_KERNEL_AT_EL0 23 |
688f1e4b | 32 | #define ARM64_SPECTRE_V2 24 |
4bc352ff SD |
33 | #define ARM64_HAS_RAS_EXTN 25 |
34 | #define ARM64_WORKAROUND_843419 26 | |
35 | #define ARM64_HAS_CACHE_IDC 27 | |
36 | #define ARM64_HAS_CACHE_DIC 28 | |
37 | #define ARM64_HW_DBM 29 | |
9b0955ba | 38 | #define ARM64_SPECTRE_V4 30 |
314d53d2 | 39 | #define ARM64_MISMATCHED_CACHE_TYPE 31 |
63198930 | 40 | #define ARM64_HAS_STAGE2_FWB 32 |
86d0dd34 | 41 | #define ARM64_HAS_CRC32 33 |
d71be2b6 | 42 | #define ARM64_SSBS 34 |
a5325089 | 43 | #define ARM64_WORKAROUND_1418040 35 |
bd4fb6d2 | 44 | #define ARM64_HAS_SB 36 |
c350717e | 45 | #define ARM64_WORKAROUND_SPECULATIVE_AT 37 |
6984eb47 MR |
46 | #define ARM64_HAS_ADDRESS_AUTH_ARCH 38 |
47 | #define ARM64_HAS_ADDRESS_AUTH_IMP_DEF 39 | |
a56005d3 WD |
48 | #define ARM64_HAS_GENERIC_AUTH_ARCH 40 |
49 | #define ARM64_HAS_GENERIC_AUTH_IMP_DEF 41 | |
b90d2b22 | 50 | #define ARM64_HAS_IRQ_PRIO_MASKING 42 |
b9585f53 | 51 | #define ARM64_HAS_DCPODP 43 |
969f5ea6 | 52 | #define ARM64_WORKAROUND_1463225 44 |
d3ec3a08 | 53 | #define ARM64_WORKAROUND_CAVIUM_TX2_219_TVM 45 |
9405447e | 54 | #define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 46 |
6a036afb | 55 | #define ARM64_WORKAROUND_1542419 47 |
02ab1f50 AS |
56 | #define ARM64_HAS_E0PD 48 |
57 | #define ARM64_HAS_RNG 49 | |
58 | #define ARM64_HAS_AMU_EXTN 50 | |
59 | #define ARM64_HAS_ADDRESS_AUTH 51 | |
60 | #define ARM64_HAS_GENERIC_AUTH 52 | |
c350717e WD |
61 | #define ARM64_HAS_32BIT_EL1 53 |
62 | #define ARM64_BTI 54 | |
552ae76f | 63 | #define ARM64_HAS_ARMv8_4_TTL 55 |
b620ba54 | 64 | #define ARM64_HAS_TLB_RANGE 56 |
3b714d24 | 65 | #define ARM64_MTE 57 |
96d389ca | 66 | #define ARM64_WORKAROUND_1508412 58 |
364a5a8a | 67 | #define ARM64_HAS_LDAPR 59 |
3eb681fb | 68 | #define ARM64_KVM_PROTECTED_MODE 60 |
20109a85 | 69 | #define ARM64_WORKAROUND_NVIDIA_CARMEL_CNP 61 |
272d01bd | 70 | |
20109a85 | 71 | #define ARM64_NCAPS 62 |
272d01bd CM |
72 | |
73 | #endif /* __ASM_CPUCAPS_H */ |