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3be1a5c4 AB |
1 | /* |
2 | * Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org> | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #ifndef __ASM_CPUFEATURE_H | |
10 | #define __ASM_CPUFEATURE_H | |
11 | ||
12 | #include <asm/hwcap.h> | |
cdcf817b | 13 | #include <asm/sysreg.h> |
3be1a5c4 AB |
14 | |
15 | /* | |
16 | * In the arm64 world (as in the ARM world), elf_hwcap is used both internally | |
17 | * in the kernel and for user space to keep track of which optional features | |
18 | * are supported by the current system. So let's map feature 'x' to HWCAP_x. | |
19 | * Note that HWCAP_x constants are bit fields so we need to take the log. | |
20 | */ | |
21 | ||
22 | #define MAX_CPU_FEATURES (8 * sizeof(elf_hwcap)) | |
23 | #define cpu_feature(x) ilog2(HWCAP_ ## x) | |
24 | ||
5afaa1fc AP |
25 | #define ARM64_WORKAROUND_CLEAN_CACHE 0 |
26 | #define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE 1 | |
905e8c5d | 27 | #define ARM64_WORKAROUND_845719 2 |
94a9e04a | 28 | #define ARM64_HAS_SYSREG_GIC_CPUIF 3 |
338d4f49 | 29 | #define ARM64_HAS_PAN 4 |
c739dc83 | 30 | #define ARM64_HAS_LSE_ATOMICS 5 |
301bcfac | 31 | |
d964b722 | 32 | #define ARM64_NCAPS 6 |
301bcfac AP |
33 | |
34 | #ifndef __ASSEMBLY__ | |
930da09f | 35 | |
144e9697 WD |
36 | #include <linux/kernel.h> |
37 | ||
359b7064 MZ |
38 | struct arm64_cpu_capabilities { |
39 | const char *desc; | |
40 | u16 capability; | |
41 | bool (*matches)(const struct arm64_cpu_capabilities *); | |
1c076303 | 42 | void (*enable)(void); |
359b7064 MZ |
43 | union { |
44 | struct { /* To be used for erratum handling only */ | |
45 | u32 midr_model; | |
46 | u32 midr_range_min, midr_range_max; | |
47 | }; | |
94a9e04a MZ |
48 | |
49 | struct { /* Feature register checking */ | |
18ffa046 JM |
50 | int field_pos; |
51 | int min_field_value; | |
94a9e04a | 52 | }; |
359b7064 MZ |
53 | }; |
54 | }; | |
55 | ||
06f9eb88 | 56 | extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); |
930da09f | 57 | |
3be1a5c4 AB |
58 | static inline bool cpu_have_feature(unsigned int num) |
59 | { | |
60 | return elf_hwcap & (1UL << num); | |
61 | } | |
62 | ||
930da09f AP |
63 | static inline bool cpus_have_cap(unsigned int num) |
64 | { | |
06f9eb88 | 65 | if (num >= ARM64_NCAPS) |
930da09f AP |
66 | return false; |
67 | return test_bit(num, cpu_hwcaps); | |
68 | } | |
69 | ||
70 | static inline void cpus_set_cap(unsigned int num) | |
71 | { | |
06f9eb88 | 72 | if (num >= ARM64_NCAPS) |
930da09f | 73 | pr_warn("Attempt to set an illegal CPU capability (%d >= %d)\n", |
06f9eb88 | 74 | num, ARM64_NCAPS); |
930da09f AP |
75 | else |
76 | __set_bit(num, cpu_hwcaps); | |
77 | } | |
78 | ||
79b0e09a JM |
79 | static inline int __attribute_const__ cpuid_feature_extract_field(u64 features, |
80 | int field) | |
81 | { | |
82 | return (s64)(features << (64 - 4 - field)) >> (64 - 4); | |
83 | } | |
84 | ||
cdcf817b SP |
85 | static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0) |
86 | { | |
87 | return cpuid_feature_extract_field(mmfr0, ID_AA64MMFR0_BIGENDEL_SHIFT) == 0x1 || | |
88 | cpuid_feature_extract_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1; | |
89 | } | |
90 | ||
3a75578e | 91 | void __init setup_cpu_features(void); |
79b0e09a | 92 | |
359b7064 MZ |
93 | void check_cpu_capabilities(const struct arm64_cpu_capabilities *caps, |
94 | const char *info); | |
e116a375 | 95 | void check_local_cpu_errata(void); |
359b7064 | 96 | void check_local_cpu_features(void); |
04597a65 SP |
97 | bool cpu_supports_mixed_endian_el0(void); |
98 | bool system_supports_mixed_endian_el0(void); | |
e116a375 | 99 | |
301bcfac AP |
100 | #endif /* __ASSEMBLY__ */ |
101 | ||
3be1a5c4 | 102 | #endif |