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9cce7a43 CM |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | #ifndef __ASM_CPUTYPE_H | |
17 | #define __ASM_CPUTYPE_H | |
18 | ||
3e98fdac JM |
19 | #define INVALID_HWID ULONG_MAX |
20 | ||
4e6f7084 ZSL |
21 | #define MPIDR_UP_BITMASK (0x1 << 30) |
22 | #define MPIDR_MT_BITMASK (0x1 << 24) | |
4c7aa002 JM |
23 | #define MPIDR_HWID_BITMASK 0xff00ffffff |
24 | ||
b058450f LP |
25 | #define MPIDR_LEVEL_BITS_SHIFT 3 |
26 | #define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT) | |
27 | #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) | |
28 | ||
29 | #define MPIDR_LEVEL_SHIFT(level) \ | |
30 | (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT) | |
31 | ||
32 | #define MPIDR_AFFINITY_LEVEL(mpidr, level) \ | |
33 | ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK) | |
34 | ||
89c4a306 MR |
35 | #define MIDR_REVISION_MASK 0xf |
36 | #define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK) | |
37 | #define MIDR_PARTNUM_SHIFT 4 | |
38 | #define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT) | |
39 | #define MIDR_PARTNUM(midr) \ | |
40 | (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT) | |
41 | #define MIDR_ARCHITECTURE_SHIFT 16 | |
42 | #define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT) | |
43 | #define MIDR_ARCHITECTURE(midr) \ | |
44 | (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT) | |
45 | #define MIDR_VARIANT_SHIFT 20 | |
46 | #define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT) | |
47 | #define MIDR_VARIANT(midr) \ | |
48 | (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT) | |
49 | #define MIDR_IMPLEMENTOR_SHIFT 24 | |
50 | #define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT) | |
51 | #define MIDR_IMPLEMENTOR(midr) \ | |
52 | (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT) | |
53 | ||
d5370f75 | 54 | #define MIDR_CPU_MODEL(imp, partnum) \ |
301bcfac AP |
55 | (((imp) << MIDR_IMPLEMENTOR_SHIFT) | \ |
56 | (0xf << MIDR_ARCHITECTURE_SHIFT) | \ | |
57 | ((partnum) << MIDR_PARTNUM_SHIFT)) | |
58 | ||
fa5ce3d1 RR |
59 | #define MIDR_CPU_VAR_REV(var, rev) \ |
60 | (((var) << MIDR_VARIANT_SHIFT) | (rev)) | |
61 | ||
d5370f75 WD |
62 | #define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \ |
63 | MIDR_ARCHITECTURE_MASK) | |
64 | ||
65 | #define MIDR_IS_CPU_MODEL_RANGE(midr, model, rv_min, rv_max) \ | |
66 | ({ \ | |
67 | u32 _model = (midr) & MIDR_CPU_MODEL_MASK; \ | |
68 | u32 rv = (midr) & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK); \ | |
69 | \ | |
70 | _model == (model) && rv >= (rv_min) && rv <= (rv_max); \ | |
71 | }) | |
72 | ||
6d4e11c5 RR |
73 | #define ARM_CPU_IMP_ARM 0x41 |
74 | #define ARM_CPU_IMP_APM 0x50 | |
75 | #define ARM_CPU_IMP_CAVIUM 0x43 | |
9eb8a2cd | 76 | #define ARM_CPU_IMP_BRCM 0x42 |
ea5f9d1a | 77 | #define ARM_CPU_IMP_QCOM 0x51 |
d9c1951f | 78 | |
6d4e11c5 RR |
79 | #define ARM_CPU_PART_AEM_V8 0xD0F |
80 | #define ARM_CPU_PART_FOUNDATION 0xD00 | |
81 | #define ARM_CPU_PART_CORTEX_A57 0xD07 | |
82 | #define ARM_CPU_PART_CORTEX_A53 0xD03 | |
199fd2bf | 83 | #define ARM_CPU_PART_CORTEX_A73 0xD09 |
d9c1951f | 84 | |
6d4e11c5 RR |
85 | #define APM_CPU_PART_POTENZA 0x000 |
86 | ||
87 | #define CAVIUM_CPU_PART_THUNDERX 0x0A1 | |
47c459be | 88 | #define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2 |
e982276d | 89 | #define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3 |
4ad637a4 | 90 | |
9eb8a2cd J |
91 | #define BRCM_CPU_PART_VULCAN 0x516 |
92 | ||
ea5f9d1a | 93 | #define QCOM_CPU_PART_FALKOR_V1 0x800 |
82b02d94 | 94 | #define QCOM_CPU_PART_FALKOR 0xC00 |
ea5f9d1a | 95 | |
d5370f75 WD |
96 | #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) |
97 | #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) | |
199fd2bf | 98 | #define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) |
d5370f75 | 99 | #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) |
47c459be | 100 | #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) |
e982276d | 101 | #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) |
ea5f9d1a | 102 | #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1) |
82b02d94 | 103 | #define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR) |
d5370f75 | 104 | |
0359b0e2 JM |
105 | #ifndef __ASSEMBLY__ |
106 | ||
0f54b14e JM |
107 | #include <asm/sysreg.h> |
108 | ||
8a71f0c6 | 109 | #define read_cpuid(reg) read_sysreg_s(SYS_ ## reg) |
0f54b14e | 110 | |
9cce7a43 CM |
111 | /* |
112 | * The CPU ID never changes at run time, so we might as well tell the | |
113 | * compiler that it's constant. Use this function to read the CPU ID | |
114 | * rather than directly reading processor_id or read_cpuid() directly. | |
115 | */ | |
116 | static inline u32 __attribute_const__ read_cpuid_id(void) | |
117 | { | |
1cc6ed90 | 118 | return read_cpuid(MIDR_EL1); |
9cce7a43 CM |
119 | } |
120 | ||
d9c1951f MZ |
121 | static inline u64 __attribute_const__ read_cpuid_mpidr(void) |
122 | { | |
1cc6ed90 | 123 | return read_cpuid(MPIDR_EL1); |
d9c1951f MZ |
124 | } |
125 | ||
126 | static inline unsigned int __attribute_const__ read_cpuid_implementor(void) | |
127 | { | |
89c4a306 | 128 | return MIDR_IMPLEMENTOR(read_cpuid_id()); |
d9c1951f MZ |
129 | } |
130 | ||
131 | static inline unsigned int __attribute_const__ read_cpuid_part_number(void) | |
132 | { | |
89c4a306 | 133 | return MIDR_PARTNUM(read_cpuid_id()); |
d9c1951f MZ |
134 | } |
135 | ||
9cce7a43 CM |
136 | static inline u32 __attribute_const__ read_cpuid_cachetype(void) |
137 | { | |
1cc6ed90 | 138 | return read_cpuid(CTR_EL0); |
9cce7a43 | 139 | } |
0359b0e2 JM |
140 | #endif /* __ASSEMBLY__ */ |
141 | ||
9cce7a43 | 142 | #endif |