[mirror_ubuntu-hirsute-kernel.git] / arch / arm64 / include / asm / debug-monitors.h

/*
 * Copyright (C) 2012 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __ASM_DEBUG_MONITORS_H
#define __ASM_DEBUG_MONITORS_H

#ifdef __KERNEL__

#include <linux/errno.h>
#include <linux/types.h>
#include <asm/brk-imm.h>
#include <asm/esr.h>
#include <asm/insn.h>
#include <asm/ptrace.h>

/* Low-level stepping controls. */
#define DBG_MDSCR_SS		(1 << 0)
#define DBG_SPSR_SS		(1 << 21)

/* MDSCR_EL1 enabling bits */
#define DBG_MDSCR_KDE		(1 << 13)
#define DBG_MDSCR_MDE		(1 << 15)
#define DBG_MDSCR_MASK		~(DBG_MDSCR_KDE | DBG_MDSCR_MDE)

#define	DBG_ESR_EVT(x)		(((x) >> 27) & 0x7)

/* AArch64 */
#define DBG_ESR_EVT_HWBP	0x0
#define DBG_ESR_EVT_HWSS	0x1
#define DBG_ESR_EVT_HWWP	0x2
#define DBG_ESR_EVT_BRK		0x6

/*
 * Break point instruction encoding
 */
#define BREAK_INSTR_SIZE		AARCH64_INSN_SIZE

/*
 * BRK instruction encoding
 * The #imm16 value should be placed at bits[20:5] within BRK ins
 */
#define AARCH64_BREAK_MON	0xd4200000

/*
 * BRK instruction for provoking a fault on purpose
 * Unlike kgdb, #imm16 value with unallocated handler is used for faulting.
 */
#define AARCH64_BREAK_FAULT	(AARCH64_BREAK_MON | (FAULT_BRK_IMM << 5))

#define AARCH64_BREAK_KGDB_DYN_DBG	\
	(AARCH64_BREAK_MON | (KGDB_DYN_DBG_BRK_IMM << 5))

#define CACHE_FLUSH_IS_SAFE		1

/* kprobes BRK opcodes with ESR encoding  */
#define BRK64_ESR_MASK		0xFFFF
#define BRK64_ESR_KPROBES	0x0004
#define BRK64_OPCODE_KPROBES	(AARCH64_BREAK_MON | (BRK64_ESR_KPROBES << 5))

/* AArch32 */
#define DBG_ESR_EVT_BKPT	0x4
#define DBG_ESR_EVT_VECC	0x5

#define AARCH32_BREAK_ARM	0x07f001f0
#define AARCH32_BREAK_THUMB	0xde01
#define AARCH32_BREAK_THUMB2_LO	0xf7f0
#define AARCH32_BREAK_THUMB2_HI	0xa000

#ifndef __ASSEMBLY__
struct task_struct;

#define DBG_ARCH_ID_RESERVED	0	/* In case of ptrace ABI updates. */

#define DBG_HOOK_HANDLED	0
#define DBG_HOOK_ERROR		1

struct step_hook {
	struct list_head node;
	int (*fn)(struct pt_regs *regs, unsigned int esr);
};

void register_step_hook(struct step_hook *hook);
void unregister_step_hook(struct step_hook *hook);

struct break_hook {
	struct list_head node;
	u32 esr_val;
	u32 esr_mask;
	int (*fn)(struct pt_regs *regs, unsigned int esr);
};

void register_break_hook(struct break_hook *hook);
void unregister_break_hook(struct break_hook *hook);

u8 debug_monitors_arch(void);

enum dbg_active_el {
	DBG_ACTIVE_EL0 = 0,
	DBG_ACTIVE_EL1,
};

void enable_debug_monitors(enum dbg_active_el el);
void disable_debug_monitors(enum dbg_active_el el);

void user_rewind_single_step(struct task_struct *task);
void user_fastforward_single_step(struct task_struct *task);

void kernel_enable_single_step(struct pt_regs *regs);
void kernel_disable_single_step(void);
int kernel_active_single_step(void);

#ifdef CONFIG_HAVE_HW_BREAKPOINT
int reinstall_suspended_bps(struct pt_regs *regs);
#else
static inline int reinstall_suspended_bps(struct pt_regs *regs)
{
	return -ENODEV;
}
#endif

int aarch32_break_handler(struct pt_regs *regs);

#endif	/* __ASSEMBLY */
#endif	/* __KERNEL__ */
#endif	/* __ASM_DEBUG_MONITORS_H */
Commit	Line	Data
478fcb2c WD	1	/*
	2	* Copyright (C) 2012 ARM Ltd.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16	#ifndef __ASM_DEBUG_MONITORS_H
	17	#define __ASM_DEBUG_MONITORS_H
	18
	19	#ifdef __KERNEL__
	20
d7a33f4f DM	21	#include <linux/errno.h>
d7a33f4f DM	22	#include <linux/types.h>
f98deee9	23	#include <asm/brk-imm.h>
03923696	24	#include <asm/esr.h>
951757ae	25	#include <asm/insn.h>
d7a33f4f	26	#include <asm/ptrace.h>
951757ae	27
51ba2481 MZ	28	/* Low-level stepping controls. */
	29	#define DBG_MDSCR_SS (1 << 0)
	30	#define DBG_SPSR_SS (1 << 21)
	31
	32	/* MDSCR_EL1 enabling bits */
	33	#define DBG_MDSCR_KDE (1 << 13)
	34	#define DBG_MDSCR_MDE (1 << 15)
	35	#define DBG_MDSCR_MASK ~(DBG_MDSCR_KDE \| DBG_MDSCR_MDE)
	36
478fcb2c WD	37	#define DBG_ESR_EVT(x) (((x) >> 27) & 0x7)
	38
	39	/* AArch64 */
	40	#define DBG_ESR_EVT_HWBP 0x0
	41	#define DBG_ESR_EVT_HWSS 0x1
	42	#define DBG_ESR_EVT_HWWP 0x2
	43	#define DBG_ESR_EVT_BRK 0x6
	44
bcf5763b VK	45	/*
	46	* Break point instruction encoding
	47	*/
951757ae	48	#define BREAK_INSTR_SIZE AARCH64_INSN_SIZE
bcf5763b	49
bcf5763b VK	50	/*
	51	* BRK instruction encoding
	52	* The #imm16 value should be placed at bits[20:5] within BRK ins
	53	*/
	54	#define AARCH64_BREAK_MON 0xd4200000
	55
a9ae04c9 MB	56	/*
	57	* BRK instruction for provoking a fault on purpose
	58	* Unlike kgdb, #imm16 value with unallocated handler is used for faulting.
	59	*/
	60	#define AARCH64_BREAK_FAULT (AARCH64_BREAK_MON \| (FAULT_BRK_IMM << 5))
	61
c696b934 DM	62	#define AARCH64_BREAK_KGDB_DYN_DBG \
c696b934 DM	63	(AARCH64_BREAK_MON \| (KGDB_DYN_DBG_BRK_IMM << 5))
bcf5763b VK	64
	65	#define CACHE_FLUSH_IS_SAFE 1
	66
2dd0e8d2 SP	67	/* kprobes BRK opcodes with ESR encoding */
	68	#define BRK64_ESR_MASK 0xFFFF
	69	#define BRK64_ESR_KPROBES 0x0004
	70	#define BRK64_OPCODE_KPROBES (AARCH64_BREAK_MON \| (BRK64_ESR_KPROBES << 5))
	71
478fcb2c WD	72	/* AArch32 */
	73	#define DBG_ESR_EVT_BKPT 0x4
	74	#define DBG_ESR_EVT_VECC 0x5
	75
	76	#define AARCH32_BREAK_ARM 0x07f001f0
	77	#define AARCH32_BREAK_THUMB 0xde01
	78	#define AARCH32_BREAK_THUMB2_LO 0xf7f0
	79	#define AARCH32_BREAK_THUMB2_HI 0xa000
	80
	81	#ifndef __ASSEMBLY__
	82	struct task_struct;
	83
478fcb2c WD	84	#define DBG_ARCH_ID_RESERVED 0 /* In case of ptrace ABI updates. */
478fcb2c WD	85
ee6214ce SP	86	#define DBG_HOOK_HANDLED 0
	87	#define DBG_HOOK_ERROR 1
	88
	89	struct step_hook {
	90	struct list_head node;
	91	int (fn)(struct pt_regs regs, unsigned int esr);
	92	};
	93
	94	void register_step_hook(struct step_hook *hook);
	95	void unregister_step_hook(struct step_hook *hook);
	96
	97	struct break_hook {
	98	struct list_head node;
	99	u32 esr_val;
	100	u32 esr_mask;
	101	int (fn)(struct pt_regs regs, unsigned int esr);
	102	};
	103
	104	void register_break_hook(struct break_hook *hook);
	105	void unregister_break_hook(struct break_hook *hook);
	106
478fcb2c WD	107	u8 debug_monitors_arch(void);
478fcb2c WD	108
6f883d10	109	enum dbg_active_el {
51ba2481 MZ	110	DBG_ACTIVE_EL0 = 0,
	111	DBG_ACTIVE_EL1,
	112	};
	113
6f883d10 WD	114	void enable_debug_monitors(enum dbg_active_el el);
6f883d10 WD	115	void disable_debug_monitors(enum dbg_active_el el);
478fcb2c WD	116
	117	void user_rewind_single_step(struct task_struct *task);
	118	void user_fastforward_single_step(struct task_struct *task);
	119
	120	void kernel_enable_single_step(struct pt_regs *regs);
	121	void kernel_disable_single_step(void);
	122	int kernel_active_single_step(void);
	123
	124	#ifdef CONFIG_HAVE_HW_BREAKPOINT
	125	int reinstall_suspended_bps(struct pt_regs *regs);
	126	#else
	127	static inline int reinstall_suspended_bps(struct pt_regs *regs)
	128	{
	129	return -ENODEV;
	130	}
	131	#endif
	132
1442b6ed	133	int aarch32_break_handler(struct pt_regs *regs);
1442b6ed	134
478fcb2c WD	135	#endif /* __ASSEMBLY */
	136	#endif /* __KERNEL__ */
	137	#endif /* __ASM_DEBUG_MONITORS_H */