]>
Commit | Line | Data |
---|---|---|
478fcb2c WD |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | #ifndef __ASM_DEBUG_MONITORS_H | |
17 | #define __ASM_DEBUG_MONITORS_H | |
18 | ||
19 | #ifdef __KERNEL__ | |
20 | ||
51ba2481 MZ |
21 | /* Low-level stepping controls. */ |
22 | #define DBG_MDSCR_SS (1 << 0) | |
23 | #define DBG_SPSR_SS (1 << 21) | |
24 | ||
25 | /* MDSCR_EL1 enabling bits */ | |
26 | #define DBG_MDSCR_KDE (1 << 13) | |
27 | #define DBG_MDSCR_MDE (1 << 15) | |
28 | #define DBG_MDSCR_MASK ~(DBG_MDSCR_KDE | DBG_MDSCR_MDE) | |
29 | ||
478fcb2c WD |
30 | #define DBG_ESR_EVT(x) (((x) >> 27) & 0x7) |
31 | ||
32 | /* AArch64 */ | |
33 | #define DBG_ESR_EVT_HWBP 0x0 | |
34 | #define DBG_ESR_EVT_HWSS 0x1 | |
35 | #define DBG_ESR_EVT_HWWP 0x2 | |
36 | #define DBG_ESR_EVT_BRK 0x6 | |
37 | ||
bcf5763b VK |
38 | /* |
39 | * Break point instruction encoding | |
40 | */ | |
41 | #define BREAK_INSTR_SIZE 4 | |
42 | ||
43 | /* | |
44 | * ESR values expected for dynamic and compile time BRK instruction | |
45 | */ | |
46 | #define DBG_ESR_VAL_BRK(x) (0xf2000000 | ((x) & 0xfffff)) | |
47 | ||
48 | /* | |
49 | * #imm16 values used for BRK instruction generation | |
50 | * Allowed values for kgbd are 0x400 - 0x7ff | |
51 | * 0x400: for dynamic BRK instruction | |
52 | * 0x401: for compile time BRK instruction | |
53 | */ | |
54 | #define KGDB_DYN_DGB_BRK_IMM 0x400 | |
55 | #define KDBG_COMPILED_DBG_BRK_IMM 0x401 | |
56 | ||
57 | /* | |
58 | * BRK instruction encoding | |
59 | * The #imm16 value should be placed at bits[20:5] within BRK ins | |
60 | */ | |
61 | #define AARCH64_BREAK_MON 0xd4200000 | |
62 | ||
63 | /* | |
64 | * Extract byte from BRK instruction | |
65 | */ | |
66 | #define KGDB_DYN_DGB_BRK_INS_BYTE(x) \ | |
67 | ((((AARCH64_BREAK_MON) & 0xffe0001f) >> (x * 8)) & 0xff) | |
68 | ||
69 | /* | |
70 | * Extract byte from BRK #imm16 | |
71 | */ | |
72 | #define KGBD_DYN_DGB_BRK_IMM_BYTE(x) \ | |
73 | (((((KGDB_DYN_DGB_BRK_IMM) & 0xffff) << 5) >> (x * 8)) & 0xff) | |
74 | ||
75 | #define KGDB_DYN_DGB_BRK_BYTE(x) \ | |
76 | (KGDB_DYN_DGB_BRK_INS_BYTE(x) | KGBD_DYN_DGB_BRK_IMM_BYTE(x)) | |
77 | ||
78 | #define KGDB_DYN_BRK_INS_BYTE0 KGDB_DYN_DGB_BRK_BYTE(0) | |
79 | #define KGDB_DYN_BRK_INS_BYTE1 KGDB_DYN_DGB_BRK_BYTE(1) | |
80 | #define KGDB_DYN_BRK_INS_BYTE2 KGDB_DYN_DGB_BRK_BYTE(2) | |
81 | #define KGDB_DYN_BRK_INS_BYTE3 KGDB_DYN_DGB_BRK_BYTE(3) | |
82 | ||
83 | #define CACHE_FLUSH_IS_SAFE 1 | |
84 | ||
478fcb2c WD |
85 | /* AArch32 */ |
86 | #define DBG_ESR_EVT_BKPT 0x4 | |
87 | #define DBG_ESR_EVT_VECC 0x5 | |
88 | ||
89 | #define AARCH32_BREAK_ARM 0x07f001f0 | |
90 | #define AARCH32_BREAK_THUMB 0xde01 | |
91 | #define AARCH32_BREAK_THUMB2_LO 0xf7f0 | |
92 | #define AARCH32_BREAK_THUMB2_HI 0xa000 | |
93 | ||
94 | #ifndef __ASSEMBLY__ | |
95 | struct task_struct; | |
96 | ||
478fcb2c WD |
97 | #define DBG_ARCH_ID_RESERVED 0 /* In case of ptrace ABI updates. */ |
98 | ||
ee6214ce SP |
99 | #define DBG_HOOK_HANDLED 0 |
100 | #define DBG_HOOK_ERROR 1 | |
101 | ||
102 | struct step_hook { | |
103 | struct list_head node; | |
104 | int (*fn)(struct pt_regs *regs, unsigned int esr); | |
105 | }; | |
106 | ||
107 | void register_step_hook(struct step_hook *hook); | |
108 | void unregister_step_hook(struct step_hook *hook); | |
109 | ||
110 | struct break_hook { | |
111 | struct list_head node; | |
112 | u32 esr_val; | |
113 | u32 esr_mask; | |
114 | int (*fn)(struct pt_regs *regs, unsigned int esr); | |
115 | }; | |
116 | ||
117 | void register_break_hook(struct break_hook *hook); | |
118 | void unregister_break_hook(struct break_hook *hook); | |
119 | ||
478fcb2c WD |
120 | u8 debug_monitors_arch(void); |
121 | ||
51ba2481 MZ |
122 | enum debug_el { |
123 | DBG_ACTIVE_EL0 = 0, | |
124 | DBG_ACTIVE_EL1, | |
125 | }; | |
126 | ||
478fcb2c WD |
127 | void enable_debug_monitors(enum debug_el el); |
128 | void disable_debug_monitors(enum debug_el el); | |
129 | ||
130 | void user_rewind_single_step(struct task_struct *task); | |
131 | void user_fastforward_single_step(struct task_struct *task); | |
132 | ||
133 | void kernel_enable_single_step(struct pt_regs *regs); | |
134 | void kernel_disable_single_step(void); | |
135 | int kernel_active_single_step(void); | |
136 | ||
137 | #ifdef CONFIG_HAVE_HW_BREAKPOINT | |
138 | int reinstall_suspended_bps(struct pt_regs *regs); | |
139 | #else | |
140 | static inline int reinstall_suspended_bps(struct pt_regs *regs) | |
141 | { | |
142 | return -ENODEV; | |
143 | } | |
144 | #endif | |
145 | ||
1442b6ed | 146 | int aarch32_break_handler(struct pt_regs *regs); |
1442b6ed | 147 | |
478fcb2c WD |
148 | #endif /* __ASSEMBLY */ |
149 | #endif /* __KERNEL__ */ | |
150 | #endif /* __ASM_DEBUG_MONITORS_H */ |