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caab277b | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
478fcb2c WD |
2 | /* |
3 | * Copyright (C) 2012 ARM Ltd. | |
478fcb2c WD |
4 | */ |
5 | #ifndef __ASM_DEBUG_MONITORS_H | |
6 | #define __ASM_DEBUG_MONITORS_H | |
7 | ||
8 | #ifdef __KERNEL__ | |
9 | ||
d7a33f4f DM |
10 | #include <linux/errno.h> |
11 | #include <linux/types.h> | |
f98deee9 | 12 | #include <asm/brk-imm.h> |
03923696 | 13 | #include <asm/esr.h> |
951757ae | 14 | #include <asm/insn.h> |
d7a33f4f | 15 | #include <asm/ptrace.h> |
951757ae | 16 | |
51ba2481 MZ |
17 | /* Low-level stepping controls. */ |
18 | #define DBG_MDSCR_SS (1 << 0) | |
19 | #define DBG_SPSR_SS (1 << 21) | |
20 | ||
21 | /* MDSCR_EL1 enabling bits */ | |
22 | #define DBG_MDSCR_KDE (1 << 13) | |
23 | #define DBG_MDSCR_MDE (1 << 15) | |
24 | #define DBG_MDSCR_MASK ~(DBG_MDSCR_KDE | DBG_MDSCR_MDE) | |
25 | ||
478fcb2c WD |
26 | #define DBG_ESR_EVT(x) (((x) >> 27) & 0x7) |
27 | ||
28 | /* AArch64 */ | |
29 | #define DBG_ESR_EVT_HWBP 0x0 | |
30 | #define DBG_ESR_EVT_HWSS 0x1 | |
31 | #define DBG_ESR_EVT_HWWP 0x2 | |
32 | #define DBG_ESR_EVT_BRK 0x6 | |
33 | ||
bcf5763b VK |
34 | /* |
35 | * Break point instruction encoding | |
36 | */ | |
951757ae | 37 | #define BREAK_INSTR_SIZE AARCH64_INSN_SIZE |
bcf5763b | 38 | |
bcf5763b VK |
39 | /* |
40 | * BRK instruction encoding | |
41 | * The #imm16 value should be placed at bits[20:5] within BRK ins | |
42 | */ | |
43 | #define AARCH64_BREAK_MON 0xd4200000 | |
44 | ||
a9ae04c9 MB |
45 | /* |
46 | * BRK instruction for provoking a fault on purpose | |
47 | * Unlike kgdb, #imm16 value with unallocated handler is used for faulting. | |
48 | */ | |
49 | #define AARCH64_BREAK_FAULT (AARCH64_BREAK_MON | (FAULT_BRK_IMM << 5)) | |
50 | ||
c696b934 DM |
51 | #define AARCH64_BREAK_KGDB_DYN_DBG \ |
52 | (AARCH64_BREAK_MON | (KGDB_DYN_DBG_BRK_IMM << 5)) | |
bcf5763b VK |
53 | |
54 | #define CACHE_FLUSH_IS_SAFE 1 | |
55 | ||
2dd0e8d2 | 56 | /* kprobes BRK opcodes with ESR encoding */ |
453b7740 | 57 | #define BRK64_OPCODE_KPROBES (AARCH64_BREAK_MON | (KPROBES_BRK_IMM << 5)) |
9842ceae | 58 | /* uprobes BRK opcodes with ESR encoding */ |
453b7740 | 59 | #define BRK64_OPCODE_UPROBES (AARCH64_BREAK_MON | (UPROBES_BRK_IMM << 5)) |
2dd0e8d2 | 60 | |
478fcb2c WD |
61 | /* AArch32 */ |
62 | #define DBG_ESR_EVT_BKPT 0x4 | |
63 | #define DBG_ESR_EVT_VECC 0x5 | |
64 | ||
65 | #define AARCH32_BREAK_ARM 0x07f001f0 | |
66 | #define AARCH32_BREAK_THUMB 0xde01 | |
67 | #define AARCH32_BREAK_THUMB2_LO 0xf7f0 | |
68 | #define AARCH32_BREAK_THUMB2_HI 0xa000 | |
69 | ||
70 | #ifndef __ASSEMBLY__ | |
71 | struct task_struct; | |
72 | ||
478fcb2c WD |
73 | #define DBG_ARCH_ID_RESERVED 0 /* In case of ptrace ABI updates. */ |
74 | ||
ee6214ce SP |
75 | #define DBG_HOOK_HANDLED 0 |
76 | #define DBG_HOOK_ERROR 1 | |
77 | ||
78 | struct step_hook { | |
79 | struct list_head node; | |
80 | int (*fn)(struct pt_regs *regs, unsigned int esr); | |
81 | }; | |
82 | ||
26a04d84 WD |
83 | void register_user_step_hook(struct step_hook *hook); |
84 | void unregister_user_step_hook(struct step_hook *hook); | |
85 | ||
86 | void register_kernel_step_hook(struct step_hook *hook); | |
87 | void unregister_kernel_step_hook(struct step_hook *hook); | |
ee6214ce SP |
88 | |
89 | struct break_hook { | |
90 | struct list_head node; | |
ee6214ce | 91 | int (*fn)(struct pt_regs *regs, unsigned int esr); |
26a04d84 WD |
92 | u16 imm; |
93 | u16 mask; /* These bits are ignored when comparing with imm */ | |
ee6214ce SP |
94 | }; |
95 | ||
26a04d84 WD |
96 | void register_user_break_hook(struct break_hook *hook); |
97 | void unregister_user_break_hook(struct break_hook *hook); | |
98 | ||
99 | void register_kernel_break_hook(struct break_hook *hook); | |
100 | void unregister_kernel_break_hook(struct break_hook *hook); | |
ee6214ce | 101 | |
478fcb2c WD |
102 | u8 debug_monitors_arch(void); |
103 | ||
6f883d10 | 104 | enum dbg_active_el { |
51ba2481 MZ |
105 | DBG_ACTIVE_EL0 = 0, |
106 | DBG_ACTIVE_EL1, | |
107 | }; | |
108 | ||
6f883d10 WD |
109 | void enable_debug_monitors(enum dbg_active_el el); |
110 | void disable_debug_monitors(enum dbg_active_el el); | |
478fcb2c WD |
111 | |
112 | void user_rewind_single_step(struct task_struct *task); | |
113 | void user_fastforward_single_step(struct task_struct *task); | |
114 | ||
115 | void kernel_enable_single_step(struct pt_regs *regs); | |
116 | void kernel_disable_single_step(void); | |
117 | int kernel_active_single_step(void); | |
118 | ||
119 | #ifdef CONFIG_HAVE_HW_BREAKPOINT | |
120 | int reinstall_suspended_bps(struct pt_regs *regs); | |
121 | #else | |
122 | static inline int reinstall_suspended_bps(struct pt_regs *regs) | |
123 | { | |
124 | return -ENODEV; | |
125 | } | |
126 | #endif | |
127 | ||
1442b6ed | 128 | int aarch32_break_handler(struct pt_regs *regs); |
1442b6ed | 129 | |
478fcb2c WD |
130 | #endif /* __ASSEMBLY */ |
131 | #endif /* __KERNEL__ */ | |
132 | #endif /* __ASM_DEBUG_MONITORS_H */ |