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5c1ce6f7 MZ |
1 | /* |
2 | * Copyright (C) 2013 - ARM Ltd | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #ifndef __ASM_ESR_H | |
19 | #define __ASM_ESR_H | |
20 | ||
d7a33f4f DM |
21 | #include <asm/memory.h> |
22 | ||
cf99a48d MR |
23 | #define ESR_ELx_EC_UNKNOWN (0x00) |
24 | #define ESR_ELx_EC_WFx (0x01) | |
25 | /* Unallocated EC: 0x02 */ | |
26 | #define ESR_ELx_EC_CP15_32 (0x03) | |
27 | #define ESR_ELx_EC_CP15_64 (0x04) | |
28 | #define ESR_ELx_EC_CP14_MR (0x05) | |
29 | #define ESR_ELx_EC_CP14_LS (0x06) | |
30 | #define ESR_ELx_EC_FP_ASIMD (0x07) | |
31 | #define ESR_ELx_EC_CP10_ID (0x08) | |
32 | /* Unallocated EC: 0x09 - 0x0B */ | |
33 | #define ESR_ELx_EC_CP14_64 (0x0C) | |
34 | /* Unallocated EC: 0x0d */ | |
35 | #define ESR_ELx_EC_ILL (0x0E) | |
36 | /* Unallocated EC: 0x0F - 0x10 */ | |
37 | #define ESR_ELx_EC_SVC32 (0x11) | |
38 | #define ESR_ELx_EC_HVC32 (0x12) | |
39 | #define ESR_ELx_EC_SMC32 (0x13) | |
40 | /* Unallocated EC: 0x14 */ | |
41 | #define ESR_ELx_EC_SVC64 (0x15) | |
42 | #define ESR_ELx_EC_HVC64 (0x16) | |
43 | #define ESR_ELx_EC_SMC64 (0x17) | |
44 | #define ESR_ELx_EC_SYS64 (0x18) | |
45 | /* Unallocated EC: 0x19 - 0x1E */ | |
46 | #define ESR_ELx_EC_IMP_DEF (0x1f) | |
47 | #define ESR_ELx_EC_IABT_LOW (0x20) | |
48 | #define ESR_ELx_EC_IABT_CUR (0x21) | |
49 | #define ESR_ELx_EC_PC_ALIGN (0x22) | |
50 | /* Unallocated EC: 0x23 */ | |
51 | #define ESR_ELx_EC_DABT_LOW (0x24) | |
52 | #define ESR_ELx_EC_DABT_CUR (0x25) | |
53 | #define ESR_ELx_EC_SP_ALIGN (0x26) | |
54 | /* Unallocated EC: 0x27 */ | |
55 | #define ESR_ELx_EC_FP_EXC32 (0x28) | |
56 | /* Unallocated EC: 0x29 - 0x2B */ | |
57 | #define ESR_ELx_EC_FP_EXC64 (0x2C) | |
58 | /* Unallocated EC: 0x2D - 0x2E */ | |
59 | #define ESR_ELx_EC_SERROR (0x2F) | |
60 | #define ESR_ELx_EC_BREAKPT_LOW (0x30) | |
61 | #define ESR_ELx_EC_BREAKPT_CUR (0x31) | |
62 | #define ESR_ELx_EC_SOFTSTP_LOW (0x32) | |
63 | #define ESR_ELx_EC_SOFTSTP_CUR (0x33) | |
64 | #define ESR_ELx_EC_WATCHPT_LOW (0x34) | |
65 | #define ESR_ELx_EC_WATCHPT_CUR (0x35) | |
66 | /* Unallocated EC: 0x36 - 0x37 */ | |
67 | #define ESR_ELx_EC_BKPT32 (0x38) | |
68 | /* Unallocated EC: 0x39 */ | |
69 | #define ESR_ELx_EC_VECTOR32 (0x3A) | |
70 | /* Unallocted EC: 0x3B */ | |
71 | #define ESR_ELx_EC_BRK64 (0x3C) | |
72 | /* Unallocated EC: 0x3D - 0x3F */ | |
73 | #define ESR_ELx_EC_MAX (0x3F) | |
74 | ||
75 | #define ESR_ELx_EC_SHIFT (26) | |
76 | #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT) | |
275f344b | 77 | #define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) |
cf99a48d MR |
78 | |
79 | #define ESR_ELx_IL (UL(1) << 25) | |
80 | #define ESR_ELx_ISS_MASK (ESR_ELx_IL - 1) | |
9dbd5bb2 SP |
81 | |
82 | /* ISS field definitions shared by different classes */ | |
83 | #define ESR_ELx_WNR (UL(1) << 6) | |
84 | ||
85 | /* Shared ISS field definitions for Data/Instruction aborts */ | |
86 | #define ESR_ELx_EA (UL(1) << 9) | |
87 | #define ESR_ELx_S1PTW (UL(1) << 7) | |
88 | ||
89 | /* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */ | |
90 | #define ESR_ELx_FSC (0x3F) | |
91 | #define ESR_ELx_FSC_TYPE (0x3C) | |
92 | #define ESR_ELx_FSC_EXTABT (0x10) | |
93 | #define ESR_ELx_FSC_ACCESS (0x08) | |
94 | #define ESR_ELx_FSC_FAULT (0x04) | |
95 | #define ESR_ELx_FSC_PERM (0x0C) | |
96 | ||
97 | /* ISS field definitions for Data Aborts */ | |
cf99a48d MR |
98 | #define ESR_ELx_ISV (UL(1) << 24) |
99 | #define ESR_ELx_SAS_SHIFT (22) | |
100 | #define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT) | |
101 | #define ESR_ELx_SSE (UL(1) << 21) | |
102 | #define ESR_ELx_SRT_SHIFT (16) | |
103 | #define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT) | |
104 | #define ESR_ELx_SF (UL(1) << 15) | |
105 | #define ESR_ELx_AR (UL(1) << 14) | |
cf99a48d | 106 | #define ESR_ELx_CM (UL(1) << 8) |
9dbd5bb2 SP |
107 | |
108 | /* ISS field definitions for exceptions taken in to Hyp */ | |
cf99a48d MR |
109 | #define ESR_ELx_CV (UL(1) << 24) |
110 | #define ESR_ELx_COND_SHIFT (20) | |
111 | #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT) | |
112 | #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0) | |
1c6007d5 | 113 | #define ESR_ELx_xVC_IMM_MASK ((1UL << 16) - 1) |
cf99a48d | 114 | |
72d033e8 DM |
115 | /* ESR value templates for specific events */ |
116 | ||
117 | /* BRK instruction trap from AArch64 state */ | |
118 | #define ESR_ELx_VAL_BRK64(imm) \ | |
119 | ((ESR_ELx_EC_BRK64 << ESR_ELx_EC_SHIFT) | ESR_ELx_IL | \ | |
120 | ((imm) & 0xffff)) | |
121 | ||
9dbd5bb2 SP |
122 | /* ISS field definitions for System instruction traps */ |
123 | #define ESR_ELx_SYS64_ISS_RES0_SHIFT 22 | |
124 | #define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT) | |
125 | #define ESR_ELx_SYS64_ISS_DIR_MASK 0x1 | |
126 | #define ESR_ELx_SYS64_ISS_DIR_READ 0x1 | |
127 | #define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0 | |
128 | ||
129 | #define ESR_ELx_SYS64_ISS_RT_SHIFT 5 | |
130 | #define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT) | |
131 | #define ESR_ELx_SYS64_ISS_CRM_SHIFT 1 | |
132 | #define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT) | |
133 | #define ESR_ELx_SYS64_ISS_CRN_SHIFT 10 | |
134 | #define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | |
135 | #define ESR_ELx_SYS64_ISS_OP1_SHIFT 14 | |
136 | #define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | |
137 | #define ESR_ELx_SYS64_ISS_OP2_SHIFT 17 | |
138 | #define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | |
139 | #define ESR_ELx_SYS64_ISS_OP0_SHIFT 20 | |
140 | #define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | |
141 | #define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ | |
142 | ESR_ELx_SYS64_ISS_OP1_MASK | \ | |
143 | ESR_ELx_SYS64_ISS_OP2_MASK | \ | |
144 | ESR_ELx_SYS64_ISS_CRN_MASK | \ | |
145 | ESR_ELx_SYS64_ISS_CRM_MASK) | |
146 | #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \ | |
147 | (((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \ | |
148 | ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \ | |
149 | ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \ | |
150 | ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \ | |
151 | ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT)) | |
116c81f4 SP |
152 | |
153 | #define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \ | |
154 | ESR_ELx_SYS64_ISS_DIR_MASK) | |
9dbd5bb2 SP |
155 | /* |
156 | * User space cache operations have the following sysreg encoding | |
157 | * in System instructions. | |
158 | * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 14 }, WRITE (L=0) | |
159 | */ | |
160 | #define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14 | |
161 | #define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11 | |
162 | #define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10 | |
163 | #define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5 | |
164 | ||
165 | #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ | |
166 | ESR_ELx_SYS64_ISS_OP1_MASK | \ | |
167 | ESR_ELx_SYS64_ISS_OP2_MASK | \ | |
168 | ESR_ELx_SYS64_ISS_CRN_MASK | \ | |
169 | ESR_ELx_SYS64_ISS_DIR_MASK) | |
170 | #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \ | |
171 | (ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \ | |
172 | ESR_ELx_SYS64_ISS_DIR_WRITE) | |
116c81f4 SP |
173 | |
174 | #define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0) | |
175 | #define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \ | |
176 | ESR_ELx_SYS64_ISS_DIR_READ) | |
177 | ||
6126ce05 MZ |
178 | #define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \ |
179 | ESR_ELx_SYS64_ISS_DIR_READ) | |
9842119a MZ |
180 | |
181 | #define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \ | |
182 | ESR_ELx_SYS64_ISS_DIR_READ) | |
183 | ||
60a1f02c MR |
184 | #ifndef __ASSEMBLY__ |
185 | #include <asm/types.h> | |
186 | ||
187 | const char *esr_get_class_string(u32 esr); | |
188 | #endif /* __ASSEMBLY */ | |
189 | ||
5c1ce6f7 | 190 | #endif /* __ASM_ESR_H */ |