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5c1ce6f7 MZ |
1 | /* |
2 | * Copyright (C) 2013 - ARM Ltd | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #ifndef __ASM_ESR_H | |
19 | #define __ASM_ESR_H | |
20 | ||
d7a33f4f | 21 | #include <asm/memory.h> |
d251f67a | 22 | #include <asm/sysreg.h> |
d7a33f4f | 23 | |
cf99a48d MR |
24 | #define ESR_ELx_EC_UNKNOWN (0x00) |
25 | #define ESR_ELx_EC_WFx (0x01) | |
26 | /* Unallocated EC: 0x02 */ | |
27 | #define ESR_ELx_EC_CP15_32 (0x03) | |
28 | #define ESR_ELx_EC_CP15_64 (0x04) | |
29 | #define ESR_ELx_EC_CP14_MR (0x05) | |
30 | #define ESR_ELx_EC_CP14_LS (0x06) | |
31 | #define ESR_ELx_EC_FP_ASIMD (0x07) | |
32 | #define ESR_ELx_EC_CP10_ID (0x08) | |
33 | /* Unallocated EC: 0x09 - 0x0B */ | |
34 | #define ESR_ELx_EC_CP14_64 (0x0C) | |
35 | /* Unallocated EC: 0x0d */ | |
36 | #define ESR_ELx_EC_ILL (0x0E) | |
37 | /* Unallocated EC: 0x0F - 0x10 */ | |
38 | #define ESR_ELx_EC_SVC32 (0x11) | |
39 | #define ESR_ELx_EC_HVC32 (0x12) | |
40 | #define ESR_ELx_EC_SMC32 (0x13) | |
41 | /* Unallocated EC: 0x14 */ | |
42 | #define ESR_ELx_EC_SVC64 (0x15) | |
43 | #define ESR_ELx_EC_HVC64 (0x16) | |
44 | #define ESR_ELx_EC_SMC64 (0x17) | |
45 | #define ESR_ELx_EC_SYS64 (0x18) | |
67236564 DM |
46 | #define ESR_ELx_EC_SVE (0x19) |
47 | /* Unallocated EC: 0x1A - 0x1E */ | |
cf99a48d MR |
48 | #define ESR_ELx_EC_IMP_DEF (0x1f) |
49 | #define ESR_ELx_EC_IABT_LOW (0x20) | |
50 | #define ESR_ELx_EC_IABT_CUR (0x21) | |
51 | #define ESR_ELx_EC_PC_ALIGN (0x22) | |
52 | /* Unallocated EC: 0x23 */ | |
53 | #define ESR_ELx_EC_DABT_LOW (0x24) | |
54 | #define ESR_ELx_EC_DABT_CUR (0x25) | |
55 | #define ESR_ELx_EC_SP_ALIGN (0x26) | |
56 | /* Unallocated EC: 0x27 */ | |
57 | #define ESR_ELx_EC_FP_EXC32 (0x28) | |
58 | /* Unallocated EC: 0x29 - 0x2B */ | |
59 | #define ESR_ELx_EC_FP_EXC64 (0x2C) | |
60 | /* Unallocated EC: 0x2D - 0x2E */ | |
61 | #define ESR_ELx_EC_SERROR (0x2F) | |
62 | #define ESR_ELx_EC_BREAKPT_LOW (0x30) | |
63 | #define ESR_ELx_EC_BREAKPT_CUR (0x31) | |
64 | #define ESR_ELx_EC_SOFTSTP_LOW (0x32) | |
65 | #define ESR_ELx_EC_SOFTSTP_CUR (0x33) | |
66 | #define ESR_ELx_EC_WATCHPT_LOW (0x34) | |
67 | #define ESR_ELx_EC_WATCHPT_CUR (0x35) | |
68 | /* Unallocated EC: 0x36 - 0x37 */ | |
69 | #define ESR_ELx_EC_BKPT32 (0x38) | |
70 | /* Unallocated EC: 0x39 */ | |
71 | #define ESR_ELx_EC_VECTOR32 (0x3A) | |
72 | /* Unallocted EC: 0x3B */ | |
73 | #define ESR_ELx_EC_BRK64 (0x3C) | |
74 | /* Unallocated EC: 0x3D - 0x3F */ | |
75 | #define ESR_ELx_EC_MAX (0x3F) | |
76 | ||
77 | #define ESR_ELx_EC_SHIFT (26) | |
78 | #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT) | |
275f344b | 79 | #define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) |
cf99a48d | 80 | |
1f9b8936 JT |
81 | #define ESR_ELx_IL_SHIFT (25) |
82 | #define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT) | |
cf99a48d | 83 | #define ESR_ELx_ISS_MASK (ESR_ELx_IL - 1) |
9dbd5bb2 SP |
84 | |
85 | /* ISS field definitions shared by different classes */ | |
1f9b8936 JT |
86 | #define ESR_ELx_WNR_SHIFT (6) |
87 | #define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT) | |
9dbd5bb2 | 88 | |
acf161a3 JM |
89 | /* Asynchronous Error Type */ |
90 | #define ESR_ELx_IDS_SHIFT (24) | |
91 | #define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT) | |
92 | #define ESR_ELx_AET_SHIFT (10) | |
93 | #define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT) | |
94 | ||
95 | #define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT) | |
96 | #define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT) | |
97 | #define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT) | |
98 | #define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT) | |
99 | #define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT) | |
100 | ||
9dbd5bb2 | 101 | /* Shared ISS field definitions for Data/Instruction aborts */ |
1f9b8936 JT |
102 | #define ESR_ELx_SET_SHIFT (11) |
103 | #define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT) | |
104 | #define ESR_ELx_FnV_SHIFT (10) | |
105 | #define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT) | |
106 | #define ESR_ELx_EA_SHIFT (9) | |
107 | #define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT) | |
108 | #define ESR_ELx_S1PTW_SHIFT (7) | |
109 | #define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT) | |
9dbd5bb2 SP |
110 | |
111 | /* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */ | |
112 | #define ESR_ELx_FSC (0x3F) | |
113 | #define ESR_ELx_FSC_TYPE (0x3C) | |
114 | #define ESR_ELx_FSC_EXTABT (0x10) | |
acf161a3 | 115 | #define ESR_ELx_FSC_SERROR (0x11) |
9dbd5bb2 SP |
116 | #define ESR_ELx_FSC_ACCESS (0x08) |
117 | #define ESR_ELx_FSC_FAULT (0x04) | |
118 | #define ESR_ELx_FSC_PERM (0x0C) | |
119 | ||
120 | /* ISS field definitions for Data Aborts */ | |
1f9b8936 JT |
121 | #define ESR_ELx_ISV_SHIFT (24) |
122 | #define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT) | |
cf99a48d MR |
123 | #define ESR_ELx_SAS_SHIFT (22) |
124 | #define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT) | |
1f9b8936 JT |
125 | #define ESR_ELx_SSE_SHIFT (21) |
126 | #define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT) | |
cf99a48d MR |
127 | #define ESR_ELx_SRT_SHIFT (16) |
128 | #define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT) | |
1f9b8936 JT |
129 | #define ESR_ELx_SF_SHIFT (15) |
130 | #define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT) | |
131 | #define ESR_ELx_AR_SHIFT (14) | |
132 | #define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT) | |
133 | #define ESR_ELx_CM_SHIFT (8) | |
134 | #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT) | |
9dbd5bb2 SP |
135 | |
136 | /* ISS field definitions for exceptions taken in to Hyp */ | |
cf99a48d MR |
137 | #define ESR_ELx_CV (UL(1) << 24) |
138 | #define ESR_ELx_COND_SHIFT (20) | |
139 | #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT) | |
140 | #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0) | |
1c6007d5 | 141 | #define ESR_ELx_xVC_IMM_MASK ((1UL << 16) - 1) |
cf99a48d | 142 | |
47be510b JM |
143 | #define DISR_EL1_IDS (UL(1) << 24) |
144 | /* | |
145 | * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean | |
146 | * different things in the future... | |
147 | */ | |
148 | #define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC) | |
149 | ||
72d033e8 DM |
150 | /* ESR value templates for specific events */ |
151 | ||
152 | /* BRK instruction trap from AArch64 state */ | |
153 | #define ESR_ELx_VAL_BRK64(imm) \ | |
154 | ((ESR_ELx_EC_BRK64 << ESR_ELx_EC_SHIFT) | ESR_ELx_IL | \ | |
155 | ((imm) & 0xffff)) | |
156 | ||
9dbd5bb2 SP |
157 | /* ISS field definitions for System instruction traps */ |
158 | #define ESR_ELx_SYS64_ISS_RES0_SHIFT 22 | |
159 | #define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT) | |
160 | #define ESR_ELx_SYS64_ISS_DIR_MASK 0x1 | |
161 | #define ESR_ELx_SYS64_ISS_DIR_READ 0x1 | |
162 | #define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0 | |
163 | ||
164 | #define ESR_ELx_SYS64_ISS_RT_SHIFT 5 | |
165 | #define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT) | |
166 | #define ESR_ELx_SYS64_ISS_CRM_SHIFT 1 | |
167 | #define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT) | |
168 | #define ESR_ELx_SYS64_ISS_CRN_SHIFT 10 | |
169 | #define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | |
170 | #define ESR_ELx_SYS64_ISS_OP1_SHIFT 14 | |
171 | #define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | |
172 | #define ESR_ELx_SYS64_ISS_OP2_SHIFT 17 | |
173 | #define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | |
174 | #define ESR_ELx_SYS64_ISS_OP0_SHIFT 20 | |
175 | #define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | |
176 | #define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ | |
177 | ESR_ELx_SYS64_ISS_OP1_MASK | \ | |
178 | ESR_ELx_SYS64_ISS_OP2_MASK | \ | |
179 | ESR_ELx_SYS64_ISS_CRN_MASK | \ | |
180 | ESR_ELx_SYS64_ISS_CRM_MASK) | |
181 | #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \ | |
182 | (((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \ | |
183 | ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \ | |
184 | ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \ | |
185 | ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \ | |
186 | ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT)) | |
116c81f4 SP |
187 | |
188 | #define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \ | |
189 | ESR_ELx_SYS64_ISS_DIR_MASK) | |
9dbd5bb2 SP |
190 | /* |
191 | * User space cache operations have the following sysreg encoding | |
192 | * in System instructions. | |
e1bc5d1b | 193 | * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 14 }, WRITE (L=0) |
9dbd5bb2 SP |
194 | */ |
195 | #define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14 | |
e1bc5d1b | 196 | #define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12 |
9dbd5bb2 SP |
197 | #define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11 |
198 | #define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10 | |
199 | #define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5 | |
200 | ||
201 | #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ | |
202 | ESR_ELx_SYS64_ISS_OP1_MASK | \ | |
203 | ESR_ELx_SYS64_ISS_OP2_MASK | \ | |
204 | ESR_ELx_SYS64_ISS_CRN_MASK | \ | |
205 | ESR_ELx_SYS64_ISS_DIR_MASK) | |
206 | #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \ | |
207 | (ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \ | |
208 | ESR_ELx_SYS64_ISS_DIR_WRITE) | |
116c81f4 SP |
209 | |
210 | #define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0) | |
211 | #define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \ | |
212 | ESR_ELx_SYS64_ISS_DIR_READ) | |
213 | ||
6126ce05 MZ |
214 | #define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \ |
215 | ESR_ELx_SYS64_ISS_DIR_READ) | |
9842119a MZ |
216 | |
217 | #define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \ | |
218 | ESR_ELx_SYS64_ISS_DIR_READ) | |
219 | ||
d251f67a MZ |
220 | #define esr_sys64_to_sysreg(e) \ |
221 | sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \ | |
222 | ESR_ELx_SYS64_ISS_OP0_SHIFT), \ | |
223 | (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ | |
224 | ESR_ELx_SYS64_ISS_OP1_SHIFT), \ | |
225 | (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ | |
226 | ESR_ELx_SYS64_ISS_CRN_SHIFT), \ | |
227 | (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ | |
228 | ESR_ELx_SYS64_ISS_CRM_SHIFT), \ | |
229 | (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ | |
230 | ESR_ELx_SYS64_ISS_OP2_SHIFT)) | |
231 | ||
232 | #define esr_cp15_to_sysreg(e) \ | |
233 | sys_reg(3, \ | |
234 | (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ | |
235 | ESR_ELx_SYS64_ISS_OP1_SHIFT), \ | |
236 | (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ | |
237 | ESR_ELx_SYS64_ISS_CRN_SHIFT), \ | |
238 | (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ | |
239 | ESR_ELx_SYS64_ISS_CRM_SHIFT), \ | |
240 | (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ | |
241 | ESR_ELx_SYS64_ISS_OP2_SHIFT)) | |
242 | ||
60a1f02c MR |
243 | #ifndef __ASSEMBLY__ |
244 | #include <asm/types.h> | |
245 | ||
1f9b8936 JT |
246 | static inline bool esr_is_data_abort(u32 esr) |
247 | { | |
248 | const u32 ec = ESR_ELx_EC(esr); | |
249 | ||
250 | return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR; | |
251 | } | |
252 | ||
60a1f02c MR |
253 | const char *esr_get_class_string(u32 esr); |
254 | #endif /* __ASSEMBLY */ | |
255 | ||
5c1ce6f7 | 256 | #endif /* __ASM_ESR_H */ |