[mirror_ubuntu-jammy-kernel.git] / arch / arm64 / include / asm / insn.h

/*
 * Copyright (C) 2013 Huawei Ltd.
 * Author: Jiang Liu <liuj97@gmail.com>
 *
 * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef	__ASM_INSN_H
#define	__ASM_INSN_H
#include <linux/build_bug.h>
#include <linux/types.h>

/* A64 instructions are always 32 bits. */
#define	AARCH64_INSN_SIZE		4

#ifndef __ASSEMBLY__
/*
 * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
 * Section C3.1 "A64 instruction index by encoding":
 * AArch64 main encoding table
 *  Bit position
 *   28 27 26 25	Encoding Group
 *   0  0  -  -		Unallocated
 *   1  0  0  -		Data processing, immediate
 *   1  0  1  -		Branch, exception generation and system instructions
 *   -  1  -  0		Loads and stores
 *   -  1  0  1		Data processing - register
 *   0  1  1  1		Data processing - SIMD and floating point
 *   1  1  1  1		Data processing - SIMD and floating point
 * "-" means "don't care"
 */
enum aarch64_insn_encoding_class {
	AARCH64_INSN_CLS_UNKNOWN,	/* UNALLOCATED */
	AARCH64_INSN_CLS_DP_IMM,	/* Data processing - immediate */
	AARCH64_INSN_CLS_DP_REG,	/* Data processing - register */
	AARCH64_INSN_CLS_DP_FPSIMD,	/* Data processing - SIMD and FP */
	AARCH64_INSN_CLS_LDST,		/* Loads and stores */
	AARCH64_INSN_CLS_BR_SYS,	/* Branch, exception generation and
					 * system instructions */
};

enum aarch64_insn_hint_op {
	AARCH64_INSN_HINT_NOP	= 0x0 << 5,
	AARCH64_INSN_HINT_YIELD	= 0x1 << 5,
	AARCH64_INSN_HINT_WFE	= 0x2 << 5,
	AARCH64_INSN_HINT_WFI	= 0x3 << 5,
	AARCH64_INSN_HINT_SEV	= 0x4 << 5,
	AARCH64_INSN_HINT_SEVL	= 0x5 << 5,
};

enum aarch64_insn_imm_type {
	AARCH64_INSN_IMM_ADR,
	AARCH64_INSN_IMM_26,
	AARCH64_INSN_IMM_19,
	AARCH64_INSN_IMM_16,
	AARCH64_INSN_IMM_14,
	AARCH64_INSN_IMM_12,
	AARCH64_INSN_IMM_9,
	AARCH64_INSN_IMM_7,
	AARCH64_INSN_IMM_6,
	AARCH64_INSN_IMM_S,
	AARCH64_INSN_IMM_R,
	AARCH64_INSN_IMM_N,
	AARCH64_INSN_IMM_MAX
};

enum aarch64_insn_register_type {
	AARCH64_INSN_REGTYPE_RT,
	AARCH64_INSN_REGTYPE_RN,
	AARCH64_INSN_REGTYPE_RT2,
	AARCH64_INSN_REGTYPE_RM,
	AARCH64_INSN_REGTYPE_RD,
	AARCH64_INSN_REGTYPE_RA,
	AARCH64_INSN_REGTYPE_RS,
};

enum aarch64_insn_register {
	AARCH64_INSN_REG_0  = 0,
	AARCH64_INSN_REG_1  = 1,
	AARCH64_INSN_REG_2  = 2,
	AARCH64_INSN_REG_3  = 3,
	AARCH64_INSN_REG_4  = 4,
	AARCH64_INSN_REG_5  = 5,
	AARCH64_INSN_REG_6  = 6,
	AARCH64_INSN_REG_7  = 7,
	AARCH64_INSN_REG_8  = 8,
	AARCH64_INSN_REG_9  = 9,
	AARCH64_INSN_REG_10 = 10,
	AARCH64_INSN_REG_11 = 11,
	AARCH64_INSN_REG_12 = 12,
	AARCH64_INSN_REG_13 = 13,
	AARCH64_INSN_REG_14 = 14,
	AARCH64_INSN_REG_15 = 15,
	AARCH64_INSN_REG_16 = 16,
	AARCH64_INSN_REG_17 = 17,
	AARCH64_INSN_REG_18 = 18,
	AARCH64_INSN_REG_19 = 19,
	AARCH64_INSN_REG_20 = 20,
	AARCH64_INSN_REG_21 = 21,
	AARCH64_INSN_REG_22 = 22,
	AARCH64_INSN_REG_23 = 23,
	AARCH64_INSN_REG_24 = 24,
	AARCH64_INSN_REG_25 = 25,
	AARCH64_INSN_REG_26 = 26,
	AARCH64_INSN_REG_27 = 27,
	AARCH64_INSN_REG_28 = 28,
	AARCH64_INSN_REG_29 = 29,
	AARCH64_INSN_REG_FP = 29, /* Frame pointer */
	AARCH64_INSN_REG_30 = 30,
	AARCH64_INSN_REG_LR = 30, /* Link register */
	AARCH64_INSN_REG_ZR = 31, /* Zero: as source register */
	AARCH64_INSN_REG_SP = 31  /* Stack pointer: as load/store base reg */
};

enum aarch64_insn_special_register {
	AARCH64_INSN_SPCLREG_SPSR_EL1	= 0xC200,
	AARCH64_INSN_SPCLREG_ELR_EL1	= 0xC201,
	AARCH64_INSN_SPCLREG_SP_EL0	= 0xC208,
	AARCH64_INSN_SPCLREG_SPSEL	= 0xC210,
	AARCH64_INSN_SPCLREG_CURRENTEL	= 0xC212,
	AARCH64_INSN_SPCLREG_DAIF	= 0xDA11,
	AARCH64_INSN_SPCLREG_NZCV	= 0xDA10,
	AARCH64_INSN_SPCLREG_FPCR	= 0xDA20,
	AARCH64_INSN_SPCLREG_DSPSR_EL0	= 0xDA28,
	AARCH64_INSN_SPCLREG_DLR_EL0	= 0xDA29,
	AARCH64_INSN_SPCLREG_SPSR_EL2	= 0xE200,
	AARCH64_INSN_SPCLREG_ELR_EL2	= 0xE201,
	AARCH64_INSN_SPCLREG_SP_EL1	= 0xE208,
	AARCH64_INSN_SPCLREG_SPSR_INQ	= 0xE218,
	AARCH64_INSN_SPCLREG_SPSR_ABT	= 0xE219,
	AARCH64_INSN_SPCLREG_SPSR_UND	= 0xE21A,
	AARCH64_INSN_SPCLREG_SPSR_FIQ	= 0xE21B,
	AARCH64_INSN_SPCLREG_SPSR_EL3	= 0xF200,
	AARCH64_INSN_SPCLREG_ELR_EL3	= 0xF201,
	AARCH64_INSN_SPCLREG_SP_EL2	= 0xF210
};

enum aarch64_insn_variant {
	AARCH64_INSN_VARIANT_32BIT,
	AARCH64_INSN_VARIANT_64BIT
};

enum aarch64_insn_condition {
	AARCH64_INSN_COND_EQ = 0x0, /* == */
	AARCH64_INSN_COND_NE = 0x1, /* != */
	AARCH64_INSN_COND_CS = 0x2, /* unsigned >= */
	AARCH64_INSN_COND_CC = 0x3, /* unsigned < */
	AARCH64_INSN_COND_MI = 0x4, /* < 0 */
	AARCH64_INSN_COND_PL = 0x5, /* >= 0 */
	AARCH64_INSN_COND_VS = 0x6, /* overflow */
	AARCH64_INSN_COND_VC = 0x7, /* no overflow */
	AARCH64_INSN_COND_HI = 0x8, /* unsigned > */
	AARCH64_INSN_COND_LS = 0x9, /* unsigned <= */
	AARCH64_INSN_COND_GE = 0xa, /* signed >= */
	AARCH64_INSN_COND_LT = 0xb, /* signed < */
	AARCH64_INSN_COND_GT = 0xc, /* signed > */
	AARCH64_INSN_COND_LE = 0xd, /* signed <= */
	AARCH64_INSN_COND_AL = 0xe, /* always */
};

enum aarch64_insn_branch_type {
	AARCH64_INSN_BRANCH_NOLINK,
	AARCH64_INSN_BRANCH_LINK,
	AARCH64_INSN_BRANCH_RETURN,
	AARCH64_INSN_BRANCH_COMP_ZERO,
	AARCH64_INSN_BRANCH_COMP_NONZERO,
};

enum aarch64_insn_size_type {
	AARCH64_INSN_SIZE_8,
	AARCH64_INSN_SIZE_16,
	AARCH64_INSN_SIZE_32,
	AARCH64_INSN_SIZE_64,
};

enum aarch64_insn_ldst_type {
	AARCH64_INSN_LDST_LOAD_REG_OFFSET,
	AARCH64_INSN_LDST_STORE_REG_OFFSET,
	AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX,
	AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX,
	AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX,
	AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX,
	AARCH64_INSN_LDST_LOAD_EX,
	AARCH64_INSN_LDST_STORE_EX,
};

enum aarch64_insn_adsb_type {
	AARCH64_INSN_ADSB_ADD,
	AARCH64_INSN_ADSB_SUB,
	AARCH64_INSN_ADSB_ADD_SETFLAGS,
	AARCH64_INSN_ADSB_SUB_SETFLAGS
};

enum aarch64_insn_movewide_type {
	AARCH64_INSN_MOVEWIDE_ZERO,
	AARCH64_INSN_MOVEWIDE_KEEP,
	AARCH64_INSN_MOVEWIDE_INVERSE
};

enum aarch64_insn_bitfield_type {
	AARCH64_INSN_BITFIELD_MOVE,
	AARCH64_INSN_BITFIELD_MOVE_UNSIGNED,
	AARCH64_INSN_BITFIELD_MOVE_SIGNED
};

enum aarch64_insn_data1_type {
	AARCH64_INSN_DATA1_REVERSE_16,
	AARCH64_INSN_DATA1_REVERSE_32,
	AARCH64_INSN_DATA1_REVERSE_64,
};

enum aarch64_insn_data2_type {
	AARCH64_INSN_DATA2_UDIV,
	AARCH64_INSN_DATA2_SDIV,
	AARCH64_INSN_DATA2_LSLV,
	AARCH64_INSN_DATA2_LSRV,
	AARCH64_INSN_DATA2_ASRV,
	AARCH64_INSN_DATA2_RORV,
};

enum aarch64_insn_data3_type {
	AARCH64_INSN_DATA3_MADD,
	AARCH64_INSN_DATA3_MSUB,
};

enum aarch64_insn_logic_type {
	AARCH64_INSN_LOGIC_AND,
	AARCH64_INSN_LOGIC_BIC,
	AARCH64_INSN_LOGIC_ORR,
	AARCH64_INSN_LOGIC_ORN,
	AARCH64_INSN_LOGIC_EOR,
	AARCH64_INSN_LOGIC_EON,
	AARCH64_INSN_LOGIC_AND_SETFLAGS,
	AARCH64_INSN_LOGIC_BIC_SETFLAGS
};

enum aarch64_insn_prfm_type {
	AARCH64_INSN_PRFM_TYPE_PLD,
	AARCH64_INSN_PRFM_TYPE_PLI,
	AARCH64_INSN_PRFM_TYPE_PST,
};

enum aarch64_insn_prfm_target {
	AARCH64_INSN_PRFM_TARGET_L1,
	AARCH64_INSN_PRFM_TARGET_L2,
	AARCH64_INSN_PRFM_TARGET_L3,
};

enum aarch64_insn_prfm_policy {
	AARCH64_INSN_PRFM_POLICY_KEEP,
	AARCH64_INSN_PRFM_POLICY_STRM,
};

enum aarch64_insn_adr_type {
	AARCH64_INSN_ADR_TYPE_ADRP,
	AARCH64_INSN_ADR_TYPE_ADR,
};

#define	__AARCH64_INSN_FUNCS(abbr, mask, val)				\
static __always_inline bool aarch64_insn_is_##abbr(u32 code)		\
{									\
	BUILD_BUG_ON(~(mask) & (val));					\
	return (code & (mask)) == (val);				\
}									\
static __always_inline u32 aarch64_insn_get_##abbr##_value(void)	\
{									\
	return (val);							\
}

__AARCH64_INSN_FUNCS(adr,	0x9F000000, 0x10000000)
__AARCH64_INSN_FUNCS(adrp,	0x9F000000, 0x90000000)
__AARCH64_INSN_FUNCS(prfm,	0x3FC00000, 0x39800000)
__AARCH64_INSN_FUNCS(prfm_lit,	0xFF000000, 0xD8000000)
__AARCH64_INSN_FUNCS(str_reg,	0x3FE0EC00, 0x38206800)
__AARCH64_INSN_FUNCS(ldadd,	0x3F20FC00, 0x38200000)
__AARCH64_INSN_FUNCS(ldr_reg,	0x3FE0EC00, 0x38606800)
__AARCH64_INSN_FUNCS(ldr_lit,	0xBF000000, 0x18000000)
__AARCH64_INSN_FUNCS(ldrsw_lit,	0xFF000000, 0x98000000)
__AARCH64_INSN_FUNCS(exclusive,	0x3F800000, 0x08000000)
__AARCH64_INSN_FUNCS(load_ex,	0x3F400000, 0x08400000)
__AARCH64_INSN_FUNCS(store_ex,	0x3F400000, 0x08000000)
__AARCH64_INSN_FUNCS(stp_post,	0x7FC00000, 0x28800000)
__AARCH64_INSN_FUNCS(ldp_post,	0x7FC00000, 0x28C00000)
__AARCH64_INSN_FUNCS(stp_pre,	0x7FC00000, 0x29800000)
__AARCH64_INSN_FUNCS(ldp_pre,	0x7FC00000, 0x29C00000)
__AARCH64_INSN_FUNCS(add_imm,	0x7F000000, 0x11000000)
__AARCH64_INSN_FUNCS(adds_imm,	0x7F000000, 0x31000000)
__AARCH64_INSN_FUNCS(sub_imm,	0x7F000000, 0x51000000)
__AARCH64_INSN_FUNCS(subs_imm,	0x7F000000, 0x71000000)
__AARCH64_INSN_FUNCS(movn,	0x7F800000, 0x12800000)
__AARCH64_INSN_FUNCS(sbfm,	0x7F800000, 0x13000000)
__AARCH64_INSN_FUNCS(bfm,	0x7F800000, 0x33000000)
__AARCH64_INSN_FUNCS(movz,	0x7F800000, 0x52800000)
__AARCH64_INSN_FUNCS(ubfm,	0x7F800000, 0x53000000)
__AARCH64_INSN_FUNCS(movk,	0x7F800000, 0x72800000)
__AARCH64_INSN_FUNCS(add,	0x7F200000, 0x0B000000)
__AARCH64_INSN_FUNCS(adds,	0x7F200000, 0x2B000000)
__AARCH64_INSN_FUNCS(sub,	0x7F200000, 0x4B000000)
__AARCH64_INSN_FUNCS(subs,	0x7F200000, 0x6B000000)
__AARCH64_INSN_FUNCS(madd,	0x7FE08000, 0x1B000000)
__AARCH64_INSN_FUNCS(msub,	0x7FE08000, 0x1B008000)
__AARCH64_INSN_FUNCS(udiv,	0x7FE0FC00, 0x1AC00800)
__AARCH64_INSN_FUNCS(sdiv,	0x7FE0FC00, 0x1AC00C00)
__AARCH64_INSN_FUNCS(lslv,	0x7FE0FC00, 0x1AC02000)
__AARCH64_INSN_FUNCS(lsrv,	0x7FE0FC00, 0x1AC02400)
__AARCH64_INSN_FUNCS(asrv,	0x7FE0FC00, 0x1AC02800)
__AARCH64_INSN_FUNCS(rorv,	0x7FE0FC00, 0x1AC02C00)
__AARCH64_INSN_FUNCS(rev16,	0x7FFFFC00, 0x5AC00400)
__AARCH64_INSN_FUNCS(rev32,	0x7FFFFC00, 0x5AC00800)
__AARCH64_INSN_FUNCS(rev64,	0x7FFFFC00, 0x5AC00C00)
__AARCH64_INSN_FUNCS(and,	0x7F200000, 0x0A000000)
__AARCH64_INSN_FUNCS(bic,	0x7F200000, 0x0A200000)
__AARCH64_INSN_FUNCS(orr,	0x7F200000, 0x2A000000)
__AARCH64_INSN_FUNCS(orn,	0x7F200000, 0x2A200000)
__AARCH64_INSN_FUNCS(eor,	0x7F200000, 0x4A000000)
__AARCH64_INSN_FUNCS(eon,	0x7F200000, 0x4A200000)
__AARCH64_INSN_FUNCS(ands,	0x7F200000, 0x6A000000)
__AARCH64_INSN_FUNCS(bics,	0x7F200000, 0x6A200000)
__AARCH64_INSN_FUNCS(and_imm,	0x7F800000, 0x12000000)
__AARCH64_INSN_FUNCS(orr_imm,	0x7F800000, 0x32000000)
__AARCH64_INSN_FUNCS(eor_imm,	0x7F800000, 0x52000000)
__AARCH64_INSN_FUNCS(ands_imm,	0x7F800000, 0x72000000)
__AARCH64_INSN_FUNCS(extr,	0x7FA00000, 0x13800000)
__AARCH64_INSN_FUNCS(b,		0xFC000000, 0x14000000)
__AARCH64_INSN_FUNCS(bl,	0xFC000000, 0x94000000)
__AARCH64_INSN_FUNCS(cbz,	0x7F000000, 0x34000000)
__AARCH64_INSN_FUNCS(cbnz,	0x7F000000, 0x35000000)
__AARCH64_INSN_FUNCS(tbz,	0x7F000000, 0x36000000)
__AARCH64_INSN_FUNCS(tbnz,	0x7F000000, 0x37000000)
__AARCH64_INSN_FUNCS(bcond,	0xFF000010, 0x54000000)
__AARCH64_INSN_FUNCS(svc,	0xFFE0001F, 0xD4000001)
__AARCH64_INSN_FUNCS(hvc,	0xFFE0001F, 0xD4000002)
__AARCH64_INSN_FUNCS(smc,	0xFFE0001F, 0xD4000003)
__AARCH64_INSN_FUNCS(brk,	0xFFE0001F, 0xD4200000)
__AARCH64_INSN_FUNCS(exception,	0xFF000000, 0xD4000000)
__AARCH64_INSN_FUNCS(hint,	0xFFFFF01F, 0xD503201F)
__AARCH64_INSN_FUNCS(br,	0xFFFFFC1F, 0xD61F0000)
__AARCH64_INSN_FUNCS(blr,	0xFFFFFC1F, 0xD63F0000)
__AARCH64_INSN_FUNCS(ret,	0xFFFFFC1F, 0xD65F0000)
__AARCH64_INSN_FUNCS(eret,	0xFFFFFFFF, 0xD69F03E0)
__AARCH64_INSN_FUNCS(mrs,	0xFFF00000, 0xD5300000)
__AARCH64_INSN_FUNCS(msr_imm,	0xFFF8F01F, 0xD500401F)
__AARCH64_INSN_FUNCS(msr_reg,	0xFFF00000, 0xD5100000)

#undef	__AARCH64_INSN_FUNCS

bool aarch64_insn_is_nop(u32 insn);
bool aarch64_insn_is_branch_imm(u32 insn);

static inline bool aarch64_insn_is_adr_adrp(u32 insn)
{
	return aarch64_insn_is_adr(insn) || aarch64_insn_is_adrp(insn);
}

int aarch64_insn_read(void *addr, u32 *insnp);
int aarch64_insn_write(void *addr, u32 insn);
enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn);
bool aarch64_insn_uses_literal(u32 insn);
bool aarch64_insn_is_branch(u32 insn);
u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn);
u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
				  u32 insn, u64 imm);
u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,
					 u32 insn);
u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
				enum aarch64_insn_branch_type type);
u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
				     enum aarch64_insn_register reg,
				     enum aarch64_insn_variant variant,
				     enum aarch64_insn_branch_type type);
u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
				     enum aarch64_insn_condition cond);
u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_op op);
u32 aarch64_insn_gen_nop(void);
u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
				enum aarch64_insn_branch_type type);
u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
				    enum aarch64_insn_register base,
				    enum aarch64_insn_register offset,
				    enum aarch64_insn_size_type size,
				    enum aarch64_insn_ldst_type type);
u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
				     enum aarch64_insn_register reg2,
				     enum aarch64_insn_register base,
				     int offset,
				     enum aarch64_insn_variant variant,
				     enum aarch64_insn_ldst_type type);
u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
				   enum aarch64_insn_register base,
				   enum aarch64_insn_register state,
				   enum aarch64_insn_size_type size,
				   enum aarch64_insn_ldst_type type);
u32 aarch64_insn_gen_ldadd(enum aarch64_insn_register result,
			   enum aarch64_insn_register address,
			   enum aarch64_insn_register value,
			   enum aarch64_insn_size_type size);
u32 aarch64_insn_gen_stadd(enum aarch64_insn_register address,
			   enum aarch64_insn_register value,
			   enum aarch64_insn_size_type size);
u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
				 enum aarch64_insn_register src,
				 int imm, enum aarch64_insn_variant variant,
				 enum aarch64_insn_adsb_type type);
u32 aarch64_insn_gen_adr(unsigned long pc, unsigned long addr,
			 enum aarch64_insn_register reg,
			 enum aarch64_insn_adr_type type);
u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
			      enum aarch64_insn_register src,
			      int immr, int imms,
			      enum aarch64_insn_variant variant,
			      enum aarch64_insn_bitfield_type type);
u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
			      int imm, int shift,
			      enum aarch64_insn_variant variant,
			      enum aarch64_insn_movewide_type type);
u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
					 enum aarch64_insn_register src,
					 enum aarch64_insn_register reg,
					 int shift,
					 enum aarch64_insn_variant variant,
					 enum aarch64_insn_adsb_type type);
u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
			   enum aarch64_insn_register src,
			   enum aarch64_insn_variant variant,
			   enum aarch64_insn_data1_type type);
u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
			   enum aarch64_insn_register src,
			   enum aarch64_insn_register reg,
			   enum aarch64_insn_variant variant,
			   enum aarch64_insn_data2_type type);
u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
			   enum aarch64_insn_register src,
			   enum aarch64_insn_register reg1,
			   enum aarch64_insn_register reg2,
			   enum aarch64_insn_variant variant,
			   enum aarch64_insn_data3_type type);
u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
					 enum aarch64_insn_register src,
					 enum aarch64_insn_register reg,
					 int shift,
					 enum aarch64_insn_variant variant,
					 enum aarch64_insn_logic_type type);
u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type,
				       enum aarch64_insn_variant variant,
				       enum aarch64_insn_register Rn,
				       enum aarch64_insn_register Rd,
				       u64 imm);
u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
			  enum aarch64_insn_register Rm,
			  enum aarch64_insn_register Rn,
			  enum aarch64_insn_register Rd,
			  u8 lsb);
u32 aarch64_insn_gen_prefetch(enum aarch64_insn_register base,
			      enum aarch64_insn_prfm_type type,
			      enum aarch64_insn_prfm_target target,
			      enum aarch64_insn_prfm_policy policy);
s32 aarch64_get_branch_offset(u32 insn);
u32 aarch64_set_branch_offset(u32 insn, s32 offset);

int aarch64_insn_patch_text_nosync(void *addr, u32 insn);
int aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt);

s32 aarch64_insn_adrp_get_offset(u32 insn);
u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset);

bool aarch32_insn_is_wide(u32 insn);

#define A32_RN_OFFSET	16
#define A32_RT_OFFSET	12
#define A32_RT2_OFFSET	 0

u32 aarch64_insn_extract_system_reg(u32 insn);
u32 aarch32_insn_extract_reg_num(u32 insn, int offset);
u32 aarch32_insn_mcr_extract_opc2(u32 insn);
u32 aarch32_insn_mcr_extract_crm(u32 insn);

typedef bool (pstate_check_t)(unsigned long);
extern pstate_check_t * const aarch32_opcode_cond_checks[16];
#endif /* __ASSEMBLY__ */

#endif	/* __ASM_INSN_H */
Commit	Line	Data
b11a64a4 JL	1	/*
	2	* Copyright (C) 2013 Huawei Ltd.
	3	* Author: Jiang Liu <liuj97@gmail.com>
	4	*
617d2fbc ZSL	5	* Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
617d2fbc ZSL	6	*
b11a64a4 JL	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19	#ifndef __ASM_INSN_H
	20	#define __ASM_INSN_H
edbcf50e	21	#include <linux/build_bug.h>
b11a64a4 JL	22	#include <linux/types.h>
b11a64a4 JL	23
ae164807 JL	24	/* A64 instructions are always 32 bits. */
	25	#define AARCH64_INSN_SIZE 4
	26
26e9b83a	27	#ifndef __ASSEMBLY__
b11a64a4 JL	28	/*
	29	* ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
	30	* Section C3.1 "A64 instruction index by encoding":
	31	* AArch64 main encoding table
	32	* Bit position
	33	* 28 27 26 25 Encoding Group
	34	* 0 0 - - Unallocated
	35	* 1 0 0 - Data processing, immediate
	36	* 1 0 1 - Branch, exception generation and system instructions
	37	* - 1 - 0 Loads and stores
	38	* - 1 0 1 Data processing - register
	39	* 0 1 1 1 Data processing - SIMD and floating point
	40	* 1 1 1 1 Data processing - SIMD and floating point
	41	* "-" means "don't care"
	42	*/
	43	enum aarch64_insn_encoding_class {
	44	AARCH64_INSN_CLS_UNKNOWN, /* UNALLOCATED */
	45	AARCH64_INSN_CLS_DP_IMM, /* Data processing - immediate */
	46	AARCH64_INSN_CLS_DP_REG, /* Data processing - register */
	47	AARCH64_INSN_CLS_DP_FPSIMD, /* Data processing - SIMD and FP */
	48	AARCH64_INSN_CLS_LDST, /* Loads and stores */
	49	AARCH64_INSN_CLS_BR_SYS, /* Branch, exception generation and
	50	* system instructions */
	51	};
	52
	53	enum aarch64_insn_hint_op {
	54	AARCH64_INSN_HINT_NOP = 0x0 << 5,
	55	AARCH64_INSN_HINT_YIELD = 0x1 << 5,
	56	AARCH64_INSN_HINT_WFE = 0x2 << 5,
	57	AARCH64_INSN_HINT_WFI = 0x3 << 5,
	58	AARCH64_INSN_HINT_SEV = 0x4 << 5,
	59	AARCH64_INSN_HINT_SEVL = 0x5 << 5,
	60	};
	61
c84fced8 JL	62	enum aarch64_insn_imm_type {
	63	AARCH64_INSN_IMM_ADR,
	64	AARCH64_INSN_IMM_26,
	65	AARCH64_INSN_IMM_19,
	66	AARCH64_INSN_IMM_16,
	67	AARCH64_INSN_IMM_14,
	68	AARCH64_INSN_IMM_12,
	69	AARCH64_INSN_IMM_9,
1bba567d	70	AARCH64_INSN_IMM_7,
5fdc639a	71	AARCH64_INSN_IMM_6,
4a89d2c9 ZSL	72	AARCH64_INSN_IMM_S,
4a89d2c9 ZSL	73	AARCH64_INSN_IMM_R,
a264bf34	74	AARCH64_INSN_IMM_N,
c84fced8 JL	75	AARCH64_INSN_IMM_MAX
	76	};
	77
617d2fbc ZSL	78	enum aarch64_insn_register_type {
617d2fbc ZSL	79	AARCH64_INSN_REGTYPE_RT,
c0cafbae	80	AARCH64_INSN_REGTYPE_RN,
1bba567d	81	AARCH64_INSN_REGTYPE_RT2,
17cac179	82	AARCH64_INSN_REGTYPE_RM,
9951a157	83	AARCH64_INSN_REGTYPE_RD,
27f95ba5	84	AARCH64_INSN_REGTYPE_RA,
85f68fe8	85	AARCH64_INSN_REGTYPE_RS,
617d2fbc ZSL	86	};
	87
	88	enum aarch64_insn_register {
	89	AARCH64_INSN_REG_0 = 0,
	90	AARCH64_INSN_REG_1 = 1,
	91	AARCH64_INSN_REG_2 = 2,
	92	AARCH64_INSN_REG_3 = 3,
	93	AARCH64_INSN_REG_4 = 4,
	94	AARCH64_INSN_REG_5 = 5,
	95	AARCH64_INSN_REG_6 = 6,
	96	AARCH64_INSN_REG_7 = 7,
	97	AARCH64_INSN_REG_8 = 8,
	98	AARCH64_INSN_REG_9 = 9,
	99	AARCH64_INSN_REG_10 = 10,
	100	AARCH64_INSN_REG_11 = 11,
	101	AARCH64_INSN_REG_12 = 12,
	102	AARCH64_INSN_REG_13 = 13,
	103	AARCH64_INSN_REG_14 = 14,
	104	AARCH64_INSN_REG_15 = 15,
	105	AARCH64_INSN_REG_16 = 16,
	106	AARCH64_INSN_REG_17 = 17,
	107	AARCH64_INSN_REG_18 = 18,
	108	AARCH64_INSN_REG_19 = 19,
	109	AARCH64_INSN_REG_20 = 20,
	110	AARCH64_INSN_REG_21 = 21,
	111	AARCH64_INSN_REG_22 = 22,
	112	AARCH64_INSN_REG_23 = 23,
	113	AARCH64_INSN_REG_24 = 24,
	114	AARCH64_INSN_REG_25 = 25,
	115	AARCH64_INSN_REG_26 = 26,
	116	AARCH64_INSN_REG_27 = 27,
	117	AARCH64_INSN_REG_28 = 28,
	118	AARCH64_INSN_REG_29 = 29,
	119	AARCH64_INSN_REG_FP = 29, /* Frame pointer */
	120	AARCH64_INSN_REG_30 = 30,
	121	AARCH64_INSN_REG_LR = 30, /* Link register */
	122	AARCH64_INSN_REG_ZR = 31, /* Zero: as source register */
	123	AARCH64_INSN_REG_SP = 31 /* Stack pointer: as load/store base reg */
	124	};
	125
d59bee88 DL	126	enum aarch64_insn_special_register {
	127	AARCH64_INSN_SPCLREG_SPSR_EL1 = 0xC200,
	128	AARCH64_INSN_SPCLREG_ELR_EL1 = 0xC201,
	129	AARCH64_INSN_SPCLREG_SP_EL0 = 0xC208,
	130	AARCH64_INSN_SPCLREG_SPSEL = 0xC210,
	131	AARCH64_INSN_SPCLREG_CURRENTEL = 0xC212,
	132	AARCH64_INSN_SPCLREG_DAIF = 0xDA11,
	133	AARCH64_INSN_SPCLREG_NZCV = 0xDA10,
	134	AARCH64_INSN_SPCLREG_FPCR = 0xDA20,
	135	AARCH64_INSN_SPCLREG_DSPSR_EL0 = 0xDA28,
	136	AARCH64_INSN_SPCLREG_DLR_EL0 = 0xDA29,
	137	AARCH64_INSN_SPCLREG_SPSR_EL2 = 0xE200,
	138	AARCH64_INSN_SPCLREG_ELR_EL2 = 0xE201,
	139	AARCH64_INSN_SPCLREG_SP_EL1 = 0xE208,
	140	AARCH64_INSN_SPCLREG_SPSR_INQ = 0xE218,
	141	AARCH64_INSN_SPCLREG_SPSR_ABT = 0xE219,
	142	AARCH64_INSN_SPCLREG_SPSR_UND = 0xE21A,
	143	AARCH64_INSN_SPCLREG_SPSR_FIQ = 0xE21B,
	144	AARCH64_INSN_SPCLREG_SPSR_EL3 = 0xF200,
	145	AARCH64_INSN_SPCLREG_ELR_EL3 = 0xF201,
	146	AARCH64_INSN_SPCLREG_SP_EL2 = 0xF210
	147	};
	148
617d2fbc ZSL	149	enum aarch64_insn_variant {
	150	AARCH64_INSN_VARIANT_32BIT,
	151	AARCH64_INSN_VARIANT_64BIT
	152	};
	153
345e0d35 ZSL	154	enum aarch64_insn_condition {
	155	AARCH64_INSN_COND_EQ = 0x0, /* == */
	156	AARCH64_INSN_COND_NE = 0x1, /* != */
	157	AARCH64_INSN_COND_CS = 0x2, /* unsigned >= */
	158	AARCH64_INSN_COND_CC = 0x3, /* unsigned < */
	159	AARCH64_INSN_COND_MI = 0x4, /* < 0 */
	160	AARCH64_INSN_COND_PL = 0x5, /* >= 0 */
	161	AARCH64_INSN_COND_VS = 0x6, /* overflow */
	162	AARCH64_INSN_COND_VC = 0x7, /* no overflow */
	163	AARCH64_INSN_COND_HI = 0x8, /* unsigned > */
	164	AARCH64_INSN_COND_LS = 0x9, /* unsigned <= */
	165	AARCH64_INSN_COND_GE = 0xa, /* signed >= */
	166	AARCH64_INSN_COND_LT = 0xb, /* signed < */
	167	AARCH64_INSN_COND_GT = 0xc, /* signed > */
	168	AARCH64_INSN_COND_LE = 0xd, /* signed <= */
	169	AARCH64_INSN_COND_AL = 0xe, /* always */
	170	};
	171
5c5bf25d JL	172	enum aarch64_insn_branch_type {
	173	AARCH64_INSN_BRANCH_NOLINK,
	174	AARCH64_INSN_BRANCH_LINK,
c0cafbae	175	AARCH64_INSN_BRANCH_RETURN,
617d2fbc ZSL	176	AARCH64_INSN_BRANCH_COMP_ZERO,
617d2fbc ZSL	177	AARCH64_INSN_BRANCH_COMP_NONZERO,
5c5bf25d JL	178	};
5c5bf25d JL	179
17cac179 ZSL	180	enum aarch64_insn_size_type {
	181	AARCH64_INSN_SIZE_8,
	182	AARCH64_INSN_SIZE_16,
	183	AARCH64_INSN_SIZE_32,
	184	AARCH64_INSN_SIZE_64,
	185	};
	186
	187	enum aarch64_insn_ldst_type {
	188	AARCH64_INSN_LDST_LOAD_REG_OFFSET,
	189	AARCH64_INSN_LDST_STORE_REG_OFFSET,
1bba567d ZSL	190	AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX,
	191	AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX,
	192	AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX,
	193	AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX,
85f68fe8 DB	194	AARCH64_INSN_LDST_LOAD_EX,
85f68fe8 DB	195	AARCH64_INSN_LDST_STORE_EX,
17cac179 ZSL	196	};
17cac179 ZSL	197
9951a157 ZSL	198	enum aarch64_insn_adsb_type {
	199	AARCH64_INSN_ADSB_ADD,
	200	AARCH64_INSN_ADSB_SUB,
	201	AARCH64_INSN_ADSB_ADD_SETFLAGS,
	202	AARCH64_INSN_ADSB_SUB_SETFLAGS
	203	};
	204
6098f2d5 ZSL	205	enum aarch64_insn_movewide_type {
	206	AARCH64_INSN_MOVEWIDE_ZERO,
	207	AARCH64_INSN_MOVEWIDE_KEEP,
	208	AARCH64_INSN_MOVEWIDE_INVERSE
	209	};
	210
4a89d2c9 ZSL	211	enum aarch64_insn_bitfield_type {
	212	AARCH64_INSN_BITFIELD_MOVE,
	213	AARCH64_INSN_BITFIELD_MOVE_UNSIGNED,
	214	AARCH64_INSN_BITFIELD_MOVE_SIGNED
	215	};
	216
546dd36b ZSL	217	enum aarch64_insn_data1_type {
	218	AARCH64_INSN_DATA1_REVERSE_16,
	219	AARCH64_INSN_DATA1_REVERSE_32,
	220	AARCH64_INSN_DATA1_REVERSE_64,
	221	};
	222
64810639 ZSL	223	enum aarch64_insn_data2_type {
	224	AARCH64_INSN_DATA2_UDIV,
	225	AARCH64_INSN_DATA2_SDIV,
	226	AARCH64_INSN_DATA2_LSLV,
	227	AARCH64_INSN_DATA2_LSRV,
	228	AARCH64_INSN_DATA2_ASRV,
	229	AARCH64_INSN_DATA2_RORV,
	230	};
	231
27f95ba5 ZSL	232	enum aarch64_insn_data3_type {
	233	AARCH64_INSN_DATA3_MADD,
	234	AARCH64_INSN_DATA3_MSUB,
	235	};
	236
5e6e15a2 ZSL	237	enum aarch64_insn_logic_type {
	238	AARCH64_INSN_LOGIC_AND,
	239	AARCH64_INSN_LOGIC_BIC,
	240	AARCH64_INSN_LOGIC_ORR,
	241	AARCH64_INSN_LOGIC_ORN,
	242	AARCH64_INSN_LOGIC_EOR,
	243	AARCH64_INSN_LOGIC_EON,
	244	AARCH64_INSN_LOGIC_AND_SETFLAGS,
	245	AARCH64_INSN_LOGIC_BIC_SETFLAGS
	246	};
	247
85f68fe8 DB	248	enum aarch64_insn_prfm_type {
	249	AARCH64_INSN_PRFM_TYPE_PLD,
	250	AARCH64_INSN_PRFM_TYPE_PLI,
	251	AARCH64_INSN_PRFM_TYPE_PST,
	252	};
	253
	254	enum aarch64_insn_prfm_target {
	255	AARCH64_INSN_PRFM_TARGET_L1,
	256	AARCH64_INSN_PRFM_TARGET_L2,
	257	AARCH64_INSN_PRFM_TARGET_L3,
	258	};
	259
	260	enum aarch64_insn_prfm_policy {
	261	AARCH64_INSN_PRFM_POLICY_KEEP,
	262	AARCH64_INSN_PRFM_POLICY_STRM,
	263	};
	264
7aaf7b2f AB	265	enum aarch64_insn_adr_type {
	266	AARCH64_INSN_ADR_TYPE_ADRP,
	267	AARCH64_INSN_ADR_TYPE_ADR,
	268	};
	269
edbcf50e JPB	270	#define __AARCH64_INSN_FUNCS(abbr, mask, val) \
	271	static __always_inline bool aarch64_insn_is_##abbr(u32 code) \
	272	{ \
	273	BUILD_BUG_ON(~(mask) & (val)); \
	274	return (code & (mask)) == (val); \
	275	} \
	276	static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \
	277	{ \
	278	return (val); \
	279	}
b11a64a4	280
46084bc2 SP	281	__AARCH64_INSN_FUNCS(adr, 0x9F000000, 0x10000000)
46084bc2 SP	282	__AARCH64_INSN_FUNCS(adrp, 0x9F000000, 0x90000000)
85f68fe8	283	__AARCH64_INSN_FUNCS(prfm, 0x3FC00000, 0x39800000)
d59bee88	284	__AARCH64_INSN_FUNCS(prfm_lit, 0xFF000000, 0xD8000000)
17cac179	285	__AARCH64_INSN_FUNCS(str_reg, 0x3FE0EC00, 0x38206800)
c5e2edeb	286	__AARCH64_INSN_FUNCS(ldadd, 0x3F20FC00, 0x38200000)
17cac179	287	__AARCH64_INSN_FUNCS(ldr_reg, 0x3FE0EC00, 0x38606800)
d59bee88 DL	288	__AARCH64_INSN_FUNCS(ldr_lit, 0xBF000000, 0x18000000)
	289	__AARCH64_INSN_FUNCS(ldrsw_lit, 0xFF000000, 0x98000000)
	290	__AARCH64_INSN_FUNCS(exclusive, 0x3F800000, 0x08000000)
2dd0e8d2 SP	291	__AARCH64_INSN_FUNCS(load_ex, 0x3F400000, 0x08400000)
2dd0e8d2 SP	292	__AARCH64_INSN_FUNCS(store_ex, 0x3F400000, 0x08000000)
1bba567d ZSL	293	__AARCH64_INSN_FUNCS(stp_post, 0x7FC00000, 0x28800000)
	294	__AARCH64_INSN_FUNCS(ldp_post, 0x7FC00000, 0x28C00000)
	295	__AARCH64_INSN_FUNCS(stp_pre, 0x7FC00000, 0x29800000)
	296	__AARCH64_INSN_FUNCS(ldp_pre, 0x7FC00000, 0x29C00000)
9951a157 ZSL	297	__AARCH64_INSN_FUNCS(add_imm, 0x7F000000, 0x11000000)
	298	__AARCH64_INSN_FUNCS(adds_imm, 0x7F000000, 0x31000000)
	299	__AARCH64_INSN_FUNCS(sub_imm, 0x7F000000, 0x51000000)
	300	__AARCH64_INSN_FUNCS(subs_imm, 0x7F000000, 0x71000000)
6098f2d5	301	__AARCH64_INSN_FUNCS(movn, 0x7F800000, 0x12800000)
4a89d2c9 ZSL	302	__AARCH64_INSN_FUNCS(sbfm, 0x7F800000, 0x13000000)
4a89d2c9 ZSL	303	__AARCH64_INSN_FUNCS(bfm, 0x7F800000, 0x33000000)
6098f2d5	304	__AARCH64_INSN_FUNCS(movz, 0x7F800000, 0x52800000)
4a89d2c9	305	__AARCH64_INSN_FUNCS(ubfm, 0x7F800000, 0x53000000)
6098f2d5	306	__AARCH64_INSN_FUNCS(movk, 0x7F800000, 0x72800000)
5fdc639a ZSL	307	__AARCH64_INSN_FUNCS(add, 0x7F200000, 0x0B000000)
	308	__AARCH64_INSN_FUNCS(adds, 0x7F200000, 0x2B000000)
	309	__AARCH64_INSN_FUNCS(sub, 0x7F200000, 0x4B000000)
	310	__AARCH64_INSN_FUNCS(subs, 0x7F200000, 0x6B000000)
27f95ba5 ZSL	311	__AARCH64_INSN_FUNCS(madd, 0x7FE08000, 0x1B000000)
27f95ba5 ZSL	312	__AARCH64_INSN_FUNCS(msub, 0x7FE08000, 0x1B008000)
64810639 ZSL	313	__AARCH64_INSN_FUNCS(udiv, 0x7FE0FC00, 0x1AC00800)
	314	__AARCH64_INSN_FUNCS(sdiv, 0x7FE0FC00, 0x1AC00C00)
	315	__AARCH64_INSN_FUNCS(lslv, 0x7FE0FC00, 0x1AC02000)
	316	__AARCH64_INSN_FUNCS(lsrv, 0x7FE0FC00, 0x1AC02400)
	317	__AARCH64_INSN_FUNCS(asrv, 0x7FE0FC00, 0x1AC02800)
	318	__AARCH64_INSN_FUNCS(rorv, 0x7FE0FC00, 0x1AC02C00)
546dd36b ZSL	319	__AARCH64_INSN_FUNCS(rev16, 0x7FFFFC00, 0x5AC00400)
	320	__AARCH64_INSN_FUNCS(rev32, 0x7FFFFC00, 0x5AC00800)
	321	__AARCH64_INSN_FUNCS(rev64, 0x7FFFFC00, 0x5AC00C00)
5e6e15a2 ZSL	322	__AARCH64_INSN_FUNCS(and, 0x7F200000, 0x0A000000)
	323	__AARCH64_INSN_FUNCS(bic, 0x7F200000, 0x0A200000)
	324	__AARCH64_INSN_FUNCS(orr, 0x7F200000, 0x2A000000)
	325	__AARCH64_INSN_FUNCS(orn, 0x7F200000, 0x2A200000)
	326	__AARCH64_INSN_FUNCS(eor, 0x7F200000, 0x4A000000)
	327	__AARCH64_INSN_FUNCS(eon, 0x7F200000, 0x4A200000)
	328	__AARCH64_INSN_FUNCS(ands, 0x7F200000, 0x6A000000)
	329	__AARCH64_INSN_FUNCS(bics, 0x7F200000, 0x6A200000)
ef3935ee MZ	330	__AARCH64_INSN_FUNCS(and_imm, 0x7F800000, 0x12000000)
	331	__AARCH64_INSN_FUNCS(orr_imm, 0x7F800000, 0x32000000)
	332	__AARCH64_INSN_FUNCS(eor_imm, 0x7F800000, 0x52000000)
	333	__AARCH64_INSN_FUNCS(ands_imm, 0x7F800000, 0x72000000)
9f2efa32	334	__AARCH64_INSN_FUNCS(extr, 0x7FA00000, 0x13800000)
b11a64a4 JL	335	__AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000)
b11a64a4 JL	336	__AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000)
115386f8 RM	337	__AARCH64_INSN_FUNCS(cbz, 0x7F000000, 0x34000000)
	338	__AARCH64_INSN_FUNCS(cbnz, 0x7F000000, 0x35000000)
	339	__AARCH64_INSN_FUNCS(tbz, 0x7F000000, 0x36000000)
	340	__AARCH64_INSN_FUNCS(tbnz, 0x7F000000, 0x37000000)
345e0d35	341	__AARCH64_INSN_FUNCS(bcond, 0xFF000010, 0x54000000)
b11a64a4 JL	342	__AARCH64_INSN_FUNCS(svc, 0xFFE0001F, 0xD4000001)
	343	__AARCH64_INSN_FUNCS(hvc, 0xFFE0001F, 0xD4000002)
	344	__AARCH64_INSN_FUNCS(smc, 0xFFE0001F, 0xD4000003)
	345	__AARCH64_INSN_FUNCS(brk, 0xFFE0001F, 0xD4200000)
d59bee88	346	__AARCH64_INSN_FUNCS(exception, 0xFF000000, 0xD4000000)
b11a64a4	347	__AARCH64_INSN_FUNCS(hint, 0xFFFFF01F, 0xD503201F)
c0cafbae ZSL	348	__AARCH64_INSN_FUNCS(br, 0xFFFFFC1F, 0xD61F0000)
	349	__AARCH64_INSN_FUNCS(blr, 0xFFFFFC1F, 0xD63F0000)
	350	__AARCH64_INSN_FUNCS(ret, 0xFFFFFC1F, 0xD65F0000)
d59bee88 DL	351	__AARCH64_INSN_FUNCS(eret, 0xFFFFFFFF, 0xD69F03E0)
	352	__AARCH64_INSN_FUNCS(mrs, 0xFFF00000, 0xD5300000)
	353	__AARCH64_INSN_FUNCS(msr_imm, 0xFFF8F01F, 0xD500401F)
	354	__AARCH64_INSN_FUNCS(msr_reg, 0xFFF00000, 0xD5100000)
b11a64a4 JL	355
	356	#undef __AARCH64_INSN_FUNCS
	357
	358	bool aarch64_insn_is_nop(u32 insn);
10b48f7e	359	bool aarch64_insn_is_branch_imm(u32 insn);
b11a64a4	360
46084bc2 SP	361	static inline bool aarch64_insn_is_adr_adrp(u32 insn)
	362	{
	363	return aarch64_insn_is_adr(insn) \|\| aarch64_insn_is_adrp(insn);
	364	}
	365
ae164807 JL	366	int aarch64_insn_read(void addr, u32 insnp);
ae164807 JL	367	int aarch64_insn_write(void *addr, u32 insn);
b11a64a4	368	enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn);
d59bee88 DL	369	bool aarch64_insn_uses_literal(u32 insn);
d59bee88 DL	370	bool aarch64_insn_is_branch(u32 insn);
0978fb25	371	u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn);
c84fced8 JL	372	u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
c84fced8 JL	373	u32 insn, u64 imm);
8c2dcbd2 SP	374	u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,
8c2dcbd2 SP	375	u32 insn);
5c5bf25d JL	376	u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
5c5bf25d JL	377	enum aarch64_insn_branch_type type);
617d2fbc ZSL	378	u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
	379	enum aarch64_insn_register reg,
	380	enum aarch64_insn_variant variant,
	381	enum aarch64_insn_branch_type type);
345e0d35 ZSL	382	u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
345e0d35 ZSL	383	enum aarch64_insn_condition cond);
5c5bf25d JL	384	u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_op op);
5c5bf25d JL	385	u32 aarch64_insn_gen_nop(void);
c0cafbae ZSL	386	u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
c0cafbae ZSL	387	enum aarch64_insn_branch_type type);
17cac179 ZSL	388	u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
	389	enum aarch64_insn_register base,
	390	enum aarch64_insn_register offset,
	391	enum aarch64_insn_size_type size,
	392	enum aarch64_insn_ldst_type type);
1bba567d ZSL	393	u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
	394	enum aarch64_insn_register reg2,
	395	enum aarch64_insn_register base,
	396	int offset,
	397	enum aarch64_insn_variant variant,
	398	enum aarch64_insn_ldst_type type);
85f68fe8 DB	399	u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
	400	enum aarch64_insn_register base,
	401	enum aarch64_insn_register state,
	402	enum aarch64_insn_size_type size,
	403	enum aarch64_insn_ldst_type type);
34b8ab09 DB	404	u32 aarch64_insn_gen_ldadd(enum aarch64_insn_register result,
	405	enum aarch64_insn_register address,
	406	enum aarch64_insn_register value,
	407	enum aarch64_insn_size_type size);
	408	u32 aarch64_insn_gen_stadd(enum aarch64_insn_register address,
	409	enum aarch64_insn_register value,
	410	enum aarch64_insn_size_type size);
9951a157 ZSL	411	u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
	412	enum aarch64_insn_register src,
	413	int imm, enum aarch64_insn_variant variant,
	414	enum aarch64_insn_adsb_type type);
7aaf7b2f AB	415	u32 aarch64_insn_gen_adr(unsigned long pc, unsigned long addr,
	416	enum aarch64_insn_register reg,
	417	enum aarch64_insn_adr_type type);
4a89d2c9 ZSL	418	u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
	419	enum aarch64_insn_register src,
	420	int immr, int imms,
	421	enum aarch64_insn_variant variant,
	422	enum aarch64_insn_bitfield_type type);
6098f2d5 ZSL	423	u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
	424	int imm, int shift,
	425	enum aarch64_insn_variant variant,
	426	enum aarch64_insn_movewide_type type);
5fdc639a ZSL	427	u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
	428	enum aarch64_insn_register src,
	429	enum aarch64_insn_register reg,
	430	int shift,
	431	enum aarch64_insn_variant variant,
	432	enum aarch64_insn_adsb_type type);
546dd36b ZSL	433	u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
	434	enum aarch64_insn_register src,
	435	enum aarch64_insn_variant variant,
	436	enum aarch64_insn_data1_type type);
64810639 ZSL	437	u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
	438	enum aarch64_insn_register src,
	439	enum aarch64_insn_register reg,
	440	enum aarch64_insn_variant variant,
	441	enum aarch64_insn_data2_type type);
27f95ba5 ZSL	442	u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
	443	enum aarch64_insn_register src,
	444	enum aarch64_insn_register reg1,
	445	enum aarch64_insn_register reg2,
	446	enum aarch64_insn_variant variant,
	447	enum aarch64_insn_data3_type type);
5e6e15a2 ZSL	448	u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
	449	enum aarch64_insn_register src,
	450	enum aarch64_insn_register reg,
	451	int shift,
	452	enum aarch64_insn_variant variant,
	453	enum aarch64_insn_logic_type type);
ef3935ee MZ	454	u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type,
	455	enum aarch64_insn_variant variant,
	456	enum aarch64_insn_register Rn,
	457	enum aarch64_insn_register Rd,
	458	u64 imm);
9f2efa32 MZ	459	u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
	460	enum aarch64_insn_register Rm,
	461	enum aarch64_insn_register Rn,
	462	enum aarch64_insn_register Rd,
	463	u8 lsb);
85f68fe8 DB	464	u32 aarch64_insn_gen_prefetch(enum aarch64_insn_register base,
	465	enum aarch64_insn_prfm_type type,
	466	enum aarch64_insn_prfm_target target,
	467	enum aarch64_insn_prfm_policy policy);
10b48f7e MZ	468	s32 aarch64_get_branch_offset(u32 insn);
10b48f7e MZ	469	u32 aarch64_set_branch_offset(u32 insn, s32 offset);
5c5bf25d	470
ae164807	471	int aarch64_insn_patch_text_nosync(void *addr, u32 insn);
ae164807	472	int aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt);
9b79f52d	473
46084bc2 SP	474	s32 aarch64_insn_adrp_get_offset(u32 insn);
	475	u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset);
	476
9b79f52d	477	bool aarch32_insn_is_wide(u32 insn);
bd35a4ad PA	478
	479	#define A32_RN_OFFSET 16
	480	#define A32_RT_OFFSET 12
	481	#define A32_RT2_OFFSET 0
	482
d59bee88	483	u32 aarch64_insn_extract_system_reg(u32 insn);
bd35a4ad	484	u32 aarch32_insn_extract_reg_num(u32 insn, int offset);
c852f320 PA	485	u32 aarch32_insn_mcr_extract_opc2(u32 insn);
c852f320 PA	486	u32 aarch32_insn_mcr_extract_crm(u32 insn);
2af3ec08 DL	487
	488	typedef bool (pstate_check_t)(unsigned long);
	489	extern pstate_check_t * const aarch32_opcode_cond_checks[16];
26e9b83a	490	#endif /* __ASSEMBLY__ */
ae164807	491
b11a64a4	492	#endif /* __ASM_INSN_H */