[mirror_ubuntu-focal-kernel.git] / arch / arm64 / include / asm / io.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Based on arch/arm/include/asm/io.h
 *
 * Copyright (C) 1996-2000 Russell King
 * Copyright (C) 2012 ARM Ltd.
 */
#ifndef __ASM_IO_H
#define __ASM_IO_H

#include <linux/types.h>

#include <asm/byteorder.h>
#include <asm/barrier.h>
#include <asm/memory.h>
#include <asm/pgtable.h>
#include <asm/early_ioremap.h>
#include <asm/alternative.h>
#include <asm/cpufeature.h>

/*
 * Generic IO read/write.  These perform native-endian accesses.
 */
#define __raw_writeb __raw_writeb
static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
{
	asm volatile("strb %w0, [%1]" : : "rZ" (val), "r" (addr));
}

#define __raw_writew __raw_writew
static inline void __raw_writew(u16 val, volatile void __iomem *addr)
{
	asm volatile("strh %w0, [%1]" : : "rZ" (val), "r" (addr));
}

#define __raw_writel __raw_writel
static inline void __raw_writel(u32 val, volatile void __iomem *addr)
{
	asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr));
}

#define __raw_writeq __raw_writeq
static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
{
	asm volatile("str %x0, [%1]" : : "rZ" (val), "r" (addr));
}

#define __raw_readb __raw_readb
static inline u8 __raw_readb(const volatile void __iomem *addr)
{
	u8 val;
	asm volatile(ALTERNATIVE("ldrb %w0, [%1]",
				 "ldarb %w0, [%1]",
				 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
		     : "=r" (val) : "r" (addr));
	return val;
}

#define __raw_readw __raw_readw
static inline u16 __raw_readw(const volatile void __iomem *addr)
{
	u16 val;

	asm volatile(ALTERNATIVE("ldrh %w0, [%1]",
				 "ldarh %w0, [%1]",
				 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
		     : "=r" (val) : "r" (addr));
	return val;
}

#define __raw_readl __raw_readl
static inline u32 __raw_readl(const volatile void __iomem *addr)
{
	u32 val;
	asm volatile(ALTERNATIVE("ldr %w0, [%1]",
				 "ldar %w0, [%1]",
				 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
		     : "=r" (val) : "r" (addr));
	return val;
}

#define __raw_readq __raw_readq
static inline u64 __raw_readq(const volatile void __iomem *addr)
{
	u64 val;
	asm volatile(ALTERNATIVE("ldr %0, [%1]",
				 "ldar %0, [%1]",
				 ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
		     : "=r" (val) : "r" (addr));
	return val;
}

/* IO barriers */
#define __iormb(v)							\
({									\
	unsigned long tmp;						\
									\
	dma_rmb();								\
									\
	/*								\
	 * Create a dummy control dependency from the IO read to any	\
	 * later instructions. This ensures that a subsequent call to	\
	 * udelay() will be ordered due to the ISB in get_cycles().	\
	 */								\
	asm volatile("eor	%0, %1, %1\n"				\
		     "cbnz	%0, ."					\
		     : "=r" (tmp) : "r" ((unsigned long)(v))		\
		     : "memory");					\
})

#define __io_par(v)		__iormb(v)
#define __iowmb()		dma_wmb()

/*
 * Relaxed I/O memory access primitives. These follow the Device memory
 * ordering rules but do not guarantee any ordering relative to Normal memory
 * accesses.
 */
#define readb_relaxed(c)	({ u8  __r = __raw_readb(c); __r; })
#define readw_relaxed(c)	({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
#define readl_relaxed(c)	({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
#define readq_relaxed(c)	({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })

#define writeb_relaxed(v,c)	((void)__raw_writeb((v),(c)))
#define writew_relaxed(v,c)	((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
#define writel_relaxed(v,c)	((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
#define writeq_relaxed(v,c)	((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))

/*
 * I/O memory access primitives. Reads are ordered relative to any
 * following Normal memory access. Writes are ordered relative to any prior
 * Normal memory access.
 */
#define readb(c)		({ u8  __v = readb_relaxed(c); __iormb(__v); __v; })
#define readw(c)		({ u16 __v = readw_relaxed(c); __iormb(__v); __v; })
#define readl(c)		({ u32 __v = readl_relaxed(c); __iormb(__v); __v; })
#define readq(c)		({ u64 __v = readq_relaxed(c); __iormb(__v); __v; })

#define writeb(v,c)		({ __iowmb(); writeb_relaxed((v),(c)); })
#define writew(v,c)		({ __iowmb(); writew_relaxed((v),(c)); })
#define writel(v,c)		({ __iowmb(); writel_relaxed((v),(c)); })
#define writeq(v,c)		({ __iowmb(); writeq_relaxed((v),(c)); })

/*
 *  I/O port access primitives.
 */
#define arch_has_dev_port()	(1)
#define IO_SPACE_LIMIT		(PCI_IO_SIZE - 1)
#define PCI_IOBASE		((void __iomem *)PCI_IO_START)

/*
 * String version of I/O memory access operations.
 */
extern void __memcpy_fromio(void *, const volatile void __iomem *, size_t);
extern void __memcpy_toio(volatile void __iomem *, const void *, size_t);
extern void __memset_io(volatile void __iomem *, int, size_t);

#define memset_io(c,v,l)	__memset_io((c),(v),(l))
#define memcpy_fromio(a,c,l)	__memcpy_fromio((a),(c),(l))
#define memcpy_toio(c,a,l)	__memcpy_toio((c),(a),(l))

/*
 * I/O memory mapping functions.
 */
extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot);
extern void iounmap(volatile void __iomem *addr);
extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size);

#define ioremap(addr, size)		__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
#define ioremap_nocache(addr, size)	__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
#define ioremap_wc(addr, size)		__ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
#define ioremap_wt(addr, size)		__ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))

/*
 * PCI configuration space mapping function.
 *
 * The PCI specification disallows posted write configuration transactions.
 * Add an arch specific pci_remap_cfgspace() definition that is implemented
 * through nGnRnE device memory attribute as recommended by the ARM v8
 * Architecture reference manual Issue A.k B2.8.2 "Device memory".
 */
#define pci_remap_cfgspace(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRnE))

/*
 * io{read,write}{16,32,64}be() macros
 */
#define ioread16be(p)		({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(__v); __v; })
#define ioread32be(p)		({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(__v); __v; })
#define ioread64be(p)		({ __u64 __v = be64_to_cpu((__force __be64)__raw_readq(p)); __iormb(__v); __v; })

#define iowrite16be(v,p)	({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
#define iowrite32be(v,p)	({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
#define iowrite64be(v,p)	({ __iowmb(); __raw_writeq((__force __u64)cpu_to_be64(v), p); })

#include <asm-generic/io.h>

/*
 * More restrictive address range checking than the default implementation
 * (PHYS_OFFSET and PHYS_MASK taken into account).
 */
#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);

extern int devmem_is_allowed(unsigned long pfn);

#endif	/* __ASM_IO_H */
Commit	Line	Data
caab277b	1	/* SPDX-License-Identifier: GPL-2.0-only */
fc47897d CM	2	/*
	3	* Based on arch/arm/include/asm/io.h
	4	*
	5	* Copyright (C) 1996-2000 Russell King
	6	* Copyright (C) 2012 ARM Ltd.
fc47897d CM	7	*/
	8	#ifndef __ASM_IO_H
	9	#define __ASM_IO_H
	10
fc47897d CM	11	#include <linux/types.h>
	12
	13	#include <asm/byteorder.h>
	14	#include <asm/barrier.h>
aa03c428	15	#include <asm/memory.h>
fc47897d	16	#include <asm/pgtable.h>
bf4b558e	17	#include <asm/early_ioremap.h>
5afaa1fc AP	18	#include <asm/alternative.h>
5afaa1fc AP	19	#include <asm/cpufeature.h>
fc47897d CM	20
	21	/*
	22	* Generic IO read/write. These perform native-endian accesses.
	23	*/
09a57239	24	#define __raw_writeb __raw_writeb
fc47897d CM	25	static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
fc47897d CM	26	{
ee5e41b5	27	asm volatile("strb %w0, [%1]" : : "rZ" (val), "r" (addr));
fc47897d CM	28	}
fc47897d CM	29
09a57239	30	#define __raw_writew __raw_writew
fc47897d CM	31	static inline void __raw_writew(u16 val, volatile void __iomem *addr)
fc47897d CM	32	{
ee5e41b5	33	asm volatile("strh %w0, [%1]" : : "rZ" (val), "r" (addr));
fc47897d CM	34	}
fc47897d CM	35
09a57239	36	#define __raw_writel __raw_writel
fc47897d CM	37	static inline void __raw_writel(u32 val, volatile void __iomem *addr)
fc47897d CM	38	{
ee5e41b5	39	asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr));
fc47897d CM	40	}
fc47897d CM	41
09a57239	42	#define __raw_writeq __raw_writeq
fc47897d CM	43	static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
fc47897d CM	44	{
ee5e41b5	45	asm volatile("str %x0, [%1]" : : "rZ" (val), "r" (addr));
fc47897d CM	46	}
fc47897d CM	47
09a57239	48	#define __raw_readb __raw_readb
fc47897d CM	49	static inline u8 __raw_readb(const volatile void __iomem *addr)
	50	{
	51	u8 val;
5afaa1fc AP	52	asm volatile(ALTERNATIVE("ldrb %w0, [%1]",
	53	"ldarb %w0, [%1]",
	54	ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
	55	: "=r" (val) : "r" (addr));
fc47897d CM	56	return val;
	57	}
	58
09a57239	59	#define __raw_readw __raw_readw
fc47897d CM	60	static inline u16 __raw_readw(const volatile void __iomem *addr)
	61	{
	62	u16 val;
5afaa1fc AP	63
	64	asm volatile(ALTERNATIVE("ldrh %w0, [%1]",
	65	"ldarh %w0, [%1]",
	66	ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
	67	: "=r" (val) : "r" (addr));
fc47897d CM	68	return val;
	69	}
	70
09a57239	71	#define __raw_readl __raw_readl
fc47897d CM	72	static inline u32 __raw_readl(const volatile void __iomem *addr)
	73	{
	74	u32 val;
5afaa1fc AP	75	asm volatile(ALTERNATIVE("ldr %w0, [%1]",
	76	"ldar %w0, [%1]",
	77	ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
	78	: "=r" (val) : "r" (addr));
fc47897d CM	79	return val;
	80	}
	81
09a57239	82	#define __raw_readq __raw_readq
fc47897d CM	83	static inline u64 __raw_readq(const volatile void __iomem *addr)
	84	{
	85	u64 val;
5afaa1fc AP	86	asm volatile(ALTERNATIVE("ldr %0, [%1]",
	87	"ldar %0, [%1]",
	88	ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE)
	89	: "=r" (val) : "r" (addr));
fc47897d CM	90	return val;
	91	}
	92
	93	/* IO barriers */
6460d320 WD	94	#define __iormb(v) \
	95	({ \
	96	unsigned long tmp; \
	97	\
22ec7161	98	dma_rmb(); \
6460d320 WD	99	\
	100	/* \
	101	* Create a dummy control dependency from the IO read to any \
	102	* later instructions. This ensures that a subsequent call to \
	103	* udelay() will be ordered due to the ISB in get_cycles(). \
	104	*/ \
	105	asm volatile("eor %0, %1, %1\n" \
	106	"cbnz %0, ." \
1b57ec8c WD	107	: "=r" (tmp) : "r" ((unsigned long)(v)) \
1b57ec8c WD	108	: "memory"); \
6460d320 WD	109	})
6460d320 WD	110
2c97a9cc	111	#define __io_par(v) __iormb(v)
22ec7161	112	#define __iowmb() dma_wmb()
fc47897d	113
fc47897d CM	114	/*
	115	* Relaxed I/O memory access primitives. These follow the Device memory
	116	* ordering rules but do not guarantee any ordering relative to Normal memory
	117	* accesses.
	118	*/
e985ad17 MS	119	#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
	120	#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
	121	#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
	122	#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
fc47897d CM	123
	124	#define writeb_relaxed(v,c) ((void)__raw_writeb((v),(c)))
	125	#define writew_relaxed(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c)))
	126	#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
12f88398	127	#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
fc47897d CM	128
	129	/*
	130	* I/O memory access primitives. Reads are ordered relative to any
	131	* following Normal memory access. Writes are ordered relative to any prior
	132	* Normal memory access.
	133	*/
6460d320 WD	134	#define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(__v); __v; })
	135	#define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(__v); __v; })
	136	#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(__v); __v; })
	137	#define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(__v); __v; })
fc47897d CM	138
	139	#define writeb(v,c) ({ __iowmb(); writeb_relaxed((v),(c)); })
	140	#define writew(v,c) ({ __iowmb(); writew_relaxed((v),(c)); })
	141	#define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c)); })
12f88398	142	#define writeq(v,c) ({ __iowmb(); writeq_relaxed((v),(c)); })
fc47897d CM	143
	144	/*
	145	* I/O port access primitives.
	146	*/
d1e6dc91	147	#define arch_has_dev_port() (1)
aa03c428 MR	148	#define IO_SPACE_LIMIT (PCI_IO_SIZE - 1)
aa03c428 MR	149	#define PCI_IOBASE ((void __iomem *)PCI_IO_START)
fc47897d	150
fc47897d CM	151	/*
	152	* String version of I/O memory access operations.
	153	*/
	154	extern void __memcpy_fromio(void , const volatile void __iomem , size_t);
	155	extern void __memcpy_toio(volatile void __iomem , const void , size_t);
	156	extern void __memset_io(volatile void __iomem *, int, size_t);
	157
	158	#define memset_io(c,v,l) __memset_io((c),(v),(l))
	159	#define memcpy_fromio(a,c,l) __memcpy_fromio((a),(c),(l))
	160	#define memcpy_toio(c,a,l) __memcpy_toio((c),(a),(l))
	161
	162	/*
	163	* I/O memory mapping functions.
	164	*/
	165	extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot);
e376897f	166	extern void iounmap(volatile void __iomem *addr);
c04e8e2f	167	extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size);
fc47897d	168
489f781a CM	169	#define ioremap(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
	170	#define ioremap_nocache(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
	171	#define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
556269c1	172	#define ioremap_wt(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
fc47897d	173
f1e209b7 LP	174	/*
	175	* PCI configuration space mapping function.
	176	*
	177	* The PCI specification disallows posted write configuration transactions.
	178	* Add an arch specific pci_remap_cfgspace() definition that is implemented
	179	* through nGnRnE device memory attribute as recommended by the ARM v8
	180	* Architecture reference manual Issue A.k B2.8.2 "Device memory".
	181	*/
	182	#define pci_remap_cfgspace(addr, size) __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRnE))
	183
fc47897d	184	/*
2a41bfbc	185	* io{read,write}{16,32,64}be() macros
fc47897d	186	*/
6460d320 WD	187	#define ioread16be(p) ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(__v); __v; })
	188	#define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(__v); __v; })
	189	#define ioread64be(p) ({ __u64 __v = be64_to_cpu((__force __be64)__raw_readq(p)); __iormb(__v); __v; })
fc47897d	190
09a57239 TR	191	#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
09a57239 TR	192	#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
2a41bfbc	193	#define iowrite64be(v,p) ({ __iowmb(); __raw_writeq((__force __u64)cpu_to_be64(v), p); })
fc47897d	194
09a57239 TR	195	#include <asm-generic/io.h>
	196
	197	/*
	198	* More restrictive address range checking than the default implementation
	199	* (PHYS_OFFSET and PHYS_MASK taken into account).
	200	*/
	201	#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
	202	extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
	203	extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
	204
	205	extern int devmem_is_allowed(unsigned long pfn);
	206
fc47897d	207	#endif /* __ASM_IO_H */