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0369f6a3 MZ |
1 | /* |
2 | * Copyright (C) 2012,2013 - ARM Ltd | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #ifndef __ARM64_KVM_ARM_H__ | |
19 | #define __ARM64_KVM_ARM_H__ | |
20 | ||
6e53031e | 21 | #include <asm/esr.h> |
286fb1cc | 22 | #include <asm/memory.h> |
0369f6a3 MZ |
23 | #include <asm/types.h> |
24 | ||
25 | /* Hyp Configuration Register (HCR) bits */ | |
558daf69 DG |
26 | #define HCR_TEA (UL(1) << 37) |
27 | #define HCR_TERR (UL(1) << 36) | |
68908bf7 | 28 | #define HCR_E2H (UL(1) << 34) |
0369f6a3 MZ |
29 | #define HCR_ID (UL(1) << 33) |
30 | #define HCR_CD (UL(1) << 32) | |
31 | #define HCR_RW_SHIFT 31 | |
32 | #define HCR_RW (UL(1) << HCR_RW_SHIFT) | |
33 | #define HCR_TRVM (UL(1) << 30) | |
34 | #define HCR_HCD (UL(1) << 29) | |
35 | #define HCR_TDZ (UL(1) << 28) | |
36 | #define HCR_TGE (UL(1) << 27) | |
37 | #define HCR_TVM (UL(1) << 26) | |
38 | #define HCR_TTLB (UL(1) << 25) | |
39 | #define HCR_TPU (UL(1) << 24) | |
40 | #define HCR_TPC (UL(1) << 23) | |
41 | #define HCR_TSW (UL(1) << 22) | |
42 | #define HCR_TAC (UL(1) << 21) | |
43 | #define HCR_TIDCP (UL(1) << 20) | |
44 | #define HCR_TSC (UL(1) << 19) | |
45 | #define HCR_TID3 (UL(1) << 18) | |
46 | #define HCR_TID2 (UL(1) << 17) | |
47 | #define HCR_TID1 (UL(1) << 16) | |
48 | #define HCR_TID0 (UL(1) << 15) | |
49 | #define HCR_TWE (UL(1) << 14) | |
50 | #define HCR_TWI (UL(1) << 13) | |
51 | #define HCR_DC (UL(1) << 12) | |
52 | #define HCR_BSU (3 << 10) | |
53 | #define HCR_BSU_IS (UL(1) << 10) | |
54 | #define HCR_FB (UL(1) << 9) | |
7b17145e | 55 | #define HCR_VSE (UL(1) << 8) |
0369f6a3 MZ |
56 | #define HCR_VI (UL(1) << 7) |
57 | #define HCR_VF (UL(1) << 6) | |
58 | #define HCR_AMO (UL(1) << 5) | |
59 | #define HCR_IMO (UL(1) << 4) | |
60 | #define HCR_FMO (UL(1) << 3) | |
61 | #define HCR_PTW (UL(1) << 2) | |
62 | #define HCR_SWIO (UL(1) << 1) | |
63 | #define HCR_VM (UL(1) << 0) | |
64 | ||
65 | /* | |
66 | * The bits we set in HCR: | |
ef769e32 | 67 | * RW: 64bit by default, can be overridden for 32bit VMs |
0369f6a3 MZ |
68 | * TAC: Trap ACTLR |
69 | * TSC: Trap SMC | |
4d44923b | 70 | * TVM: Trap VM ops (until M+C set in SCTLR_EL1) |
0369f6a3 | 71 | * TSW: Trap cache operations by set/way |
d241aac7 | 72 | * TWE: Trap WFE |
0369f6a3 MZ |
73 | * TWI: Trap WFI |
74 | * TIDCP: Trap L2CTLR/L2ECTLR | |
75 | * BSU_IS: Upgrade barriers to the inner shareable domain | |
76 | * FB: Force broadcast of all maintainance operations | |
77 | * AMO: Override CPSR.A and enable signaling with VA | |
78 | * IMO: Override CPSR.I and enable signaling with VI | |
79 | * FMO: Override CPSR.F and enable signaling with VF | |
80 | * SWIO: Turn set/way invalidates into set/way clean+invalidate | |
81 | */ | |
d241aac7 | 82 | #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \ |
4d44923b | 83 | HCR_TVM | HCR_BSU_IS | HCR_FB | HCR_TAC | \ |
ac3c3747 | 84 | HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW) |
7b17145e | 85 | #define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF) |
ac3c3747 | 86 | #define HCR_INT_OVERRIDE (HCR_FMO | HCR_IMO) |
68908bf7 | 87 | #define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H) |
0369f6a3 | 88 | |
0369f6a3 | 89 | /* TCR_EL2 Registers bits */ |
a563f759 SP |
90 | #define TCR_EL2_RES1 ((1 << 31) | (1 << 23)) |
91 | #define TCR_EL2_TBI (1 << 20) | |
92 | #define TCR_EL2_PS_SHIFT 16 | |
93 | #define TCR_EL2_PS_MASK (7 << TCR_EL2_PS_SHIFT) | |
94 | #define TCR_EL2_PS_40B (2 << TCR_EL2_PS_SHIFT) | |
95 | #define TCR_EL2_TG0_MASK TCR_TG0_MASK | |
96 | #define TCR_EL2_SH0_MASK TCR_SH0_MASK | |
97 | #define TCR_EL2_ORGN0_MASK TCR_ORGN0_MASK | |
98 | #define TCR_EL2_IRGN0_MASK TCR_IRGN0_MASK | |
99 | #define TCR_EL2_T0SZ_MASK 0x3f | |
100 | #define TCR_EL2_MASK (TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \ | |
101 | TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK) | |
0369f6a3 | 102 | |
0369f6a3 | 103 | /* VTCR_EL2 Registers bits */ |
857d1a97 | 104 | #define VTCR_EL2_RES1 (1 << 31) |
06485053 CM |
105 | #define VTCR_EL2_HD (1 << 22) |
106 | #define VTCR_EL2_HA (1 << 21) | |
a563f759 SP |
107 | #define VTCR_EL2_PS_MASK TCR_EL2_PS_MASK |
108 | #define VTCR_EL2_TG0_MASK TCR_TG0_MASK | |
109 | #define VTCR_EL2_TG0_4K TCR_TG0_4K | |
02e0b760 | 110 | #define VTCR_EL2_TG0_16K TCR_TG0_16K |
a563f759 SP |
111 | #define VTCR_EL2_TG0_64K TCR_TG0_64K |
112 | #define VTCR_EL2_SH0_MASK TCR_SH0_MASK | |
113 | #define VTCR_EL2_SH0_INNER TCR_SH0_INNER | |
114 | #define VTCR_EL2_ORGN0_MASK TCR_ORGN0_MASK | |
115 | #define VTCR_EL2_ORGN0_WBWA TCR_ORGN0_WBWA | |
116 | #define VTCR_EL2_IRGN0_MASK TCR_IRGN0_MASK | |
117 | #define VTCR_EL2_IRGN0_WBWA TCR_IRGN0_WBWA | |
118 | #define VTCR_EL2_SL0_SHIFT 6 | |
119 | #define VTCR_EL2_SL0_MASK (3 << VTCR_EL2_SL0_SHIFT) | |
120 | #define VTCR_EL2_SL0_LVL1 (1 << VTCR_EL2_SL0_SHIFT) | |
0369f6a3 MZ |
121 | #define VTCR_EL2_T0SZ_MASK 0x3f |
122 | #define VTCR_EL2_T0SZ_40B 24 | |
cb678d60 SP |
123 | #define VTCR_EL2_VS_SHIFT 19 |
124 | #define VTCR_EL2_VS_8BIT (0 << VTCR_EL2_VS_SHIFT) | |
125 | #define VTCR_EL2_VS_16BIT (1 << VTCR_EL2_VS_SHIFT) | |
0369f6a3 | 126 | |
dbff124e JS |
127 | /* |
128 | * We configure the Stage-2 page tables to always restrict the IPA space to be | |
129 | * 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are | |
130 | * not known to exist and will break with this configuration. | |
131 | * | |
84ed7412 MZ |
132 | * VTCR_EL2.PS is extracted from ID_AA64MMFR0_EL1.PARange at boot time |
133 | * (see hyp-init.S). | |
134 | * | |
dbff124e | 135 | * Note that when using 4K pages, we concatenate two first level page tables |
02e0b760 | 136 | * together. With 16K pages, we concatenate 16 first level page tables. |
dbff124e JS |
137 | * |
138 | * The magic numbers used for VTTBR_X in this patch can be found in Tables | |
139 | * D4-23 and D4-25 in ARM DDI 0487A.b. | |
140 | */ | |
acd05010 SP |
141 | |
142 | #define VTCR_EL2_T0SZ_IPA VTCR_EL2_T0SZ_40B | |
143 | #define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ | |
144 | VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1) | |
145 | ||
0369f6a3 MZ |
146 | #ifdef CONFIG_ARM64_64K_PAGES |
147 | /* | |
148 | * Stage2 translation configuration: | |
0369f6a3 MZ |
149 | * 64kB pages (TG0 = 1) |
150 | * 2 level page tables (SL = 1) | |
151 | */ | |
acd05010 SP |
152 | #define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_64K | VTCR_EL2_SL0_LVL1) |
153 | #define VTTBR_X_TGRAN_MAGIC 38 | |
02e0b760 SP |
154 | #elif defined(CONFIG_ARM64_16K_PAGES) |
155 | /* | |
156 | * Stage2 translation configuration: | |
157 | * 16kB pages (TG0 = 2) | |
158 | * 2 level page tables (SL = 1) | |
159 | */ | |
160 | #define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_16K | VTCR_EL2_SL0_LVL1) | |
161 | #define VTTBR_X_TGRAN_MAGIC 42 | |
162 | #else /* 4K */ | |
0369f6a3 MZ |
163 | /* |
164 | * Stage2 translation configuration: | |
0369f6a3 MZ |
165 | * 4kB pages (TG0 = 0) |
166 | * 3 level page tables (SL = 1) | |
167 | */ | |
acd05010 SP |
168 | #define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_4K | VTCR_EL2_SL0_LVL1) |
169 | #define VTTBR_X_TGRAN_MAGIC 37 | |
0369f6a3 MZ |
170 | #endif |
171 | ||
acd05010 SP |
172 | #define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN_FLAGS) |
173 | #define VTTBR_X (VTTBR_X_TGRAN_MAGIC - VTCR_EL2_T0SZ_IPA) | |
174 | ||
26aa7b3b | 175 | #define VTTBR_BADDR_MASK (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_X) |
286fb1cc | 176 | #define VTTBR_VMID_SHIFT (UL(48)) |
20475f78 | 177 | #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT) |
0369f6a3 MZ |
178 | |
179 | /* Hyp System Trap Register */ | |
0369f6a3 MZ |
180 | #define HSTR_EL2_T(x) (1 << x) |
181 | ||
edce2292 | 182 | /* Hyp Coprocessor Trap Register Shifts */ |
33c76a0b MS |
183 | #define CPTR_EL2_TFP_SHIFT 10 |
184 | ||
0369f6a3 MZ |
185 | /* Hyp Coprocessor Trap Register */ |
186 | #define CPTR_EL2_TCPAC (1 << 31) | |
187 | #define CPTR_EL2_TTA (1 << 20) | |
33c76a0b | 188 | #define CPTR_EL2_TFP (1 << CPTR_EL2_TFP_SHIFT) |
67236564 | 189 | #define CPTR_EL2_TZ (1 << 8) |
17eed27b DM |
190 | #define CPTR_EL2_RES1 0x000032ff /* known RES1 bits in CPTR_EL2 */ |
191 | #define CPTR_EL2_DEFAULT CPTR_EL2_RES1 | |
0369f6a3 MZ |
192 | |
193 | /* Hyp Debug Configuration Register bits */ | |
f85279b4 WD |
194 | #define MDCR_EL2_TPMS (1 << 14) |
195 | #define MDCR_EL2_E2PB_MASK (UL(0x3)) | |
196 | #define MDCR_EL2_E2PB_SHIFT (UL(12)) | |
0369f6a3 MZ |
197 | #define MDCR_EL2_TDRA (1 << 11) |
198 | #define MDCR_EL2_TDOSA (1 << 10) | |
199 | #define MDCR_EL2_TDA (1 << 9) | |
200 | #define MDCR_EL2_TDE (1 << 8) | |
201 | #define MDCR_EL2_HPME (1 << 7) | |
202 | #define MDCR_EL2_TPM (1 << 6) | |
203 | #define MDCR_EL2_TPMCR (1 << 5) | |
204 | #define MDCR_EL2_HPMN_MASK (0x1F) | |
205 | ||
6e53031e MR |
206 | /* For compatibility with fault code shared with 32-bit */ |
207 | #define FSC_FAULT ESR_ELx_FSC_FAULT | |
35307b9a | 208 | #define FSC_ACCESS ESR_ELx_FSC_ACCESS |
6e53031e | 209 | #define FSC_PERM ESR_ELx_FSC_PERM |
621f48e4 TB |
210 | #define FSC_SEA ESR_ELx_FSC_EXTABT |
211 | #define FSC_SEA_TTW0 (0x14) | |
212 | #define FSC_SEA_TTW1 (0x15) | |
213 | #define FSC_SEA_TTW2 (0x16) | |
214 | #define FSC_SEA_TTW3 (0x17) | |
215 | #define FSC_SECC (0x18) | |
216 | #define FSC_SECC_TTW0 (0x1c) | |
217 | #define FSC_SECC_TTW1 (0x1d) | |
218 | #define FSC_SECC_TTW2 (0x1e) | |
219 | #define FSC_SECC_TTW3 (0x1f) | |
0369f6a3 MZ |
220 | |
221 | /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */ | |
286fb1cc | 222 | #define HPFAR_MASK (~UL(0xf)) |
0369f6a3 | 223 | |
b5905dc1 CD |
224 | #define kvm_arm_exception_type \ |
225 | {0, "IRQ" }, \ | |
226 | {1, "TRAP" } | |
227 | ||
228 | #define ECN(x) { ESR_ELx_EC_##x, #x } | |
229 | ||
230 | #define kvm_arm_exception_class \ | |
231 | ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \ | |
232 | ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(CP14_64), ECN(SVC64), \ | |
233 | ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(IMP_DEF), ECN(IABT_LOW), \ | |
234 | ECN(IABT_CUR), ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \ | |
235 | ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \ | |
236 | ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \ | |
237 | ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \ | |
238 | ECN(BKPT32), ECN(VECTOR32), ECN(BRK64) | |
239 | ||
32876224 MZ |
240 | #define CPACR_EL1_FPEN (3 << 20) |
241 | #define CPACR_EL1_TTA (1 << 28) | |
17eed27b | 242 | #define CPACR_EL1_DEFAULT (CPACR_EL1_FPEN | CPACR_EL1_ZEN_EL1EN) |
32876224 | 243 | |
0369f6a3 | 244 | #endif /* __ARM64_KVM_ARM_H__ */ |