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0369f6a3 MZ |
1 | /* |
2 | * Copyright (C) 2012,2013 - ARM Ltd | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #ifndef __ARM64_KVM_ARM_H__ | |
19 | #define __ARM64_KVM_ARM_H__ | |
20 | ||
6e53031e | 21 | #include <asm/esr.h> |
286fb1cc | 22 | #include <asm/memory.h> |
0369f6a3 MZ |
23 | #include <asm/types.h> |
24 | ||
25 | /* Hyp Configuration Register (HCR) bits */ | |
26 | #define HCR_ID (UL(1) << 33) | |
27 | #define HCR_CD (UL(1) << 32) | |
28 | #define HCR_RW_SHIFT 31 | |
29 | #define HCR_RW (UL(1) << HCR_RW_SHIFT) | |
30 | #define HCR_TRVM (UL(1) << 30) | |
31 | #define HCR_HCD (UL(1) << 29) | |
32 | #define HCR_TDZ (UL(1) << 28) | |
33 | #define HCR_TGE (UL(1) << 27) | |
34 | #define HCR_TVM (UL(1) << 26) | |
35 | #define HCR_TTLB (UL(1) << 25) | |
36 | #define HCR_TPU (UL(1) << 24) | |
37 | #define HCR_TPC (UL(1) << 23) | |
38 | #define HCR_TSW (UL(1) << 22) | |
39 | #define HCR_TAC (UL(1) << 21) | |
40 | #define HCR_TIDCP (UL(1) << 20) | |
41 | #define HCR_TSC (UL(1) << 19) | |
42 | #define HCR_TID3 (UL(1) << 18) | |
43 | #define HCR_TID2 (UL(1) << 17) | |
44 | #define HCR_TID1 (UL(1) << 16) | |
45 | #define HCR_TID0 (UL(1) << 15) | |
46 | #define HCR_TWE (UL(1) << 14) | |
47 | #define HCR_TWI (UL(1) << 13) | |
48 | #define HCR_DC (UL(1) << 12) | |
49 | #define HCR_BSU (3 << 10) | |
50 | #define HCR_BSU_IS (UL(1) << 10) | |
51 | #define HCR_FB (UL(1) << 9) | |
52 | #define HCR_VA (UL(1) << 8) | |
53 | #define HCR_VI (UL(1) << 7) | |
54 | #define HCR_VF (UL(1) << 6) | |
55 | #define HCR_AMO (UL(1) << 5) | |
56 | #define HCR_IMO (UL(1) << 4) | |
57 | #define HCR_FMO (UL(1) << 3) | |
58 | #define HCR_PTW (UL(1) << 2) | |
59 | #define HCR_SWIO (UL(1) << 1) | |
60 | #define HCR_VM (UL(1) << 0) | |
61 | ||
62 | /* | |
63 | * The bits we set in HCR: | |
64 | * RW: 64bit by default, can be overriden for 32bit VMs | |
65 | * TAC: Trap ACTLR | |
66 | * TSC: Trap SMC | |
4d44923b | 67 | * TVM: Trap VM ops (until M+C set in SCTLR_EL1) |
0369f6a3 | 68 | * TSW: Trap cache operations by set/way |
d241aac7 | 69 | * TWE: Trap WFE |
0369f6a3 MZ |
70 | * TWI: Trap WFI |
71 | * TIDCP: Trap L2CTLR/L2ECTLR | |
72 | * BSU_IS: Upgrade barriers to the inner shareable domain | |
73 | * FB: Force broadcast of all maintainance operations | |
74 | * AMO: Override CPSR.A and enable signaling with VA | |
75 | * IMO: Override CPSR.I and enable signaling with VI | |
76 | * FMO: Override CPSR.F and enable signaling with VF | |
77 | * SWIO: Turn set/way invalidates into set/way clean+invalidate | |
78 | */ | |
d241aac7 | 79 | #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \ |
4d44923b | 80 | HCR_TVM | HCR_BSU_IS | HCR_FB | HCR_TAC | \ |
ac3c3747 | 81 | HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW) |
0369f6a3 | 82 | #define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF) |
ac3c3747 MZ |
83 | #define HCR_INT_OVERRIDE (HCR_FMO | HCR_IMO) |
84 | ||
0369f6a3 MZ |
85 | |
86 | /* Hyp System Control Register (SCTLR_EL2) bits */ | |
87 | #define SCTLR_EL2_EE (1 << 25) | |
88 | #define SCTLR_EL2_WXN (1 << 19) | |
89 | #define SCTLR_EL2_I (1 << 12) | |
90 | #define SCTLR_EL2_SA (1 << 3) | |
91 | #define SCTLR_EL2_C (1 << 2) | |
92 | #define SCTLR_EL2_A (1 << 1) | |
93 | #define SCTLR_EL2_M 1 | |
94 | #define SCTLR_EL2_FLAGS (SCTLR_EL2_M | SCTLR_EL2_A | SCTLR_EL2_C | \ | |
95 | SCTLR_EL2_SA | SCTLR_EL2_I) | |
96 | ||
97 | /* TCR_EL2 Registers bits */ | |
857d1a97 | 98 | #define TCR_EL2_RES1 ((1 << 31) | (1 << 23)) |
0369f6a3 MZ |
99 | #define TCR_EL2_TBI (1 << 20) |
100 | #define TCR_EL2_PS (7 << 16) | |
101 | #define TCR_EL2_PS_40B (2 << 16) | |
102 | #define TCR_EL2_TG0 (1 << 14) | |
103 | #define TCR_EL2_SH0 (3 << 12) | |
104 | #define TCR_EL2_ORGN0 (3 << 10) | |
105 | #define TCR_EL2_IRGN0 (3 << 8) | |
106 | #define TCR_EL2_T0SZ 0x3f | |
107 | #define TCR_EL2_MASK (TCR_EL2_TG0 | TCR_EL2_SH0 | \ | |
108 | TCR_EL2_ORGN0 | TCR_EL2_IRGN0 | TCR_EL2_T0SZ) | |
109 | ||
857d1a97 | 110 | #define TCR_EL2_FLAGS (TCR_EL2_RES1 | TCR_EL2_PS_40B) |
0369f6a3 MZ |
111 | |
112 | /* VTCR_EL2 Registers bits */ | |
857d1a97 | 113 | #define VTCR_EL2_RES1 (1 << 31) |
0369f6a3 | 114 | #define VTCR_EL2_PS_MASK (7 << 16) |
0369f6a3 MZ |
115 | #define VTCR_EL2_TG0_MASK (1 << 14) |
116 | #define VTCR_EL2_TG0_4K (0 << 14) | |
117 | #define VTCR_EL2_TG0_64K (1 << 14) | |
118 | #define VTCR_EL2_SH0_MASK (3 << 12) | |
119 | #define VTCR_EL2_SH0_INNER (3 << 12) | |
120 | #define VTCR_EL2_ORGN0_MASK (3 << 10) | |
121 | #define VTCR_EL2_ORGN0_WBWA (1 << 10) | |
122 | #define VTCR_EL2_IRGN0_MASK (3 << 8) | |
123 | #define VTCR_EL2_IRGN0_WBWA (1 << 8) | |
124 | #define VTCR_EL2_SL0_MASK (3 << 6) | |
125 | #define VTCR_EL2_SL0_LVL1 (1 << 6) | |
126 | #define VTCR_EL2_T0SZ_MASK 0x3f | |
127 | #define VTCR_EL2_T0SZ_40B 24 | |
128 | ||
dbff124e JS |
129 | /* |
130 | * We configure the Stage-2 page tables to always restrict the IPA space to be | |
131 | * 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are | |
132 | * not known to exist and will break with this configuration. | |
133 | * | |
84ed7412 MZ |
134 | * VTCR_EL2.PS is extracted from ID_AA64MMFR0_EL1.PARange at boot time |
135 | * (see hyp-init.S). | |
136 | * | |
dbff124e JS |
137 | * Note that when using 4K pages, we concatenate two first level page tables |
138 | * together. | |
139 | * | |
140 | * The magic numbers used for VTTBR_X in this patch can be found in Tables | |
141 | * D4-23 and D4-25 in ARM DDI 0487A.b. | |
142 | */ | |
0369f6a3 MZ |
143 | #ifdef CONFIG_ARM64_64K_PAGES |
144 | /* | |
145 | * Stage2 translation configuration: | |
0369f6a3 MZ |
146 | * 40bits input (T0SZ = 24) |
147 | * 64kB pages (TG0 = 1) | |
148 | * 2 level page tables (SL = 1) | |
149 | */ | |
87366d8c RMC |
150 | #define VTCR_EL2_FLAGS (VTCR_EL2_TG0_64K | VTCR_EL2_SH0_INNER | \ |
151 | VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \ | |
857d1a97 MR |
152 | VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B | \ |
153 | VTCR_EL2_RES1) | |
0369f6a3 MZ |
154 | #define VTTBR_X (38 - VTCR_EL2_T0SZ_40B) |
155 | #else | |
156 | /* | |
157 | * Stage2 translation configuration: | |
0369f6a3 MZ |
158 | * 40bits input (T0SZ = 24) |
159 | * 4kB pages (TG0 = 0) | |
160 | * 3 level page tables (SL = 1) | |
161 | */ | |
87366d8c RMC |
162 | #define VTCR_EL2_FLAGS (VTCR_EL2_TG0_4K | VTCR_EL2_SH0_INNER | \ |
163 | VTCR_EL2_ORGN0_WBWA | VTCR_EL2_IRGN0_WBWA | \ | |
857d1a97 MR |
164 | VTCR_EL2_SL0_LVL1 | VTCR_EL2_T0SZ_40B | \ |
165 | VTCR_EL2_RES1) | |
0369f6a3 MZ |
166 | #define VTTBR_X (37 - VTCR_EL2_T0SZ_40B) |
167 | #endif | |
168 | ||
169 | #define VTTBR_BADDR_SHIFT (VTTBR_X - 1) | |
286fb1cc GL |
170 | #define VTTBR_BADDR_MASK (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT) |
171 | #define VTTBR_VMID_SHIFT (UL(48)) | |
172 | #define VTTBR_VMID_MASK (UL(0xFF) << VTTBR_VMID_SHIFT) | |
0369f6a3 MZ |
173 | |
174 | /* Hyp System Trap Register */ | |
175 | #define HSTR_EL2_TTEE (1 << 16) | |
176 | #define HSTR_EL2_T(x) (1 << x) | |
177 | ||
33c76a0b MS |
178 | /* Hyp Coproccessor Trap Register Shifts */ |
179 | #define CPTR_EL2_TFP_SHIFT 10 | |
180 | ||
0369f6a3 MZ |
181 | /* Hyp Coprocessor Trap Register */ |
182 | #define CPTR_EL2_TCPAC (1 << 31) | |
183 | #define CPTR_EL2_TTA (1 << 20) | |
33c76a0b | 184 | #define CPTR_EL2_TFP (1 << CPTR_EL2_TFP_SHIFT) |
0369f6a3 MZ |
185 | |
186 | /* Hyp Debug Configuration Register bits */ | |
187 | #define MDCR_EL2_TDRA (1 << 11) | |
188 | #define MDCR_EL2_TDOSA (1 << 10) | |
189 | #define MDCR_EL2_TDA (1 << 9) | |
190 | #define MDCR_EL2_TDE (1 << 8) | |
191 | #define MDCR_EL2_HPME (1 << 7) | |
192 | #define MDCR_EL2_TPM (1 << 6) | |
193 | #define MDCR_EL2_TPMCR (1 << 5) | |
194 | #define MDCR_EL2_HPMN_MASK (0x1F) | |
195 | ||
6e53031e MR |
196 | /* For compatibility with fault code shared with 32-bit */ |
197 | #define FSC_FAULT ESR_ELx_FSC_FAULT | |
35307b9a | 198 | #define FSC_ACCESS ESR_ELx_FSC_ACCESS |
6e53031e | 199 | #define FSC_PERM ESR_ELx_FSC_PERM |
0369f6a3 MZ |
200 | |
201 | /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */ | |
286fb1cc | 202 | #define HPFAR_MASK (~UL(0xf)) |
0369f6a3 | 203 | |
0369f6a3 | 204 | #endif /* __ARM64_KVM_ARM_H__ */ |