[mirror_ubuntu-zesty-kernel.git] / arch / arm64 / include / asm / kvm_arm.h

/*
 * Copyright (C) 2012,2013 - ARM Ltd
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __ARM64_KVM_ARM_H__
#define __ARM64_KVM_ARM_H__

#include <asm/esr.h>
#include <asm/memory.h>
#include <asm/types.h>

/* Hyp Configuration Register (HCR) bits */
#define HCR_E2H		(UL(1) << 34)
#define HCR_ID		(UL(1) << 33)
#define HCR_CD		(UL(1) << 32)
#define HCR_RW_SHIFT	31
#define HCR_RW		(UL(1) << HCR_RW_SHIFT)
#define HCR_TRVM	(UL(1) << 30)
#define HCR_HCD		(UL(1) << 29)
#define HCR_TDZ		(UL(1) << 28)
#define HCR_TGE		(UL(1) << 27)
#define HCR_TVM		(UL(1) << 26)
#define HCR_TTLB	(UL(1) << 25)
#define HCR_TPU		(UL(1) << 24)
#define HCR_TPC		(UL(1) << 23)
#define HCR_TSW		(UL(1) << 22)
#define HCR_TAC		(UL(1) << 21)
#define HCR_TIDCP	(UL(1) << 20)
#define HCR_TSC		(UL(1) << 19)
#define HCR_TID3	(UL(1) << 18)
#define HCR_TID2	(UL(1) << 17)
#define HCR_TID1	(UL(1) << 16)
#define HCR_TID0	(UL(1) << 15)
#define HCR_TWE		(UL(1) << 14)
#define HCR_TWI		(UL(1) << 13)
#define HCR_DC		(UL(1) << 12)
#define HCR_BSU		(3 << 10)
#define HCR_BSU_IS	(UL(1) << 10)
#define HCR_FB		(UL(1) << 9)
#define HCR_VSE		(UL(1) << 8)
#define HCR_VI		(UL(1) << 7)
#define HCR_VF		(UL(1) << 6)
#define HCR_AMO		(UL(1) << 5)
#define HCR_IMO		(UL(1) << 4)
#define HCR_FMO		(UL(1) << 3)
#define HCR_PTW		(UL(1) << 2)
#define HCR_SWIO	(UL(1) << 1)
#define HCR_VM		(UL(1) << 0)

/*
 * The bits we set in HCR:
 * RW:		64bit by default, can be overridden for 32bit VMs
 * TAC:		Trap ACTLR
 * TSC:		Trap SMC
 * TVM:		Trap VM ops (until M+C set in SCTLR_EL1)
 * TSW:		Trap cache operations by set/way
 * TWE:		Trap WFE
 * TWI:		Trap WFI
 * TIDCP:	Trap L2CTLR/L2ECTLR
 * BSU_IS:	Upgrade barriers to the inner shareable domain
 * FB:		Force broadcast of all maintainance operations
 * AMO:		Override CPSR.A and enable signaling with VA
 * IMO:		Override CPSR.I and enable signaling with VI
 * FMO:		Override CPSR.F and enable signaling with VF
 * SWIO:	Turn set/way invalidates into set/way clean+invalidate
 */
#define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
			 HCR_TVM | HCR_BSU_IS | HCR_FB | HCR_TAC | \
			 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW)
#define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF)
#define HCR_INT_OVERRIDE   (HCR_FMO | HCR_IMO)
#define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)

/* TCR_EL2 Registers bits */
#define TCR_EL2_RES1		((1 << 31) | (1 << 23))
#define TCR_EL2_TBI		(1 << 20)
#define TCR_EL2_PS_SHIFT	16
#define TCR_EL2_PS_MASK		(7 << TCR_EL2_PS_SHIFT)
#define TCR_EL2_PS_40B		(2 << TCR_EL2_PS_SHIFT)
#define TCR_EL2_TG0_MASK	TCR_TG0_MASK
#define TCR_EL2_SH0_MASK	TCR_SH0_MASK
#define TCR_EL2_ORGN0_MASK	TCR_ORGN0_MASK
#define TCR_EL2_IRGN0_MASK	TCR_IRGN0_MASK
#define TCR_EL2_T0SZ_MASK	0x3f
#define TCR_EL2_MASK	(TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \
			 TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK)

/* VTCR_EL2 Registers bits */
#define VTCR_EL2_RES1		(1 << 31)
#define VTCR_EL2_HD		(1 << 22)
#define VTCR_EL2_HA		(1 << 21)
#define VTCR_EL2_PS_MASK	TCR_EL2_PS_MASK
#define VTCR_EL2_TG0_MASK	TCR_TG0_MASK
#define VTCR_EL2_TG0_4K		TCR_TG0_4K
#define VTCR_EL2_TG0_16K	TCR_TG0_16K
#define VTCR_EL2_TG0_64K	TCR_TG0_64K
#define VTCR_EL2_SH0_MASK	TCR_SH0_MASK
#define VTCR_EL2_SH0_INNER	TCR_SH0_INNER
#define VTCR_EL2_ORGN0_MASK	TCR_ORGN0_MASK
#define VTCR_EL2_ORGN0_WBWA	TCR_ORGN0_WBWA
#define VTCR_EL2_IRGN0_MASK	TCR_IRGN0_MASK
#define VTCR_EL2_IRGN0_WBWA	TCR_IRGN0_WBWA
#define VTCR_EL2_SL0_SHIFT	6
#define VTCR_EL2_SL0_MASK	(3 << VTCR_EL2_SL0_SHIFT)
#define VTCR_EL2_SL0_LVL1	(1 << VTCR_EL2_SL0_SHIFT)
#define VTCR_EL2_T0SZ_MASK	0x3f
#define VTCR_EL2_T0SZ_40B	24
#define VTCR_EL2_VS_SHIFT	19
#define VTCR_EL2_VS_8BIT	(0 << VTCR_EL2_VS_SHIFT)
#define VTCR_EL2_VS_16BIT	(1 << VTCR_EL2_VS_SHIFT)

/*
 * We configure the Stage-2 page tables to always restrict the IPA space to be
 * 40 bits wide (T0SZ = 24).  Systems with a PARange smaller than 40 bits are
 * not known to exist and will break with this configuration.
 *
 * VTCR_EL2.PS is extracted from ID_AA64MMFR0_EL1.PARange at boot time
 * (see hyp-init.S).
 *
 * Note that when using 4K pages, we concatenate two first level page tables
 * together. With 16K pages, we concatenate 16 first level page tables.
 *
 * The magic numbers used for VTTBR_X in this patch can be found in Tables
 * D4-23 and D4-25 in ARM DDI 0487A.b.
 */

#define VTCR_EL2_T0SZ_IPA	VTCR_EL2_T0SZ_40B
#define VTCR_EL2_COMMON_BITS	(VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \
				 VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1)

#ifdef CONFIG_ARM64_64K_PAGES
/*
 * Stage2 translation configuration:
 * 64kB pages (TG0 = 1)
 * 2 level page tables (SL = 1)
 */
#define VTCR_EL2_TGRAN_FLAGS		(VTCR_EL2_TG0_64K | VTCR_EL2_SL0_LVL1)
#define VTTBR_X_TGRAN_MAGIC		38
#elif defined(CONFIG_ARM64_16K_PAGES)
/*
 * Stage2 translation configuration:
 * 16kB pages (TG0 = 2)
 * 2 level page tables (SL = 1)
 */
#define VTCR_EL2_TGRAN_FLAGS		(VTCR_EL2_TG0_16K | VTCR_EL2_SL0_LVL1)
#define VTTBR_X_TGRAN_MAGIC		42
#else	/* 4K */
/*
 * Stage2 translation configuration:
 * 4kB pages (TG0 = 0)
 * 3 level page tables (SL = 1)
 */
#define VTCR_EL2_TGRAN_FLAGS		(VTCR_EL2_TG0_4K | VTCR_EL2_SL0_LVL1)
#define VTTBR_X_TGRAN_MAGIC		37
#endif

#define VTCR_EL2_FLAGS			(VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN_FLAGS)
#define VTTBR_X				(VTTBR_X_TGRAN_MAGIC - VTCR_EL2_T0SZ_IPA)

#define VTTBR_BADDR_SHIFT (VTTBR_X - 1)
#define VTTBR_BADDR_MASK  (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT)
#define VTTBR_VMID_SHIFT  (UL(48))
#define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)

/* Hyp System Trap Register */
#define HSTR_EL2_T(x)	(1 << x)

/* Hyp Coprocessor Trap Register Shifts */
#define CPTR_EL2_TFP_SHIFT 10

/* Hyp Coprocessor Trap Register */
#define CPTR_EL2_TCPAC	(1 << 31)
#define CPTR_EL2_TTA	(1 << 20)
#define CPTR_EL2_TFP	(1 << CPTR_EL2_TFP_SHIFT)
#define CPTR_EL2_DEFAULT	0x000033ff

/* Hyp Debug Configuration Register bits */
#define MDCR_EL2_TDRA		(1 << 11)
#define MDCR_EL2_TDOSA		(1 << 10)
#define MDCR_EL2_TDA		(1 << 9)
#define MDCR_EL2_TDE		(1 << 8)
#define MDCR_EL2_HPME		(1 << 7)
#define MDCR_EL2_TPM		(1 << 6)
#define MDCR_EL2_TPMCR		(1 << 5)
#define MDCR_EL2_HPMN_MASK	(0x1F)

/* For compatibility with fault code shared with 32-bit */
#define FSC_FAULT	ESR_ELx_FSC_FAULT
#define FSC_ACCESS	ESR_ELx_FSC_ACCESS
#define FSC_PERM	ESR_ELx_FSC_PERM
#define FSC_SEA		ESR_ELx_FSC_EXTABT
#define FSC_SEA_TTW0	(0x14)
#define FSC_SEA_TTW1	(0x15)
#define FSC_SEA_TTW2	(0x16)
#define FSC_SEA_TTW3	(0x17)
#define FSC_SECC	(0x18)
#define FSC_SECC_TTW0	(0x1c)
#define FSC_SECC_TTW1	(0x1d)
#define FSC_SECC_TTW2	(0x1e)
#define FSC_SECC_TTW3	(0x1f)

/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
#define HPFAR_MASK	(~UL(0xf))

#define kvm_arm_exception_type	\
	{0, "IRQ" }, 		\
	{1, "TRAP" }

#define ECN(x) { ESR_ELx_EC_##x, #x }

#define kvm_arm_exception_class \
	ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \
	ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(CP14_64), ECN(SVC64), \
	ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(IMP_DEF), ECN(IABT_LOW), \
	ECN(IABT_CUR), ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \
	ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \
	ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \
	ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \
	ECN(BKPT32), ECN(VECTOR32), ECN(BRK64)

#define CPACR_EL1_FPEN		(3 << 20)
#define CPACR_EL1_TTA		(1 << 28)

#endif /* __ARM64_KVM_ARM_H__ */
Commit	Line	Data
0369f6a3 MZ	1	/*
	2	* Copyright (C) 2012,2013 - ARM Ltd
	3	* Author: Marc Zyngier <marc.zyngier@arm.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	#ifndef __ARM64_KVM_ARM_H__
	19	#define __ARM64_KVM_ARM_H__
	20
6e53031e	21	#include <asm/esr.h>
286fb1cc	22	#include <asm/memory.h>
0369f6a3 MZ	23	#include <asm/types.h>
	24
	25	/* Hyp Configuration Register (HCR) bits */
68908bf7	26	#define HCR_E2H (UL(1) << 34)
0369f6a3 MZ	27	#define HCR_ID (UL(1) << 33)
	28	#define HCR_CD (UL(1) << 32)
	29	#define HCR_RW_SHIFT 31
	30	#define HCR_RW (UL(1) << HCR_RW_SHIFT)
	31	#define HCR_TRVM (UL(1) << 30)
	32	#define HCR_HCD (UL(1) << 29)
	33	#define HCR_TDZ (UL(1) << 28)
	34	#define HCR_TGE (UL(1) << 27)
	35	#define HCR_TVM (UL(1) << 26)
	36	#define HCR_TTLB (UL(1) << 25)
	37	#define HCR_TPU (UL(1) << 24)
	38	#define HCR_TPC (UL(1) << 23)
	39	#define HCR_TSW (UL(1) << 22)
	40	#define HCR_TAC (UL(1) << 21)
	41	#define HCR_TIDCP (UL(1) << 20)
	42	#define HCR_TSC (UL(1) << 19)
	43	#define HCR_TID3 (UL(1) << 18)
	44	#define HCR_TID2 (UL(1) << 17)
	45	#define HCR_TID1 (UL(1) << 16)
	46	#define HCR_TID0 (UL(1) << 15)
	47	#define HCR_TWE (UL(1) << 14)
	48	#define HCR_TWI (UL(1) << 13)
	49	#define HCR_DC (UL(1) << 12)
	50	#define HCR_BSU (3 << 10)
	51	#define HCR_BSU_IS (UL(1) << 10)
	52	#define HCR_FB (UL(1) << 9)
7b17145e	53	#define HCR_VSE (UL(1) << 8)
0369f6a3 MZ	54	#define HCR_VI (UL(1) << 7)
	55	#define HCR_VF (UL(1) << 6)
	56	#define HCR_AMO (UL(1) << 5)
	57	#define HCR_IMO (UL(1) << 4)
	58	#define HCR_FMO (UL(1) << 3)
	59	#define HCR_PTW (UL(1) << 2)
	60	#define HCR_SWIO (UL(1) << 1)
	61	#define HCR_VM (UL(1) << 0)
	62
	63	/*
	64	* The bits we set in HCR:
ef769e32	65	* RW: 64bit by default, can be overridden for 32bit VMs
0369f6a3 MZ	66	* TAC: Trap ACTLR
0369f6a3 MZ	67	* TSC: Trap SMC
4d44923b	68	* TVM: Trap VM ops (until M+C set in SCTLR_EL1)
0369f6a3	69	* TSW: Trap cache operations by set/way
d241aac7	70	* TWE: Trap WFE
0369f6a3 MZ	71	* TWI: Trap WFI
	72	* TIDCP: Trap L2CTLR/L2ECTLR
	73	* BSU_IS: Upgrade barriers to the inner shareable domain
	74	* FB: Force broadcast of all maintainance operations
	75	* AMO: Override CPSR.A and enable signaling with VA
	76	* IMO: Override CPSR.I and enable signaling with VI
	77	* FMO: Override CPSR.F and enable signaling with VF
	78	* SWIO: Turn set/way invalidates into set/way clean+invalidate
	79	*/
d241aac7	80	#define HCR_GUEST_FLAGS (HCR_TSC \| HCR_TSW \| HCR_TWE \| HCR_TWI \| HCR_VM \| \
4d44923b	81	HCR_TVM \| HCR_BSU_IS \| HCR_FB \| HCR_TAC \| \
ac3c3747	82	HCR_AMO \| HCR_SWIO \| HCR_TIDCP \| HCR_RW)
7b17145e	83	#define HCR_VIRT_EXCP_MASK (HCR_VSE \| HCR_VI \| HCR_VF)
ac3c3747	84	#define HCR_INT_OVERRIDE (HCR_FMO \| HCR_IMO)
68908bf7	85	#define HCR_HOST_VHE_FLAGS (HCR_RW \| HCR_TGE \| HCR_E2H)
0369f6a3	86
0369f6a3	87	/* TCR_EL2 Registers bits */
a563f759 SP	88	#define TCR_EL2_RES1 ((1 << 31) \| (1 << 23))
	89	#define TCR_EL2_TBI (1 << 20)
	90	#define TCR_EL2_PS_SHIFT 16
	91	#define TCR_EL2_PS_MASK (7 << TCR_EL2_PS_SHIFT)
	92	#define TCR_EL2_PS_40B (2 << TCR_EL2_PS_SHIFT)
	93	#define TCR_EL2_TG0_MASK TCR_TG0_MASK
	94	#define TCR_EL2_SH0_MASK TCR_SH0_MASK
	95	#define TCR_EL2_ORGN0_MASK TCR_ORGN0_MASK
	96	#define TCR_EL2_IRGN0_MASK TCR_IRGN0_MASK
	97	#define TCR_EL2_T0SZ_MASK 0x3f
	98	#define TCR_EL2_MASK (TCR_EL2_TG0_MASK \| TCR_EL2_SH0_MASK \| \
	99	TCR_EL2_ORGN0_MASK \| TCR_EL2_IRGN0_MASK \| TCR_EL2_T0SZ_MASK)
0369f6a3	100
0369f6a3	101	/* VTCR_EL2 Registers bits */
857d1a97	102	#define VTCR_EL2_RES1 (1 << 31)
06485053 CM	103	#define VTCR_EL2_HD (1 << 22)
06485053 CM	104	#define VTCR_EL2_HA (1 << 21)
a563f759 SP	105	#define VTCR_EL2_PS_MASK TCR_EL2_PS_MASK
	106	#define VTCR_EL2_TG0_MASK TCR_TG0_MASK
	107	#define VTCR_EL2_TG0_4K TCR_TG0_4K
02e0b760	108	#define VTCR_EL2_TG0_16K TCR_TG0_16K
a563f759 SP	109	#define VTCR_EL2_TG0_64K TCR_TG0_64K
	110	#define VTCR_EL2_SH0_MASK TCR_SH0_MASK
	111	#define VTCR_EL2_SH0_INNER TCR_SH0_INNER
	112	#define VTCR_EL2_ORGN0_MASK TCR_ORGN0_MASK
	113	#define VTCR_EL2_ORGN0_WBWA TCR_ORGN0_WBWA
	114	#define VTCR_EL2_IRGN0_MASK TCR_IRGN0_MASK
	115	#define VTCR_EL2_IRGN0_WBWA TCR_IRGN0_WBWA
	116	#define VTCR_EL2_SL0_SHIFT 6
	117	#define VTCR_EL2_SL0_MASK (3 << VTCR_EL2_SL0_SHIFT)
	118	#define VTCR_EL2_SL0_LVL1 (1 << VTCR_EL2_SL0_SHIFT)
0369f6a3 MZ	119	#define VTCR_EL2_T0SZ_MASK 0x3f
0369f6a3 MZ	120	#define VTCR_EL2_T0SZ_40B 24
cb678d60 SP	121	#define VTCR_EL2_VS_SHIFT 19
	122	#define VTCR_EL2_VS_8BIT (0 << VTCR_EL2_VS_SHIFT)
	123	#define VTCR_EL2_VS_16BIT (1 << VTCR_EL2_VS_SHIFT)
0369f6a3	124
dbff124e JS	125	/*
	126	* We configure the Stage-2 page tables to always restrict the IPA space to be
	127	* 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are
	128	* not known to exist and will break with this configuration.
	129	*
84ed7412 MZ	130	* VTCR_EL2.PS is extracted from ID_AA64MMFR0_EL1.PARange at boot time
	131	* (see hyp-init.S).
	132	*
dbff124e	133	* Note that when using 4K pages, we concatenate two first level page tables
02e0b760	134	* together. With 16K pages, we concatenate 16 first level page tables.
dbff124e JS	135	*
	136	* The magic numbers used for VTTBR_X in this patch can be found in Tables
	137	* D4-23 and D4-25 in ARM DDI 0487A.b.
	138	*/
acd05010 SP	139
	140	#define VTCR_EL2_T0SZ_IPA VTCR_EL2_T0SZ_40B
	141	#define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER \| VTCR_EL2_ORGN0_WBWA \| \
	142	VTCR_EL2_IRGN0_WBWA \| VTCR_EL2_RES1)
	143
0369f6a3 MZ	144	#ifdef CONFIG_ARM64_64K_PAGES
	145	/*
	146	* Stage2 translation configuration:
0369f6a3 MZ	147	* 64kB pages (TG0 = 1)
	148	* 2 level page tables (SL = 1)
	149	*/
acd05010 SP	150	#define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_64K \| VTCR_EL2_SL0_LVL1)
acd05010 SP	151	#define VTTBR_X_TGRAN_MAGIC 38
02e0b760 SP	152	#elif defined(CONFIG_ARM64_16K_PAGES)
	153	/*
	154	* Stage2 translation configuration:
	155	* 16kB pages (TG0 = 2)
	156	* 2 level page tables (SL = 1)
	157	*/
	158	#define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_16K \| VTCR_EL2_SL0_LVL1)
	159	#define VTTBR_X_TGRAN_MAGIC 42
	160	#else /* 4K */
0369f6a3 MZ	161	/*
0369f6a3 MZ	162	* Stage2 translation configuration:
0369f6a3 MZ	163	* 4kB pages (TG0 = 0)
	164	* 3 level page tables (SL = 1)
	165	*/
acd05010 SP	166	#define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_4K \| VTCR_EL2_SL0_LVL1)
acd05010 SP	167	#define VTTBR_X_TGRAN_MAGIC 37
0369f6a3 MZ	168	#endif
0369f6a3 MZ	169
acd05010 SP	170	#define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS \| VTCR_EL2_TGRAN_FLAGS)
	171	#define VTTBR_X (VTTBR_X_TGRAN_MAGIC - VTCR_EL2_T0SZ_IPA)
	172
0369f6a3	173	#define VTTBR_BADDR_SHIFT (VTTBR_X - 1)
286fb1cc GL	174	#define VTTBR_BADDR_MASK (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT)
286fb1cc GL	175	#define VTTBR_VMID_SHIFT (UL(48))
20475f78	176	#define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)
0369f6a3 MZ	177
0369f6a3 MZ	178	/* Hyp System Trap Register */
0369f6a3 MZ	179	#define HSTR_EL2_T(x) (1 << x)
0369f6a3 MZ	180
edce2292	181	/* Hyp Coprocessor Trap Register Shifts */
33c76a0b MS	182	#define CPTR_EL2_TFP_SHIFT 10
33c76a0b MS	183
0369f6a3 MZ	184	/* Hyp Coprocessor Trap Register */
	185	#define CPTR_EL2_TCPAC (1 << 31)
	186	#define CPTR_EL2_TTA (1 << 20)
33c76a0b	187	#define CPTR_EL2_TFP (1 << CPTR_EL2_TFP_SHIFT)
a7e0ac29	188	#define CPTR_EL2_DEFAULT 0x000033ff
0369f6a3 MZ	189
	190	/* Hyp Debug Configuration Register bits */
	191	#define MDCR_EL2_TDRA (1 << 11)
	192	#define MDCR_EL2_TDOSA (1 << 10)
	193	#define MDCR_EL2_TDA (1 << 9)
	194	#define MDCR_EL2_TDE (1 << 8)
	195	#define MDCR_EL2_HPME (1 << 7)
	196	#define MDCR_EL2_TPM (1 << 6)
	197	#define MDCR_EL2_TPMCR (1 << 5)
	198	#define MDCR_EL2_HPMN_MASK (0x1F)
	199
6e53031e MR	200	/* For compatibility with fault code shared with 32-bit */
6e53031e MR	201	#define FSC_FAULT ESR_ELx_FSC_FAULT
35307b9a	202	#define FSC_ACCESS ESR_ELx_FSC_ACCESS
6e53031e	203	#define FSC_PERM ESR_ELx_FSC_PERM
6633b457 TB	204	#define FSC_SEA ESR_ELx_FSC_EXTABT
	205	#define FSC_SEA_TTW0 (0x14)
	206	#define FSC_SEA_TTW1 (0x15)
	207	#define FSC_SEA_TTW2 (0x16)
	208	#define FSC_SEA_TTW3 (0x17)
	209	#define FSC_SECC (0x18)
	210	#define FSC_SECC_TTW0 (0x1c)
	211	#define FSC_SECC_TTW1 (0x1d)
	212	#define FSC_SECC_TTW2 (0x1e)
	213	#define FSC_SECC_TTW3 (0x1f)
0369f6a3 MZ	214
0369f6a3 MZ	215	/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
286fb1cc	216	#define HPFAR_MASK (~UL(0xf))
0369f6a3	217
b5905dc1 CD	218	#define kvm_arm_exception_type \
	219	{0, "IRQ" }, \
	220	{1, "TRAP" }
	221
	222	#define ECN(x) { ESR_ELx_EC_##x, #x }
	223
	224	#define kvm_arm_exception_class \
	225	ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \
	226	ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(CP14_64), ECN(SVC64), \
	227	ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(IMP_DEF), ECN(IABT_LOW), \
	228	ECN(IABT_CUR), ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \
	229	ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \
	230	ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \
	231	ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \
	232	ECN(BKPT32), ECN(VECTOR32), ECN(BRK64)
	233
32876224 MZ	234	#define CPACR_EL1_FPEN (3 << 20)
	235	#define CPACR_EL1_TTA (1 << 28)
	236
0369f6a3	237	#endif /* __ARM64_KVM_ARM_H__ */