[mirror_ubuntu-artful-kernel.git] / arch / arm64 / include / asm / kvm_host.h

/*
 * Copyright (C) 2012,2013 - ARM Ltd
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * Derived from arch/arm/include/asm/kvm_host.h:
 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __ARM64_KVM_HOST_H__
#define __ARM64_KVM_HOST_H__

#include <linux/types.h>
#include <linux/kvm_types.h>
#include <asm/cpufeature.h>
#include <asm/kvm.h>
#include <asm/kvm_asm.h>
#include <asm/kvm_mmio.h>

#define __KVM_HAVE_ARCH_INTC_INITIALIZED

#define KVM_USER_MEM_SLOTS 512
#define KVM_HALT_POLL_NS_DEFAULT 500000

#include <kvm/arm_vgic.h>
#include <kvm/arm_arch_timer.h>
#include <kvm/arm_pmu.h>

#define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS

#define KVM_VCPU_MAX_FEATURES 4

#define KVM_REQ_VCPU_EXIT	(8 | KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)

int __attribute_const__ kvm_target_cpu(void);
int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
int kvm_arch_dev_ioctl_check_extension(struct kvm *kvm, long ext);
void __extended_idmap_trampoline(phys_addr_t boot_pgd, phys_addr_t idmap_start);

struct kvm_arch {
	/* The VMID generation used for the virt. memory system */
	u64    vmid_gen;
	u32    vmid;

	/* 1-level 2nd stage table and lock */
	spinlock_t pgd_lock;
	pgd_t *pgd;

	/* VTTBR value associated with above pgd and vmid */
	u64    vttbr;

	/* The last vcpu id that ran on each physical CPU */
	int __percpu *last_vcpu_ran;

	/* The maximum number of vCPUs depends on the used GIC model */
	int max_vcpus;

	/* Interrupt controller */
	struct vgic_dist	vgic;
};

#define KVM_NR_MEM_OBJS     40

/*
 * We don't want allocation failures within the mmu code, so we preallocate
 * enough memory for a single page fault in a cache.
 */
struct kvm_mmu_memory_cache {
	int nobjs;
	void *objects[KVM_NR_MEM_OBJS];
};

struct kvm_vcpu_fault_info {
	u32 esr_el2;		/* Hyp Syndrom Register */
	u64 far_el2;		/* Hyp Fault Address Register */
	u64 hpfar_el2;		/* Hyp IPA Fault Address Register */
};

/*
 * 0 is reserved as an invalid value.
 * Order should be kept in sync with the save/restore code.
 */
enum vcpu_sysreg {
	__INVALID_SYSREG__,
	MPIDR_EL1,	/* MultiProcessor Affinity Register */
	CSSELR_EL1,	/* Cache Size Selection Register */
	SCTLR_EL1,	/* System Control Register */
	ACTLR_EL1,	/* Auxiliary Control Register */
	CPACR_EL1,	/* Coprocessor Access Control */
	TTBR0_EL1,	/* Translation Table Base Register 0 */
	TTBR1_EL1,	/* Translation Table Base Register 1 */
	TCR_EL1,	/* Translation Control Register */
	ESR_EL1,	/* Exception Syndrome Register */
	AFSR0_EL1,	/* Auxiliary Fault Status Register 0 */
	AFSR1_EL1,	/* Auxiliary Fault Status Register 1 */
	FAR_EL1,	/* Fault Address Register */
	MAIR_EL1,	/* Memory Attribute Indirection Register */
	VBAR_EL1,	/* Vector Base Address Register */
	CONTEXTIDR_EL1,	/* Context ID Register */
	TPIDR_EL0,	/* Thread ID, User R/W */
	TPIDRRO_EL0,	/* Thread ID, User R/O */
	TPIDR_EL1,	/* Thread ID, Privileged */
	AMAIR_EL1,	/* Aux Memory Attribute Indirection Register */
	CNTKCTL_EL1,	/* Timer Control Register (EL1) */
	PAR_EL1,	/* Physical Address Register */
	MDSCR_EL1,	/* Monitor Debug System Control Register */
	MDCCINT_EL1,	/* Monitor Debug Comms Channel Interrupt Enable Reg */

	/* Performance Monitors Registers */
	PMCR_EL0,	/* Control Register */
	PMSELR_EL0,	/* Event Counter Selection Register */
	PMEVCNTR0_EL0,	/* Event Counter Register (0-30) */
	PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
	PMCCNTR_EL0,	/* Cycle Counter Register */
	PMEVTYPER0_EL0,	/* Event Type Register (0-30) */
	PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
	PMCCFILTR_EL0,	/* Cycle Count Filter Register */
	PMCNTENSET_EL0,	/* Count Enable Set Register */
	PMINTENSET_EL1,	/* Interrupt Enable Set Register */
	PMOVSSET_EL0,	/* Overflow Flag Status Set Register */
	PMSWINC_EL0,	/* Software Increment Register */
	PMUSERENR_EL0,	/* User Enable Register */

	/* 32bit specific registers. Keep them at the end of the range */
	DACR32_EL2,	/* Domain Access Control Register */
	IFSR32_EL2,	/* Instruction Fault Status Register */
	FPEXC32_EL2,	/* Floating-Point Exception Control Register */
	DBGVCR32_EL2,	/* Debug Vector Catch Register */

	NR_SYS_REGS	/* Nothing after this line! */
};

/* 32bit mapping */
#define c0_MPIDR	(MPIDR_EL1 * 2)	/* MultiProcessor ID Register */
#define c0_CSSELR	(CSSELR_EL1 * 2)/* Cache Size Selection Register */
#define c1_SCTLR	(SCTLR_EL1 * 2)	/* System Control Register */
#define c1_ACTLR	(ACTLR_EL1 * 2)	/* Auxiliary Control Register */
#define c1_CPACR	(CPACR_EL1 * 2)	/* Coprocessor Access Control */
#define c2_TTBR0	(TTBR0_EL1 * 2)	/* Translation Table Base Register 0 */
#define c2_TTBR0_high	(c2_TTBR0 + 1)	/* TTBR0 top 32 bits */
#define c2_TTBR1	(TTBR1_EL1 * 2)	/* Translation Table Base Register 1 */
#define c2_TTBR1_high	(c2_TTBR1 + 1)	/* TTBR1 top 32 bits */
#define c2_TTBCR	(TCR_EL1 * 2)	/* Translation Table Base Control R. */
#define c3_DACR		(DACR32_EL2 * 2)/* Domain Access Control Register */
#define c5_DFSR		(ESR_EL1 * 2)	/* Data Fault Status Register */
#define c5_IFSR		(IFSR32_EL2 * 2)/* Instruction Fault Status Register */
#define c5_ADFSR	(AFSR0_EL1 * 2)	/* Auxiliary Data Fault Status R */
#define c5_AIFSR	(AFSR1_EL1 * 2)	/* Auxiliary Instr Fault Status R */
#define c6_DFAR		(FAR_EL1 * 2)	/* Data Fault Address Register */
#define c6_IFAR		(c6_DFAR + 1)	/* Instruction Fault Address Register */
#define c7_PAR		(PAR_EL1 * 2)	/* Physical Address Register */
#define c7_PAR_high	(c7_PAR + 1)	/* PAR top 32 bits */
#define c10_PRRR	(MAIR_EL1 * 2)	/* Primary Region Remap Register */
#define c10_NMRR	(c10_PRRR + 1)	/* Normal Memory Remap Register */
#define c12_VBAR	(VBAR_EL1 * 2)	/* Vector Base Address Register */
#define c13_CID		(CONTEXTIDR_EL1 * 2)	/* Context ID Register */
#define c13_TID_URW	(TPIDR_EL0 * 2)	/* Thread ID, User R/W */
#define c13_TID_URO	(TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
#define c13_TID_PRIV	(TPIDR_EL1 * 2)	/* Thread ID, Privileged */
#define c10_AMAIR0	(AMAIR_EL1 * 2)	/* Aux Memory Attr Indirection Reg */
#define c10_AMAIR1	(c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
#define c14_CNTKCTL	(CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */

#define cp14_DBGDSCRext	(MDSCR_EL1 * 2)
#define cp14_DBGBCR0	(DBGBCR0_EL1 * 2)
#define cp14_DBGBVR0	(DBGBVR0_EL1 * 2)
#define cp14_DBGBXVR0	(cp14_DBGBVR0 + 1)
#define cp14_DBGWCR0	(DBGWCR0_EL1 * 2)
#define cp14_DBGWVR0	(DBGWVR0_EL1 * 2)
#define cp14_DBGDCCINT	(MDCCINT_EL1 * 2)

#define NR_COPRO_REGS	(NR_SYS_REGS * 2)

struct kvm_cpu_context {
	struct kvm_regs	gp_regs;
	union {
		u64 sys_regs[NR_SYS_REGS];
		u32 copro[NR_COPRO_REGS];
	};
};

typedef struct kvm_cpu_context kvm_cpu_context_t;

struct kvm_vcpu_arch {
	struct kvm_cpu_context ctxt;

	/* HYP configuration */
	u64 hcr_el2;
	u32 mdcr_el2;

	/* Exception Information */
	struct kvm_vcpu_fault_info fault;

	/* Guest debug state */
	u64 debug_flags;

	/*
	 * We maintain more than a single set of debug registers to support
	 * debugging the guest from the host and to maintain separate host and
	 * guest state during world switches. vcpu_debug_state are the debug
	 * registers of the vcpu as the guest sees them.  host_debug_state are
	 * the host registers which are saved and restored during
	 * world switches. external_debug_state contains the debug
	 * values we want to debug the guest. This is set via the
	 * KVM_SET_GUEST_DEBUG ioctl.
	 *
	 * debug_ptr points to the set of debug registers that should be loaded
	 * onto the hardware when running the guest.
	 */
	struct kvm_guest_debug_arch *debug_ptr;
	struct kvm_guest_debug_arch vcpu_debug_state;
	struct kvm_guest_debug_arch external_debug_state;

	/* Pointer to host CPU context */
	kvm_cpu_context_t *host_cpu_context;
	struct {
		/* {Break,watch}point registers */
		struct kvm_guest_debug_arch regs;
		/* Statistical profiling extension */
		u64 pmscr_el1;
	} host_debug_state;

	/* VGIC state */
	struct vgic_cpu vgic_cpu;
	struct arch_timer_cpu timer_cpu;
	struct kvm_pmu pmu;

	/*
	 * Anything that is not used directly from assembly code goes
	 * here.
	 */

	/*
	 * Guest registers we preserve during guest debugging.
	 *
	 * These shadow registers are updated by the kvm_handle_sys_reg
	 * trap handler if the guest accesses or updates them while we
	 * are using guest debug.
	 */
	struct {
		u32	mdscr_el1;
	} guest_debug_preserved;

	/* vcpu power-off state */
	bool power_off;

	/* Don't run the guest (internal implementation need) */
	bool pause;

	/* IO related fields */
	struct kvm_decode mmio_decode;

	/* Interrupt related fields */
	u64 irq_lines;		/* IRQ and FIQ levels */

	/* Cache some mmu pages needed inside spinlock regions */
	struct kvm_mmu_memory_cache mmu_page_cache;

	/* Target CPU and feature flags */
	int target;
	DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);

	/* Detect first run of a vcpu */
	bool has_run_once;
};

#define vcpu_gp_regs(v)		(&(v)->arch.ctxt.gp_regs)
#define vcpu_sys_reg(v,r)	((v)->arch.ctxt.sys_regs[(r)])
/*
 * CP14 and CP15 live in the same array, as they are backed by the
 * same system registers.
 */
#define vcpu_cp14(v,r)		((v)->arch.ctxt.copro[(r)])
#define vcpu_cp15(v,r)		((v)->arch.ctxt.copro[(r)])

#ifdef CONFIG_CPU_BIG_ENDIAN
#define vcpu_cp15_64_high(v,r)	vcpu_cp15((v),(r))
#define vcpu_cp15_64_low(v,r)	vcpu_cp15((v),(r) + 1)
#else
#define vcpu_cp15_64_high(v,r)	vcpu_cp15((v),(r) + 1)
#define vcpu_cp15_64_low(v,r)	vcpu_cp15((v),(r))
#endif

struct kvm_vm_stat {
	ulong remote_tlb_flush;
};

struct kvm_vcpu_stat {
	u64 halt_successful_poll;
	u64 halt_attempted_poll;
	u64 halt_poll_invalid;
	u64 halt_wakeup;
	u64 hvc_exit_stat;
	u64 wfe_exit_stat;
	u64 wfi_exit_stat;
	u64 mmio_exit_user;
	u64 mmio_exit_kernel;
	u64 exits;
};

int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);

#define KVM_ARCH_WANT_MMU_NOTIFIER
int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
int kvm_unmap_hva_range(struct kvm *kvm,
			unsigned long start, unsigned long end);
void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);

/* We do not have shadow page tables, hence the empty hooks */
static inline void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
							 unsigned long address)
{
}

struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void);
void kvm_arm_halt_guest(struct kvm *kvm);
void kvm_arm_resume_guest(struct kvm *kvm);
void kvm_arm_halt_vcpu(struct kvm_vcpu *vcpu);
void kvm_arm_resume_vcpu(struct kvm_vcpu *vcpu);

u64 __kvm_call_hyp(void *hypfn, ...);
#define kvm_call_hyp(f, ...) __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__)

void force_vm_exit(const cpumask_t *mask);
void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot);

int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
		int exception_index);

int kvm_perf_init(void);
int kvm_perf_teardown(void);

struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);

static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr,
				       unsigned long hyp_stack_ptr,
				       unsigned long vector_ptr)
{
	/*
	 * Call initialization code, and switch to the full blown HYP code.
	 * If the cpucaps haven't been finalized yet, something has gone very
	 * wrong, and hyp will crash and burn when it uses any
	 * cpus_have_const_cap() wrapper.
	 */
	BUG_ON(!static_branch_likely(&arm64_const_caps_ready));
	__kvm_call_hyp((void *)pgd_ptr, hyp_stack_ptr, vector_ptr);
}

static inline void kvm_arch_hardware_unsetup(void) {}
static inline void kvm_arch_sync_events(struct kvm *kvm) {}
static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}

void kvm_arm_init_debug(void);
void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
			       struct kvm_device_attr *attr);
int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
			       struct kvm_device_attr *attr);
int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
			       struct kvm_device_attr *attr);

static inline void __cpu_init_stage2(void)
{
	u32 parange = kvm_call_hyp(__init_stage2_translation);

	WARN_ONCE(parange < 40,
		  "PARange is %d bits, unsupported configuration!", parange);
}

#endif /* __ARM64_KVM_HOST_H__ */
Commit	Line	Data
4f8d6632 MZ	1	/*
	2	* Copyright (C) 2012,2013 - ARM Ltd
	3	* Author: Marc Zyngier <marc.zyngier@arm.com>
	4	*
	5	* Derived from arch/arm/include/asm/kvm_host.h:
	6	* Copyright (C) 2012 - Virtual Open Systems and Columbia University
	7	* Author: Christoffer Dall <c.dall@virtualopensystems.com>
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	20	*/
	21
	22	#ifndef __ARM64_KVM_HOST_H__
	23	#define __ARM64_KVM_HOST_H__
	24
65647300 PB	25	#include <linux/types.h>
65647300 PB	26	#include <linux/kvm_types.h>
63a1e1c9	27	#include <asm/cpufeature.h>
4f8d6632	28	#include <asm/kvm.h>
3a3604bc	29	#include <asm/kvm_asm.h>
4f8d6632 MZ	30	#include <asm/kvm_mmio.h>
4f8d6632 MZ	31
c1426e4c EA	32	#define __KVM_HAVE_ARCH_INTC_INITIALIZED
c1426e4c EA	33
955a3fc6	34	#define KVM_USER_MEM_SLOTS 512
920552b2	35	#define KVM_HALT_POLL_NS_DEFAULT 500000
4f8d6632 MZ	36
	37	#include <kvm/arm_vgic.h>
	38	#include <kvm/arm_arch_timer.h>
04fe4726	39	#include <kvm/arm_pmu.h>
4f8d6632	40
ef748917 ML	41	#define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
ef748917 ML	42
808e7381	43	#define KVM_VCPU_MAX_FEATURES 4
4f8d6632	44
7a97cec2	45	#define KVM_REQ_VCPU_EXIT (8 \| KVM_REQUEST_WAIT \| KVM_REQUEST_NO_WAKEUP)
b13216cf	46
6951e48b	47	int __attribute_const__ kvm_target_cpu(void);
4f8d6632	48	int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
b46f01ce	49	int kvm_arch_dev_ioctl_check_extension(struct kvm *kvm, long ext);
c612505f	50	void __extended_idmap_trampoline(phys_addr_t boot_pgd, phys_addr_t idmap_start);
4f8d6632 MZ	51
	52	struct kvm_arch {
	53	/* The VMID generation used for the virt. memory system */
	54	u64 vmid_gen;
	55	u32 vmid;
	56
	57	/* 1-level 2nd stage table and lock */
	58	spinlock_t pgd_lock;
	59	pgd_t *pgd;
	60
	61	/* VTTBR value associated with above pgd and vmid */
	62	u64 vttbr;
	63
94d0e598 MZ	64	/* The last vcpu id that ran on each physical CPU */
	65	int __percpu *last_vcpu_ran;
	66
3caa2d8c AP	67	/* The maximum number of vCPUs depends on the used GIC model */
	68	int max_vcpus;
	69
4f8d6632 MZ	70	/* Interrupt controller */
4f8d6632 MZ	71	struct vgic_dist vgic;
4f8d6632 MZ	72	};
	73
	74	#define KVM_NR_MEM_OBJS 40
	75
	76	/*
	77	* We don't want allocation failures within the mmu code, so we preallocate
	78	* enough memory for a single page fault in a cache.
	79	*/
	80	struct kvm_mmu_memory_cache {
	81	int nobjs;
	82	void *objects[KVM_NR_MEM_OBJS];
	83	};
	84
	85	struct kvm_vcpu_fault_info {
	86	u32 esr_el2; /* Hyp Syndrom Register */
	87	u64 far_el2; /* Hyp Fault Address Register */
	88	u64 hpfar_el2; /* Hyp IPA Fault Address Register */
	89	};
	90
9d8415d6 MZ	91	/*
	92	* 0 is reserved as an invalid value.
	93	* Order should be kept in sync with the save/restore code.
	94	*/
	95	enum vcpu_sysreg {
	96	__INVALID_SYSREG__,
	97	MPIDR_EL1, /* MultiProcessor Affinity Register */
	98	CSSELR_EL1, /* Cache Size Selection Register */
	99	SCTLR_EL1, /* System Control Register */
	100	ACTLR_EL1, /* Auxiliary Control Register */
	101	CPACR_EL1, /* Coprocessor Access Control */
	102	TTBR0_EL1, /* Translation Table Base Register 0 */
	103	TTBR1_EL1, /* Translation Table Base Register 1 */
	104	TCR_EL1, /* Translation Control Register */
	105	ESR_EL1, /* Exception Syndrome Register */
ef769e32 AB	106	AFSR0_EL1, /* Auxiliary Fault Status Register 0 */
ef769e32 AB	107	AFSR1_EL1, /* Auxiliary Fault Status Register 1 */
9d8415d6 MZ	108	FAR_EL1, /* Fault Address Register */
	109	MAIR_EL1, /* Memory Attribute Indirection Register */
	110	VBAR_EL1, /* Vector Base Address Register */
	111	CONTEXTIDR_EL1, /* Context ID Register */
	112	TPIDR_EL0, /* Thread ID, User R/W */
	113	TPIDRRO_EL0, /* Thread ID, User R/O */
	114	TPIDR_EL1, /* Thread ID, Privileged */
	115	AMAIR_EL1, /* Aux Memory Attribute Indirection Register */
	116	CNTKCTL_EL1, /* Timer Control Register (EL1) */
	117	PAR_EL1, /* Physical Address Register */
	118	MDSCR_EL1, /* Monitor Debug System Control Register */
	119	MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */
	120
ab946834 SZ	121	/* Performance Monitors Registers */
ab946834 SZ	122	PMCR_EL0, /* Control Register */
3965c3ce	123	PMSELR_EL0, /* Event Counter Selection Register */
051ff581 SZ	124	PMEVCNTR0_EL0, /* Event Counter Register (0-30) */
	125	PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
	126	PMCCNTR_EL0, /* Cycle Counter Register */
9feb21ac SZ	127	PMEVTYPER0_EL0, /* Event Type Register (0-30) */
	128	PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
	129	PMCCFILTR_EL0, /* Cycle Count Filter Register */
96b0eebc	130	PMCNTENSET_EL0, /* Count Enable Set Register */
9db52c78	131	PMINTENSET_EL1, /* Interrupt Enable Set Register */
76d883c4	132	PMOVSSET_EL0, /* Overflow Flag Status Set Register */
7a0adc70	133	PMSWINC_EL0, /* Software Increment Register */
d692b8ad	134	PMUSERENR_EL0, /* User Enable Register */
ab946834	135
9d8415d6 MZ	136	/* 32bit specific registers. Keep them at the end of the range */
	137	DACR32_EL2, /* Domain Access Control Register */
	138	IFSR32_EL2, /* Instruction Fault Status Register */
	139	FPEXC32_EL2, /* Floating-Point Exception Control Register */
	140	DBGVCR32_EL2, /* Debug Vector Catch Register */
	141
	142	NR_SYS_REGS /* Nothing after this line! */
	143	};
	144
	145	/* 32bit mapping */
	146	#define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
	147	#define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */
	148	#define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */
	149	#define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */
	150	#define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */
	151	#define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */
	152	#define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */
	153	#define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
	154	#define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */
	155	#define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */
	156	#define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */
	157	#define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */
	158	#define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */
	159	#define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */
	160	#define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */
	161	#define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */
	162	#define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */
	163	#define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */
	164	#define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */
	165	#define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */
	166	#define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */
	167	#define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */
	168	#define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */
	169	#define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */
	170	#define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
	171	#define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */
	172	#define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */
	173	#define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
	174	#define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
	175
	176	#define cp14_DBGDSCRext (MDSCR_EL1 * 2)
	177	#define cp14_DBGBCR0 (DBGBCR0_EL1 * 2)
	178	#define cp14_DBGBVR0 (DBGBVR0_EL1 * 2)
	179	#define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1)
	180	#define cp14_DBGWCR0 (DBGWCR0_EL1 * 2)
	181	#define cp14_DBGWVR0 (DBGWVR0_EL1 * 2)
	182	#define cp14_DBGDCCINT (MDCCINT_EL1 * 2)
	183
	184	#define NR_COPRO_REGS (NR_SYS_REGS * 2)
	185
4f8d6632 MZ	186	struct kvm_cpu_context {
4f8d6632 MZ	187	struct kvm_regs gp_regs;
40033a61 MZ	188	union {
40033a61 MZ	189	u64 sys_regs[NR_SYS_REGS];
72564016	190	u32 copro[NR_COPRO_REGS];
40033a61	191	};
4f8d6632 MZ	192	};
	193
	194	typedef struct kvm_cpu_context kvm_cpu_context_t;
	195
	196	struct kvm_vcpu_arch {
	197	struct kvm_cpu_context ctxt;
	198
	199	/* HYP configuration */
	200	u64 hcr_el2;
56c7f5e7	201	u32 mdcr_el2;
4f8d6632 MZ	202
	203	/* Exception Information */
	204	struct kvm_vcpu_fault_info fault;
	205
84e690bf	206	/* Guest debug state */
0c557ed4 MZ	207	u64 debug_flags;
0c557ed4 MZ	208
84e690bf AB	209	/*
	210	* We maintain more than a single set of debug registers to support
	211	* debugging the guest from the host and to maintain separate host and
	212	* guest state during world switches. vcpu_debug_state are the debug
	213	* registers of the vcpu as the guest sees them. host_debug_state are
834bf887 AB	214	* the host registers which are saved and restored during
	215	* world switches. external_debug_state contains the debug
	216	* values we want to debug the guest. This is set via the
	217	* KVM_SET_GUEST_DEBUG ioctl.
84e690bf AB	218	*
	219	* debug_ptr points to the set of debug registers that should be loaded
	220	* onto the hardware when running the guest.
	221	*/
	222	struct kvm_guest_debug_arch *debug_ptr;
	223	struct kvm_guest_debug_arch vcpu_debug_state;
834bf887	224	struct kvm_guest_debug_arch external_debug_state;
84e690bf	225
4f8d6632 MZ	226	/* Pointer to host CPU context */
4f8d6632 MZ	227	kvm_cpu_context_t *host_cpu_context;
f85279b4 WD	228	struct {
	229	/* {Break,watch}point registers */
	230	struct kvm_guest_debug_arch regs;
	231	/* Statistical profiling extension */
	232	u64 pmscr_el1;
	233	} host_debug_state;
4f8d6632 MZ	234
	235	/* VGIC state */
	236	struct vgic_cpu vgic_cpu;
	237	struct arch_timer_cpu timer_cpu;
04fe4726	238	struct kvm_pmu pmu;
4f8d6632 MZ	239
	240	/*
	241	* Anything that is not used directly from assembly code goes
	242	* here.
	243	*/
4f8d6632	244
337b99bf AB	245	/*
	246	* Guest registers we preserve during guest debugging.
	247	*
	248	* These shadow registers are updated by the kvm_handle_sys_reg
	249	* trap handler if the guest accesses or updates them while we
	250	* are using guest debug.
	251	*/
	252	struct {
	253	u32 mdscr_el1;
	254	} guest_debug_preserved;
	255
3781528e EA	256	/* vcpu power-off state */
3781528e EA	257	bool power_off;
4f8d6632	258
3b92830a EA	259	/* Don't run the guest (internal implementation need) */
	260	bool pause;
	261
4f8d6632 MZ	262	/* IO related fields */
	263	struct kvm_decode mmio_decode;
	264
	265	/* Interrupt related fields */
	266	u64 irq_lines; /* IRQ and FIQ levels */
	267
	268	/* Cache some mmu pages needed inside spinlock regions */
	269	struct kvm_mmu_memory_cache mmu_page_cache;
	270
	271	/* Target CPU and feature flags */
6c8c0c4d	272	int target;
4f8d6632 MZ	273	DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
	274
	275	/* Detect first run of a vcpu */
	276	bool has_run_once;
	277	};
	278
	279	#define vcpu_gp_regs(v) (&(v)->arch.ctxt.gp_regs)
	280	#define vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)])
72564016 MZ	281	/*
	282	* CP14 and CP15 live in the same array, as they are backed by the
	283	* same system registers.
	284	*/
	285	#define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r)])
	286	#define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r)])
4f8d6632	287
f0a3eaff	288	#ifdef CONFIG_CPU_BIG_ENDIAN
dedf97e8 MZ	289	#define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r))
dedf97e8 MZ	290	#define vcpu_cp15_64_low(v,r) vcpu_cp15((v),(r) + 1)
f0a3eaff	291	#else
dedf97e8 MZ	292	#define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r) + 1)
dedf97e8 MZ	293	#define vcpu_cp15_64_low(v,r) vcpu_cp15((v),(r))
f0a3eaff VK	294	#endif
f0a3eaff VK	295
4f8d6632	296	struct kvm_vm_stat {
8a7e75d4	297	ulong remote_tlb_flush;
4f8d6632 MZ	298	};
	299
	300	struct kvm_vcpu_stat {
8a7e75d4 SJS	301	u64 halt_successful_poll;
	302	u64 halt_attempted_poll;
	303	u64 halt_poll_invalid;
	304	u64 halt_wakeup;
	305	u64 hvc_exit_stat;
b19e6892 AT	306	u64 wfe_exit_stat;
	307	u64 wfi_exit_stat;
	308	u64 mmio_exit_user;
	309	u64 mmio_exit_kernel;
	310	u64 exits;
4f8d6632 MZ	311	};
4f8d6632 MZ	312
473bdc0e	313	int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
4f8d6632 MZ	314	unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
4f8d6632 MZ	315	int kvm_arm_copy_reg_indices(struct kvm_vcpu vcpu, u64 __user indices);
4f8d6632 MZ	316	int kvm_arm_get_reg(struct kvm_vcpu vcpu, const struct kvm_one_reg reg);
	317	int kvm_arm_set_reg(struct kvm_vcpu vcpu, const struct kvm_one_reg reg);
	318
	319	#define KVM_ARCH_WANT_MMU_NOTIFIER
4f8d6632 MZ	320	int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
	321	int kvm_unmap_hva_range(struct kvm *kvm,
	322	unsigned long start, unsigned long end);
	323	void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
35307b9a MZ	324	int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
35307b9a MZ	325	int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
4f8d6632 MZ	326
4f8d6632 MZ	327	/* We do not have shadow page tables, hence the empty hooks */
fe71557a TC	328	static inline void kvm_arch_mmu_notifier_invalidate_page(struct kvm *kvm,
	329	unsigned long address)
	330	{
	331	}
	332
4f8d6632	333	struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
4000be42	334	struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void);
b13216cf CD	335	void kvm_arm_halt_guest(struct kvm *kvm);
b13216cf CD	336	void kvm_arm_resume_guest(struct kvm *kvm);
35a2d585 CD	337	void kvm_arm_halt_vcpu(struct kvm_vcpu *vcpu);
35a2d585 CD	338	void kvm_arm_resume_vcpu(struct kvm_vcpu *vcpu);
4f8d6632	339
a0bf9776	340	u64 __kvm_call_hyp(void *hypfn, ...);
22b39ca3 MZ	341	#define kvm_call_hyp(f, ...) __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__)
22b39ca3 MZ	342
cf5d3188	343	void force_vm_exit(const cpumask_t *mask);
8199ed0e	344	void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot);
4f8d6632 MZ	345
	346	int handle_exit(struct kvm_vcpu vcpu, struct kvm_run run,
	347	int exception_index);
	348
	349	int kvm_perf_init(void);
	350	int kvm_perf_teardown(void);
	351
4429fc64 AP	352	struct kvm_vcpu kvm_mpidr_to_vcpu(struct kvm kvm, unsigned long mpidr);
4429fc64 AP	353
12fda812	354	static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr,
092bd143 MZ	355	unsigned long hyp_stack_ptr,
	356	unsigned long vector_ptr)
	357	{
	358	/*
63a1e1c9 MR	359	* Call initialization code, and switch to the full blown HYP code.
	360	* If the cpucaps haven't been finalized yet, something has gone very
	361	* wrong, and hyp will crash and burn when it uses any
	362	* cpus_have_const_cap() wrapper.
092bd143	363	*/
63a1e1c9	364	BUG_ON(!static_branch_likely(&arm64_const_caps_ready));
3421e9d8	365	__kvm_call_hyp((void *)pgd_ptr, hyp_stack_ptr, vector_ptr);
092bd143	366	}
67f69197	367
0865e636 RK	368	static inline void kvm_arch_hardware_unsetup(void) {}
	369	static inline void kvm_arch_sync_events(struct kvm *kvm) {}
	370	static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
	371	static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
3491caf2	372	static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
0865e636	373
56c7f5e7 AB	374	void kvm_arm_init_debug(void);
	375	void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
	376	void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
84e690bf	377	void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
bb0c70bc SZ	378	int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
	379	struct kvm_device_attr *attr);
	380	int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
	381	struct kvm_device_attr *attr);
	382	int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
	383	struct kvm_device_attr *attr);
56c7f5e7	384
21a4179c MZ	385	static inline void __cpu_init_stage2(void)
21a4179c MZ	386	{
6141570c MZ	387	u32 parange = kvm_call_hyp(__init_stage2_translation);
	388
	389	WARN_ONCE(parange < 40,
	390	"PARange is %d bits, unsupported configuration!", parange);
21a4179c MZ	391	}
21a4179c MZ	392
4f8d6632	393	#endif /* __ARM64_KVM_HOST_H__ */