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4f8d6632 MZ |
1 | /* |
2 | * Copyright (C) 2012,2013 - ARM Ltd | |
3 | * Author: Marc Zyngier <marc.zyngier@arm.com> | |
4 | * | |
5 | * Derived from arch/arm/include/asm/kvm_host.h: | |
6 | * Copyright (C) 2012 - Virtual Open Systems and Columbia University | |
7 | * Author: Christoffer Dall <c.dall@virtualopensystems.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
22 | #ifndef __ARM64_KVM_HOST_H__ | |
23 | #define __ARM64_KVM_HOST_H__ | |
24 | ||
65647300 PB |
25 | #include <linux/types.h> |
26 | #include <linux/kvm_types.h> | |
63a1e1c9 | 27 | #include <asm/cpufeature.h> |
17eed27b | 28 | #include <asm/fpsimd.h> |
4f8d6632 | 29 | #include <asm/kvm.h> |
3a3604bc | 30 | #include <asm/kvm_asm.h> |
4f8d6632 MZ |
31 | #include <asm/kvm_mmio.h> |
32 | ||
c1426e4c EA |
33 | #define __KVM_HAVE_ARCH_INTC_INITIALIZED |
34 | ||
955a3fc6 | 35 | #define KVM_USER_MEM_SLOTS 512 |
920552b2 | 36 | #define KVM_HALT_POLL_NS_DEFAULT 500000 |
4f8d6632 MZ |
37 | |
38 | #include <kvm/arm_vgic.h> | |
39 | #include <kvm/arm_arch_timer.h> | |
04fe4726 | 40 | #include <kvm/arm_pmu.h> |
4f8d6632 | 41 | |
ef748917 ML |
42 | #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS |
43 | ||
808e7381 | 44 | #define KVM_VCPU_MAX_FEATURES 4 |
4f8d6632 | 45 | |
7b244e2b | 46 | #define KVM_REQ_SLEEP \ |
2387149e | 47 | KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) |
325f9c64 | 48 | #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1) |
b13216cf | 49 | |
6951e48b | 50 | int __attribute_const__ kvm_target_cpu(void); |
4f8d6632 | 51 | int kvm_reset_vcpu(struct kvm_vcpu *vcpu); |
b46f01ce | 52 | int kvm_arch_dev_ioctl_check_extension(struct kvm *kvm, long ext); |
c612505f | 53 | void __extended_idmap_trampoline(phys_addr_t boot_pgd, phys_addr_t idmap_start); |
4f8d6632 MZ |
54 | |
55 | struct kvm_arch { | |
56 | /* The VMID generation used for the virt. memory system */ | |
57 | u64 vmid_gen; | |
58 | u32 vmid; | |
59 | ||
60 | /* 1-level 2nd stage table and lock */ | |
61 | spinlock_t pgd_lock; | |
62 | pgd_t *pgd; | |
63 | ||
64 | /* VTTBR value associated with above pgd and vmid */ | |
65 | u64 vttbr; | |
66 | ||
94d0e598 MZ |
67 | /* The last vcpu id that ran on each physical CPU */ |
68 | int __percpu *last_vcpu_ran; | |
69 | ||
3caa2d8c AP |
70 | /* The maximum number of vCPUs depends on the used GIC model */ |
71 | int max_vcpus; | |
72 | ||
4f8d6632 MZ |
73 | /* Interrupt controller */ |
74 | struct vgic_dist vgic; | |
4f8d6632 MZ |
75 | }; |
76 | ||
77 | #define KVM_NR_MEM_OBJS 40 | |
78 | ||
79 | /* | |
80 | * We don't want allocation failures within the mmu code, so we preallocate | |
81 | * enough memory for a single page fault in a cache. | |
82 | */ | |
83 | struct kvm_mmu_memory_cache { | |
84 | int nobjs; | |
85 | void *objects[KVM_NR_MEM_OBJS]; | |
86 | }; | |
87 | ||
88 | struct kvm_vcpu_fault_info { | |
89 | u32 esr_el2; /* Hyp Syndrom Register */ | |
90 | u64 far_el2; /* Hyp Fault Address Register */ | |
91 | u64 hpfar_el2; /* Hyp IPA Fault Address Register */ | |
92 | }; | |
93 | ||
9d8415d6 MZ |
94 | /* |
95 | * 0 is reserved as an invalid value. | |
96 | * Order should be kept in sync with the save/restore code. | |
97 | */ | |
98 | enum vcpu_sysreg { | |
99 | __INVALID_SYSREG__, | |
100 | MPIDR_EL1, /* MultiProcessor Affinity Register */ | |
101 | CSSELR_EL1, /* Cache Size Selection Register */ | |
102 | SCTLR_EL1, /* System Control Register */ | |
103 | ACTLR_EL1, /* Auxiliary Control Register */ | |
104 | CPACR_EL1, /* Coprocessor Access Control */ | |
105 | TTBR0_EL1, /* Translation Table Base Register 0 */ | |
106 | TTBR1_EL1, /* Translation Table Base Register 1 */ | |
107 | TCR_EL1, /* Translation Control Register */ | |
108 | ESR_EL1, /* Exception Syndrome Register */ | |
ef769e32 AB |
109 | AFSR0_EL1, /* Auxiliary Fault Status Register 0 */ |
110 | AFSR1_EL1, /* Auxiliary Fault Status Register 1 */ | |
9d8415d6 MZ |
111 | FAR_EL1, /* Fault Address Register */ |
112 | MAIR_EL1, /* Memory Attribute Indirection Register */ | |
113 | VBAR_EL1, /* Vector Base Address Register */ | |
114 | CONTEXTIDR_EL1, /* Context ID Register */ | |
115 | TPIDR_EL0, /* Thread ID, User R/W */ | |
116 | TPIDRRO_EL0, /* Thread ID, User R/O */ | |
117 | TPIDR_EL1, /* Thread ID, Privileged */ | |
118 | AMAIR_EL1, /* Aux Memory Attribute Indirection Register */ | |
119 | CNTKCTL_EL1, /* Timer Control Register (EL1) */ | |
120 | PAR_EL1, /* Physical Address Register */ | |
121 | MDSCR_EL1, /* Monitor Debug System Control Register */ | |
122 | MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ | |
123 | ||
ab946834 SZ |
124 | /* Performance Monitors Registers */ |
125 | PMCR_EL0, /* Control Register */ | |
3965c3ce | 126 | PMSELR_EL0, /* Event Counter Selection Register */ |
051ff581 SZ |
127 | PMEVCNTR0_EL0, /* Event Counter Register (0-30) */ |
128 | PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30, | |
129 | PMCCNTR_EL0, /* Cycle Counter Register */ | |
9feb21ac SZ |
130 | PMEVTYPER0_EL0, /* Event Type Register (0-30) */ |
131 | PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30, | |
132 | PMCCFILTR_EL0, /* Cycle Count Filter Register */ | |
96b0eebc | 133 | PMCNTENSET_EL0, /* Count Enable Set Register */ |
9db52c78 | 134 | PMINTENSET_EL1, /* Interrupt Enable Set Register */ |
76d883c4 | 135 | PMOVSSET_EL0, /* Overflow Flag Status Set Register */ |
7a0adc70 | 136 | PMSWINC_EL0, /* Software Increment Register */ |
d692b8ad | 137 | PMUSERENR_EL0, /* User Enable Register */ |
ab946834 | 138 | |
9d8415d6 MZ |
139 | /* 32bit specific registers. Keep them at the end of the range */ |
140 | DACR32_EL2, /* Domain Access Control Register */ | |
141 | IFSR32_EL2, /* Instruction Fault Status Register */ | |
142 | FPEXC32_EL2, /* Floating-Point Exception Control Register */ | |
143 | DBGVCR32_EL2, /* Debug Vector Catch Register */ | |
144 | ||
145 | NR_SYS_REGS /* Nothing after this line! */ | |
146 | }; | |
147 | ||
148 | /* 32bit mapping */ | |
149 | #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */ | |
150 | #define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */ | |
151 | #define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */ | |
152 | #define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */ | |
153 | #define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */ | |
154 | #define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */ | |
155 | #define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */ | |
156 | #define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */ | |
157 | #define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */ | |
158 | #define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */ | |
159 | #define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */ | |
160 | #define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */ | |
161 | #define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */ | |
162 | #define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */ | |
163 | #define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */ | |
164 | #define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */ | |
165 | #define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */ | |
166 | #define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */ | |
167 | #define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */ | |
168 | #define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */ | |
169 | #define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */ | |
170 | #define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */ | |
171 | #define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */ | |
172 | #define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */ | |
173 | #define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */ | |
174 | #define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */ | |
175 | #define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */ | |
176 | #define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */ | |
177 | #define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */ | |
178 | ||
179 | #define cp14_DBGDSCRext (MDSCR_EL1 * 2) | |
180 | #define cp14_DBGBCR0 (DBGBCR0_EL1 * 2) | |
181 | #define cp14_DBGBVR0 (DBGBVR0_EL1 * 2) | |
182 | #define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1) | |
183 | #define cp14_DBGWCR0 (DBGWCR0_EL1 * 2) | |
184 | #define cp14_DBGWVR0 (DBGWVR0_EL1 * 2) | |
185 | #define cp14_DBGDCCINT (MDCCINT_EL1 * 2) | |
186 | ||
187 | #define NR_COPRO_REGS (NR_SYS_REGS * 2) | |
188 | ||
4f8d6632 MZ |
189 | struct kvm_cpu_context { |
190 | struct kvm_regs gp_regs; | |
40033a61 MZ |
191 | union { |
192 | u64 sys_regs[NR_SYS_REGS]; | |
72564016 | 193 | u32 copro[NR_COPRO_REGS]; |
40033a61 | 194 | }; |
4f8d6632 MZ |
195 | }; |
196 | ||
197 | typedef struct kvm_cpu_context kvm_cpu_context_t; | |
198 | ||
199 | struct kvm_vcpu_arch { | |
200 | struct kvm_cpu_context ctxt; | |
201 | ||
202 | /* HYP configuration */ | |
203 | u64 hcr_el2; | |
56c7f5e7 | 204 | u32 mdcr_el2; |
4f8d6632 MZ |
205 | |
206 | /* Exception Information */ | |
207 | struct kvm_vcpu_fault_info fault; | |
208 | ||
84e690bf | 209 | /* Guest debug state */ |
0c557ed4 MZ |
210 | u64 debug_flags; |
211 | ||
84e690bf AB |
212 | /* |
213 | * We maintain more than a single set of debug registers to support | |
214 | * debugging the guest from the host and to maintain separate host and | |
215 | * guest state during world switches. vcpu_debug_state are the debug | |
216 | * registers of the vcpu as the guest sees them. host_debug_state are | |
834bf887 AB |
217 | * the host registers which are saved and restored during |
218 | * world switches. external_debug_state contains the debug | |
219 | * values we want to debug the guest. This is set via the | |
220 | * KVM_SET_GUEST_DEBUG ioctl. | |
84e690bf AB |
221 | * |
222 | * debug_ptr points to the set of debug registers that should be loaded | |
223 | * onto the hardware when running the guest. | |
224 | */ | |
225 | struct kvm_guest_debug_arch *debug_ptr; | |
226 | struct kvm_guest_debug_arch vcpu_debug_state; | |
834bf887 | 227 | struct kvm_guest_debug_arch external_debug_state; |
84e690bf | 228 | |
4f8d6632 MZ |
229 | /* Pointer to host CPU context */ |
230 | kvm_cpu_context_t *host_cpu_context; | |
f85279b4 WD |
231 | struct { |
232 | /* {Break,watch}point registers */ | |
233 | struct kvm_guest_debug_arch regs; | |
234 | /* Statistical profiling extension */ | |
235 | u64 pmscr_el1; | |
236 | } host_debug_state; | |
4f8d6632 MZ |
237 | |
238 | /* VGIC state */ | |
239 | struct vgic_cpu vgic_cpu; | |
240 | struct arch_timer_cpu timer_cpu; | |
04fe4726 | 241 | struct kvm_pmu pmu; |
4f8d6632 MZ |
242 | |
243 | /* | |
244 | * Anything that is not used directly from assembly code goes | |
245 | * here. | |
246 | */ | |
4f8d6632 | 247 | |
337b99bf AB |
248 | /* |
249 | * Guest registers we preserve during guest debugging. | |
250 | * | |
251 | * These shadow registers are updated by the kvm_handle_sys_reg | |
252 | * trap handler if the guest accesses or updates them while we | |
253 | * are using guest debug. | |
254 | */ | |
255 | struct { | |
256 | u32 mdscr_el1; | |
257 | } guest_debug_preserved; | |
258 | ||
3781528e EA |
259 | /* vcpu power-off state */ |
260 | bool power_off; | |
4f8d6632 | 261 | |
3b92830a EA |
262 | /* Don't run the guest (internal implementation need) */ |
263 | bool pause; | |
264 | ||
4f8d6632 MZ |
265 | /* IO related fields */ |
266 | struct kvm_decode mmio_decode; | |
267 | ||
268 | /* Interrupt related fields */ | |
269 | u64 irq_lines; /* IRQ and FIQ levels */ | |
270 | ||
271 | /* Cache some mmu pages needed inside spinlock regions */ | |
272 | struct kvm_mmu_memory_cache mmu_page_cache; | |
273 | ||
274 | /* Target CPU and feature flags */ | |
6c8c0c4d | 275 | int target; |
4f8d6632 MZ |
276 | DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES); |
277 | ||
278 | /* Detect first run of a vcpu */ | |
279 | bool has_run_once; | |
280 | }; | |
281 | ||
282 | #define vcpu_gp_regs(v) (&(v)->arch.ctxt.gp_regs) | |
283 | #define vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)]) | |
72564016 MZ |
284 | /* |
285 | * CP14 and CP15 live in the same array, as they are backed by the | |
286 | * same system registers. | |
287 | */ | |
288 | #define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r)]) | |
289 | #define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r)]) | |
4f8d6632 | 290 | |
f0a3eaff | 291 | #ifdef CONFIG_CPU_BIG_ENDIAN |
dedf97e8 MZ |
292 | #define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r)) |
293 | #define vcpu_cp15_64_low(v,r) vcpu_cp15((v),(r) + 1) | |
f0a3eaff | 294 | #else |
dedf97e8 MZ |
295 | #define vcpu_cp15_64_high(v,r) vcpu_cp15((v),(r) + 1) |
296 | #define vcpu_cp15_64_low(v,r) vcpu_cp15((v),(r)) | |
f0a3eaff VK |
297 | #endif |
298 | ||
4f8d6632 | 299 | struct kvm_vm_stat { |
8a7e75d4 | 300 | ulong remote_tlb_flush; |
4f8d6632 MZ |
301 | }; |
302 | ||
303 | struct kvm_vcpu_stat { | |
8a7e75d4 SJS |
304 | u64 halt_successful_poll; |
305 | u64 halt_attempted_poll; | |
306 | u64 halt_poll_invalid; | |
307 | u64 halt_wakeup; | |
308 | u64 hvc_exit_stat; | |
b19e6892 AT |
309 | u64 wfe_exit_stat; |
310 | u64 wfi_exit_stat; | |
311 | u64 mmio_exit_user; | |
312 | u64 mmio_exit_kernel; | |
313 | u64 exits; | |
4f8d6632 MZ |
314 | }; |
315 | ||
473bdc0e | 316 | int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init); |
4f8d6632 MZ |
317 | unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); |
318 | int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); | |
4f8d6632 MZ |
319 | int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); |
320 | int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); | |
321 | ||
322 | #define KVM_ARCH_WANT_MMU_NOTIFIER | |
4f8d6632 MZ |
323 | int kvm_unmap_hva(struct kvm *kvm, unsigned long hva); |
324 | int kvm_unmap_hva_range(struct kvm *kvm, | |
325 | unsigned long start, unsigned long end); | |
326 | void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); | |
35307b9a MZ |
327 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); |
328 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); | |
4f8d6632 | 329 | |
4f8d6632 | 330 | struct kvm_vcpu *kvm_arm_get_running_vcpu(void); |
4000be42 | 331 | struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void); |
b13216cf CD |
332 | void kvm_arm_halt_guest(struct kvm *kvm); |
333 | void kvm_arm_resume_guest(struct kvm *kvm); | |
4f8d6632 | 334 | |
a0bf9776 | 335 | u64 __kvm_call_hyp(void *hypfn, ...); |
22b39ca3 MZ |
336 | #define kvm_call_hyp(f, ...) __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__) |
337 | ||
cf5d3188 | 338 | void force_vm_exit(const cpumask_t *mask); |
8199ed0e | 339 | void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot); |
4f8d6632 MZ |
340 | |
341 | int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, | |
342 | int exception_index); | |
343 | ||
344 | int kvm_perf_init(void); | |
345 | int kvm_perf_teardown(void); | |
346 | ||
4429fc64 AP |
347 | struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); |
348 | ||
12fda812 | 349 | static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr, |
092bd143 MZ |
350 | unsigned long hyp_stack_ptr, |
351 | unsigned long vector_ptr) | |
352 | { | |
353 | /* | |
63a1e1c9 MR |
354 | * Call initialization code, and switch to the full blown HYP code. |
355 | * If the cpucaps haven't been finalized yet, something has gone very | |
356 | * wrong, and hyp will crash and burn when it uses any | |
357 | * cpus_have_const_cap() wrapper. | |
092bd143 | 358 | */ |
63a1e1c9 | 359 | BUG_ON(!static_branch_likely(&arm64_const_caps_ready)); |
3421e9d8 | 360 | __kvm_call_hyp((void *)pgd_ptr, hyp_stack_ptr, vector_ptr); |
092bd143 | 361 | } |
67f69197 | 362 | |
0865e636 RK |
363 | static inline void kvm_arch_hardware_unsetup(void) {} |
364 | static inline void kvm_arch_sync_events(struct kvm *kvm) {} | |
365 | static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {} | |
366 | static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} | |
3491caf2 | 367 | static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} |
0865e636 | 368 | |
56c7f5e7 AB |
369 | void kvm_arm_init_debug(void); |
370 | void kvm_arm_setup_debug(struct kvm_vcpu *vcpu); | |
371 | void kvm_arm_clear_debug(struct kvm_vcpu *vcpu); | |
84e690bf | 372 | void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu); |
696673d1 | 373 | bool kvm_arm_handle_step_debug(struct kvm_vcpu *vcpu, struct kvm_run *run); |
bb0c70bc SZ |
374 | int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, |
375 | struct kvm_device_attr *attr); | |
376 | int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, | |
377 | struct kvm_device_attr *attr); | |
378 | int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, | |
379 | struct kvm_device_attr *attr); | |
56c7f5e7 | 380 | |
21a4179c MZ |
381 | static inline void __cpu_init_stage2(void) |
382 | { | |
6141570c MZ |
383 | u32 parange = kvm_call_hyp(__init_stage2_translation); |
384 | ||
385 | WARN_ONCE(parange < 40, | |
386 | "PARange is %d bits, unsupported configuration!", parange); | |
21a4179c MZ |
387 | } |
388 | ||
17eed27b DM |
389 | /* |
390 | * All host FP/SIMD state is restored on guest exit, so nothing needs | |
391 | * doing here except in the SVE case: | |
392 | */ | |
393 | static inline void kvm_fpsimd_flush_cpu_state(void) | |
394 | { | |
395 | if (system_supports_sve()) | |
396 | sve_flush_cpu_state(); | |
397 | } | |
398 | ||
4f8d6632 | 399 | #endif /* __ARM64_KVM_HOST_H__ */ |