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caab277b | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
4f04d8f0 CM |
2 | /* |
3 | * Copyright (C) 2012 ARM Ltd. | |
4f04d8f0 CM |
4 | */ |
5 | #ifndef __ASM_MMU_H | |
6 | #define __ASM_MMU_H | |
7 | ||
b89d82ef WD |
8 | #include <asm/cputype.h> |
9 | ||
5ce93ab6 | 10 | #define MMCF_AARCH32 0x1 /* mm context flag for AArch32 executables */ |
79e9aa59 JM |
11 | #define USER_ASID_BIT 48 |
12 | #define USER_ASID_FLAG (UL(1) << USER_ASID_BIT) | |
b519538d | 13 | #define TTBR_ASID_MASK (UL(0xffff) << 48) |
5ce93ab6 | 14 | |
4205a89b MZ |
15 | #define BP_HARDEN_EL2_SLOTS 4 |
16 | ||
fc0e1299 WD |
17 | #ifndef __ASSEMBLY__ |
18 | ||
4f04d8f0 | 19 | typedef struct { |
5aec715d WD |
20 | atomic64_t id; |
21 | void *vdso; | |
06beb72f | 22 | unsigned long flags; |
4f04d8f0 CM |
23 | } mm_context_t; |
24 | ||
5aec715d WD |
25 | /* |
26 | * This macro is only used by the TLBI code, which cannot race with an | |
27 | * ASID change and therefore doesn't need to reload the counter using | |
28 | * atomic64_read. | |
29 | */ | |
30 | #define ASID(mm) ((mm)->context.id.counter & 0xffff) | |
4f04d8f0 | 31 | |
09e3c22a | 32 | static inline bool arm64_kernel_unmapped_at_el0(void) |
c2d92353 | 33 | { |
c8355785 | 34 | return cpus_have_const_cap(ARM64_UNMAP_KERNEL_AT_EL0); |
b89d82ef WD |
35 | } |
36 | ||
0f15adbb WD |
37 | typedef void (*bp_hardening_cb_t)(void); |
38 | ||
39 | struct bp_hardening_data { | |
40 | int hyp_vectors_slot; | |
41 | bp_hardening_cb_t fn; | |
42 | }; | |
43 | ||
dee39247 MZ |
44 | #if (defined(CONFIG_HARDEN_BRANCH_PREDICTOR) || \ |
45 | defined(CONFIG_HARDEN_EL2_VECTORS)) | |
0f15adbb | 46 | extern char __bp_harden_hyp_vecs_start[], __bp_harden_hyp_vecs_end[]; |
4205a89b | 47 | extern atomic_t arm64_el2_vector_last_slot; |
dee39247 | 48 | #endif /* CONFIG_HARDEN_BRANCH_PREDICTOR || CONFIG_HARDEN_EL2_VECTORS */ |
0f15adbb | 49 | |
dee39247 | 50 | #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR |
0f15adbb WD |
51 | DECLARE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); |
52 | ||
53 | static inline struct bp_hardening_data *arm64_get_bp_hardening_data(void) | |
54 | { | |
55 | return this_cpu_ptr(&bp_hardening_data); | |
56 | } | |
57 | ||
58 | static inline void arm64_apply_bp_hardening(void) | |
59 | { | |
60 | struct bp_hardening_data *d; | |
61 | ||
62 | if (!cpus_have_const_cap(ARM64_HARDEN_BRANCH_PREDICTOR)) | |
63 | return; | |
64 | ||
65 | d = arm64_get_bp_hardening_data(); | |
66 | if (d->fn) | |
67 | d->fn(); | |
68 | } | |
69 | #else | |
70 | static inline struct bp_hardening_data *arm64_get_bp_hardening_data(void) | |
71 | { | |
72 | return NULL; | |
73 | } | |
74 | ||
75 | static inline void arm64_apply_bp_hardening(void) { } | |
76 | #endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */ | |
77 | ||
83504032 | 78 | extern void arm64_memblock_init(void); |
4f04d8f0 | 79 | extern void paging_init(void); |
3194ac6e | 80 | extern void bootmem_init(void); |
2475ff9d | 81 | extern void __iomem *early_io_map(phys_addr_t phys, unsigned long virt); |
0bf757c7 | 82 | extern void init_mem_pgprot(void); |
8ce837ce AB |
83 | extern void create_pgd_mapping(struct mm_struct *mm, phys_addr_t phys, |
84 | unsigned long virt, phys_addr_t size, | |
f14c66ce | 85 | pgprot_t prot, bool page_mappings_only); |
e112b032 | 86 | extern void *fixmap_remap_fdt(phys_addr_t dt_phys, int *size, pgprot_t prot); |
5ea5306c | 87 | extern void mark_linear_text_alias_ro(void); |
09e3c22a | 88 | extern bool kaslr_requires_kpti(void); |
4f04d8f0 | 89 | |
2b5548b6 JY |
90 | #define INIT_MM_CONTEXT(name) \ |
91 | .pgd = init_pg_dir, | |
92 | ||
fc0e1299 | 93 | #endif /* !__ASSEMBLY__ */ |
4f04d8f0 | 94 | #endif |