[mirror_ubuntu-focal-kernel.git] / arch / arm64 / include / asm / pgtable-hwdef.h

/*
 * Copyright (C) 2012 ARM Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#ifndef __ASM_PGTABLE_HWDEF_H
#define __ASM_PGTABLE_HWDEF_H

#include <asm/memory.h>

/*
 * Number of page-table levels required to address 'va_bits' wide
 * address, without section mapping. We resolve the top (va_bits - PAGE_SHIFT)
 * bits with (PAGE_SHIFT - 3) bits at each page table level. Hence:
 *
 *  levels = DIV_ROUND_UP((va_bits - PAGE_SHIFT), (PAGE_SHIFT - 3))
 *
 * where DIV_ROUND_UP(n, d) => (((n) + (d) - 1) / (d))
 *
 * We cannot include linux/kernel.h which defines DIV_ROUND_UP here
 * due to build issues. So we open code DIV_ROUND_UP here:
 *
 *	((((va_bits) - PAGE_SHIFT) + (PAGE_SHIFT - 3) - 1) / (PAGE_SHIFT - 3))
 *
 * which gets simplified as :
 */
#define ARM64_HW_PGTABLE_LEVELS(va_bits) (((va_bits) - 4) / (PAGE_SHIFT - 3))

/*
 * Size mapped by an entry at level n ( 0 <= n <= 3)
 * We map (PAGE_SHIFT - 3) at all translation levels and PAGE_SHIFT bits
 * in the final page. The maximum number of translation levels supported by
 * the architecture is 4. Hence, starting at at level n, we have further
 * ((4 - n) - 1) levels of translation excluding the offset within the page.
 * So, the total number of bits mapped by an entry at level n is :
 *
 *  ((4 - n) - 1) * (PAGE_SHIFT - 3) + PAGE_SHIFT
 *
 * Rearranging it a bit we get :
 *   (4 - n) * (PAGE_SHIFT - 3) + 3
 */
#define ARM64_HW_PGTABLE_LEVEL_SHIFT(n)	((PAGE_SHIFT - 3) * (4 - (n)) + 3)

#define PTRS_PER_PTE		(1 << (PAGE_SHIFT - 3))

/*
 * PMD_SHIFT determines the size a level 2 page table entry can map.
 */
#if CONFIG_PGTABLE_LEVELS > 2
#define PMD_SHIFT		ARM64_HW_PGTABLE_LEVEL_SHIFT(2)
#define PMD_SIZE		(_AC(1, UL) << PMD_SHIFT)
#define PMD_MASK		(~(PMD_SIZE-1))
#define PTRS_PER_PMD		PTRS_PER_PTE
#endif

/*
 * PUD_SHIFT determines the size a level 1 page table entry can map.
 */
#if CONFIG_PGTABLE_LEVELS > 3
#define PUD_SHIFT		ARM64_HW_PGTABLE_LEVEL_SHIFT(1)
#define PUD_SIZE		(_AC(1, UL) << PUD_SHIFT)
#define PUD_MASK		(~(PUD_SIZE-1))
#define PTRS_PER_PUD		PTRS_PER_PTE
#endif

/*
 * PGDIR_SHIFT determines the size a top-level page table entry can map
 * (depending on the configuration, this level can be 0, 1 or 2).
 */
#define PGDIR_SHIFT		ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - CONFIG_PGTABLE_LEVELS)
#define PGDIR_SIZE		(_AC(1, UL) << PGDIR_SHIFT)
#define PGDIR_MASK		(~(PGDIR_SIZE-1))
#ifdef CONFIG_ARM64_USER_VA_BITS_52
#define PTRS_PER_PGD		(1 << (52 - PGDIR_SHIFT))
#else
#define PTRS_PER_PGD		(1 << (VA_BITS - PGDIR_SHIFT))
#endif

/*
 * Section address mask and size definitions.
 */
#define SECTION_SHIFT		PMD_SHIFT
#define SECTION_SIZE		(_AC(1, UL) << SECTION_SHIFT)
#define SECTION_MASK		(~(SECTION_SIZE-1))

/*
 * Contiguous page definitions.
 */
#ifdef CONFIG_ARM64_64K_PAGES
#define CONT_PTE_SHIFT		5
#define CONT_PMD_SHIFT		5
#elif defined(CONFIG_ARM64_16K_PAGES)
#define CONT_PTE_SHIFT		7
#define CONT_PMD_SHIFT		5
#else
#define CONT_PTE_SHIFT		4
#define CONT_PMD_SHIFT		4
#endif

#define CONT_PTES		(1 << CONT_PTE_SHIFT)
#define CONT_PTE_SIZE		(CONT_PTES * PAGE_SIZE)
#define CONT_PTE_MASK		(~(CONT_PTE_SIZE - 1))
#define CONT_PMDS		(1 << CONT_PMD_SHIFT)
#define CONT_PMD_SIZE		(CONT_PMDS * PMD_SIZE)
#define CONT_PMD_MASK		(~(CONT_PMD_SIZE - 1))
/* the the numerical offset of the PTE within a range of CONT_PTES */
#define CONT_RANGE_OFFSET(addr) (((addr)>>PAGE_SHIFT)&(CONT_PTES-1))

/*
 * Hardware page table definitions.
 *
 * Level 1 descriptor (PUD).
 */
#define PUD_TYPE_TABLE		(_AT(pudval_t, 3) << 0)
#define PUD_TABLE_BIT		(_AT(pudval_t, 1) << 1)
#define PUD_TYPE_MASK		(_AT(pudval_t, 3) << 0)
#define PUD_TYPE_SECT		(_AT(pudval_t, 1) << 0)

/*
 * Level 2 descriptor (PMD).
 */
#define PMD_TYPE_MASK		(_AT(pmdval_t, 3) << 0)
#define PMD_TYPE_FAULT		(_AT(pmdval_t, 0) << 0)
#define PMD_TYPE_TABLE		(_AT(pmdval_t, 3) << 0)
#define PMD_TYPE_SECT		(_AT(pmdval_t, 1) << 0)
#define PMD_TABLE_BIT		(_AT(pmdval_t, 1) << 1)

/*
 * Section
 */
#define PMD_SECT_VALID		(_AT(pmdval_t, 1) << 0)
#define PMD_SECT_USER		(_AT(pmdval_t, 1) << 6)		/* AP[1] */
#define PMD_SECT_RDONLY		(_AT(pmdval_t, 1) << 7)		/* AP[2] */
#define PMD_SECT_S		(_AT(pmdval_t, 3) << 8)
#define PMD_SECT_AF		(_AT(pmdval_t, 1) << 10)
#define PMD_SECT_NG		(_AT(pmdval_t, 1) << 11)
#define PMD_SECT_CONT		(_AT(pmdval_t, 1) << 52)
#define PMD_SECT_PXN		(_AT(pmdval_t, 1) << 53)
#define PMD_SECT_UXN		(_AT(pmdval_t, 1) << 54)

/*
 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
 */
#define PMD_ATTRINDX(t)		(_AT(pmdval_t, (t)) << 2)
#define PMD_ATTRINDX_MASK	(_AT(pmdval_t, 7) << 2)

/*
 * Level 3 descriptor (PTE).
 */
#define PTE_TYPE_MASK		(_AT(pteval_t, 3) << 0)
#define PTE_TYPE_FAULT		(_AT(pteval_t, 0) << 0)
#define PTE_TYPE_PAGE		(_AT(pteval_t, 3) << 0)
#define PTE_TABLE_BIT		(_AT(pteval_t, 1) << 1)
#define PTE_USER		(_AT(pteval_t, 1) << 6)		/* AP[1] */
#define PTE_RDONLY		(_AT(pteval_t, 1) << 7)		/* AP[2] */
#define PTE_SHARED		(_AT(pteval_t, 3) << 8)		/* SH[1:0], inner shareable */
#define PTE_AF			(_AT(pteval_t, 1) << 10)	/* Access Flag */
#define PTE_NG			(_AT(pteval_t, 1) << 11)	/* nG */
#define PTE_DBM			(_AT(pteval_t, 1) << 51)	/* Dirty Bit Management */
#define PTE_CONT		(_AT(pteval_t, 1) << 52)	/* Contiguous range */
#define PTE_PXN			(_AT(pteval_t, 1) << 53)	/* Privileged XN */
#define PTE_UXN			(_AT(pteval_t, 1) << 54)	/* User XN */
#define PTE_HYP_XN		(_AT(pteval_t, 1) << 54)	/* HYP XN */

#define PTE_ADDR_LOW		(((_AT(pteval_t, 1) << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT)
#ifdef CONFIG_ARM64_PA_BITS_52
#define PTE_ADDR_HIGH		(_AT(pteval_t, 0xf) << 12)
#define PTE_ADDR_MASK		(PTE_ADDR_LOW | PTE_ADDR_HIGH)
#else
#define PTE_ADDR_MASK		PTE_ADDR_LOW
#endif

/*
 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
 */
#define PTE_ATTRINDX(t)		(_AT(pteval_t, (t)) << 2)
#define PTE_ATTRINDX_MASK	(_AT(pteval_t, 7) << 2)

/*
 * 2nd stage PTE definitions
 */
#define PTE_S2_RDONLY		(_AT(pteval_t, 1) << 6)   /* HAP[2:1] */
#define PTE_S2_RDWR		(_AT(pteval_t, 3) << 6)   /* HAP[2:1] */
#define PTE_S2_XN		(_AT(pteval_t, 2) << 53)  /* XN[1:0] */

#define PMD_S2_RDONLY		(_AT(pmdval_t, 1) << 6)   /* HAP[2:1] */
#define PMD_S2_RDWR		(_AT(pmdval_t, 3) << 6)   /* HAP[2:1] */
#define PMD_S2_XN		(_AT(pmdval_t, 2) << 53)  /* XN[1:0] */

/*
 * Memory Attribute override for Stage-2 (MemAttr[3:0])
 */
#define PTE_S2_MEMATTR(t)	(_AT(pteval_t, (t)) << 2)
#define PTE_S2_MEMATTR_MASK	(_AT(pteval_t, 0xf) << 2)

/*
 * EL2/HYP PTE/PMD definitions
 */
#define PMD_HYP			PMD_SECT_USER
#define PTE_HYP			PTE_USER

/*
 * Highest possible physical address supported.
 */
#define PHYS_MASK_SHIFT		(CONFIG_ARM64_PA_BITS)
#define PHYS_MASK		((UL(1) << PHYS_MASK_SHIFT) - 1)

#define TTBR_CNP_BIT		(UL(1) << 0)

/*
 * TCR flags.
 */
#define TCR_T0SZ_OFFSET		0
#define TCR_T1SZ_OFFSET		16
#define TCR_T0SZ(x)		((UL(64) - (x)) << TCR_T0SZ_OFFSET)
#define TCR_T1SZ(x)		((UL(64) - (x)) << TCR_T1SZ_OFFSET)
#define TCR_TxSZ(x)		(TCR_T0SZ(x) | TCR_T1SZ(x))
#define TCR_TxSZ_WIDTH		6
#define TCR_T0SZ_MASK		(((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)

#define TCR_EPD0_SHIFT		7
#define TCR_EPD0_MASK		(UL(1) << TCR_EPD0_SHIFT)
#define TCR_IRGN0_SHIFT		8
#define TCR_IRGN0_MASK		(UL(3) << TCR_IRGN0_SHIFT)
#define TCR_IRGN0_NC		(UL(0) << TCR_IRGN0_SHIFT)
#define TCR_IRGN0_WBWA		(UL(1) << TCR_IRGN0_SHIFT)
#define TCR_IRGN0_WT		(UL(2) << TCR_IRGN0_SHIFT)
#define TCR_IRGN0_WBnWA		(UL(3) << TCR_IRGN0_SHIFT)

#define TCR_EPD1_SHIFT		23
#define TCR_EPD1_MASK		(UL(1) << TCR_EPD1_SHIFT)
#define TCR_IRGN1_SHIFT		24
#define TCR_IRGN1_MASK		(UL(3) << TCR_IRGN1_SHIFT)
#define TCR_IRGN1_NC		(UL(0) << TCR_IRGN1_SHIFT)
#define TCR_IRGN1_WBWA		(UL(1) << TCR_IRGN1_SHIFT)
#define TCR_IRGN1_WT		(UL(2) << TCR_IRGN1_SHIFT)
#define TCR_IRGN1_WBnWA		(UL(3) << TCR_IRGN1_SHIFT)

#define TCR_IRGN_NC		(TCR_IRGN0_NC | TCR_IRGN1_NC)
#define TCR_IRGN_WBWA		(TCR_IRGN0_WBWA | TCR_IRGN1_WBWA)
#define TCR_IRGN_WT		(TCR_IRGN0_WT | TCR_IRGN1_WT)
#define TCR_IRGN_WBnWA		(TCR_IRGN0_WBnWA | TCR_IRGN1_WBnWA)
#define TCR_IRGN_MASK		(TCR_IRGN0_MASK | TCR_IRGN1_MASK)


#define TCR_ORGN0_SHIFT		10
#define TCR_ORGN0_MASK		(UL(3) << TCR_ORGN0_SHIFT)
#define TCR_ORGN0_NC		(UL(0) << TCR_ORGN0_SHIFT)
#define TCR_ORGN0_WBWA		(UL(1) << TCR_ORGN0_SHIFT)
#define TCR_ORGN0_WT		(UL(2) << TCR_ORGN0_SHIFT)
#define TCR_ORGN0_WBnWA		(UL(3) << TCR_ORGN0_SHIFT)

#define TCR_ORGN1_SHIFT		26
#define TCR_ORGN1_MASK		(UL(3) << TCR_ORGN1_SHIFT)
#define TCR_ORGN1_NC		(UL(0) << TCR_ORGN1_SHIFT)
#define TCR_ORGN1_WBWA		(UL(1) << TCR_ORGN1_SHIFT)
#define TCR_ORGN1_WT		(UL(2) << TCR_ORGN1_SHIFT)
#define TCR_ORGN1_WBnWA		(UL(3) << TCR_ORGN1_SHIFT)

#define TCR_ORGN_NC		(TCR_ORGN0_NC | TCR_ORGN1_NC)
#define TCR_ORGN_WBWA		(TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)
#define TCR_ORGN_WT		(TCR_ORGN0_WT | TCR_ORGN1_WT)
#define TCR_ORGN_WBnWA		(TCR_ORGN0_WBnWA | TCR_ORGN1_WBnWA)
#define TCR_ORGN_MASK		(TCR_ORGN0_MASK | TCR_ORGN1_MASK)

#define TCR_SH0_SHIFT		12
#define TCR_SH0_MASK		(UL(3) << TCR_SH0_SHIFT)
#define TCR_SH0_INNER		(UL(3) << TCR_SH0_SHIFT)

#define TCR_SH1_SHIFT		28
#define TCR_SH1_MASK		(UL(3) << TCR_SH1_SHIFT)
#define TCR_SH1_INNER		(UL(3) << TCR_SH1_SHIFT)
#define TCR_SHARED		(TCR_SH0_INNER | TCR_SH1_INNER)

#define TCR_TG0_SHIFT		14
#define TCR_TG0_MASK		(UL(3) << TCR_TG0_SHIFT)
#define TCR_TG0_4K		(UL(0) << TCR_TG0_SHIFT)
#define TCR_TG0_64K		(UL(1) << TCR_TG0_SHIFT)
#define TCR_TG0_16K		(UL(2) << TCR_TG0_SHIFT)

#define TCR_TG1_SHIFT		30
#define TCR_TG1_MASK		(UL(3) << TCR_TG1_SHIFT)
#define TCR_TG1_16K		(UL(1) << TCR_TG1_SHIFT)
#define TCR_TG1_4K		(UL(2) << TCR_TG1_SHIFT)
#define TCR_TG1_64K		(UL(3) << TCR_TG1_SHIFT)

#define TCR_IPS_SHIFT		32
#define TCR_IPS_MASK		(UL(7) << TCR_IPS_SHIFT)
#define TCR_A1			(UL(1) << 22)
#define TCR_ASID16		(UL(1) << 36)
#define TCR_TBI0		(UL(1) << 37)
#define TCR_HA			(UL(1) << 39)
#define TCR_HD			(UL(1) << 40)
#define TCR_NFD1		(UL(1) << 54)

/*
 * TTBR.
 */
#ifdef CONFIG_ARM64_PA_BITS_52
/*
 * This should be GENMASK_ULL(47, 2).
 * TTBR_ELx[1] is RES0 in this configuration.
 */
#define TTBR_BADDR_MASK_52	(((UL(1) << 46) - 1) << 2)
#endif

#ifdef CONFIG_ARM64_USER_VA_BITS_52
/* Must be at least 64-byte aligned to prevent corruption of the TTBR */
#define TTBR1_BADDR_4852_OFFSET	(((UL(1) << (52 - PGDIR_SHIFT)) - \
				 (UL(1) << (48 - PGDIR_SHIFT))) * 8)
#endif

#endif
Commit	Line	Data
4f04d8f0 CM	1	/*
	2	* Copyright (C) 2012 ARM Ltd.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16	#ifndef __ASM_PGTABLE_HWDEF_H
	17	#define __ASM_PGTABLE_HWDEF_H
	18
529c4b05 KM	19	#include <asm/memory.h>
529c4b05 KM	20
686e7838 SP	21	/*
	22	* Number of page-table levels required to address 'va_bits' wide
	23	* address, without section mapping. We resolve the top (va_bits - PAGE_SHIFT)
	24	* bits with (PAGE_SHIFT - 3) bits at each page table level. Hence:
	25	*
	26	* levels = DIV_ROUND_UP((va_bits - PAGE_SHIFT), (PAGE_SHIFT - 3))
	27	*
	28	* where DIV_ROUND_UP(n, d) => (((n) + (d) - 1) / (d))
	29	*
	30	* We cannot include linux/kernel.h which defines DIV_ROUND_UP here
	31	* due to build issues. So we open code DIV_ROUND_UP here:
	32	*
	33	* ((((va_bits) - PAGE_SHIFT) + (PAGE_SHIFT - 3) - 1) / (PAGE_SHIFT - 3))
	34	*
	35	* which gets simplified as :
	36	*/
	37	#define ARM64_HW_PGTABLE_LEVELS(va_bits) (((va_bits) - 4) / (PAGE_SHIFT - 3))
	38
	39	/*
	40	* Size mapped by an entry at level n ( 0 <= n <= 3)
	41	* We map (PAGE_SHIFT - 3) at all translation levels and PAGE_SHIFT bits
	42	* in the final page. The maximum number of translation levels supported by
	43	* the architecture is 4. Hence, starting at at level n, we have further
	44	* ((4 - n) - 1) levels of translation excluding the offset within the page.
	45	* So, the total number of bits mapped by an entry at level n is :
	46	*
	47	* ((4 - n) - 1) * (PAGE_SHIFT - 3) + PAGE_SHIFT
	48	*
	49	* Rearranging it a bit we get :
	50	* (4 - n) * (PAGE_SHIFT - 3) + 3
	51	*/
	52	#define ARM64_HW_PGTABLE_LEVEL_SHIFT(n) ((PAGE_SHIFT - 3) * (4 - (n)) + 3)
	53
6b4fee24 CM	54	#define PTRS_PER_PTE (1 << (PAGE_SHIFT - 3))
	55
	56	/*
	57	* PMD_SHIFT determines the size a level 2 page table entry can map.
	58	*/
9f25e6ad	59	#if CONFIG_PGTABLE_LEVELS > 2
686e7838	60	#define PMD_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(2)
6b4fee24 CM	61	#define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
	62	#define PMD_MASK (~(PMD_SIZE-1))
	63	#define PTRS_PER_PMD PTRS_PER_PTE
	64	#endif
	65
	66	/*
	67	* PUD_SHIFT determines the size a level 1 page table entry can map.
	68	*/
9f25e6ad	69	#if CONFIG_PGTABLE_LEVELS > 3
686e7838	70	#define PUD_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(1)
6b4fee24 CM	71	#define PUD_SIZE (_AC(1, UL) << PUD_SHIFT)
	72	#define PUD_MASK (~(PUD_SIZE-1))
	73	#define PTRS_PER_PUD PTRS_PER_PTE
4f04d8f0 CM	74	#endif
4f04d8f0 CM	75
6b4fee24 CM	76	/*
	77	* PGDIR_SHIFT determines the size a top-level page table entry can map
	78	* (depending on the configuration, this level can be 0, 1 or 2).
	79	*/
686e7838	80	#define PGDIR_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - CONFIG_PGTABLE_LEVELS)
6b4fee24 CM	81	#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
6b4fee24 CM	82	#define PGDIR_MASK (~(PGDIR_SIZE-1))
68d23da4	83	#ifdef CONFIG_ARM64_USER_VA_BITS_52
e842dfb5 SC	84	#define PTRS_PER_PGD (1 << (52 - PGDIR_SHIFT))
e842dfb5 SC	85	#else
6b4fee24	86	#define PTRS_PER_PGD (1 << (VA_BITS - PGDIR_SHIFT))
e842dfb5	87	#endif
6b4fee24 CM	88
	89	/*
	90	* Section address mask and size definitions.
	91	*/
	92	#define SECTION_SHIFT PMD_SHIFT
	93	#define SECTION_SIZE (_AC(1, UL) << SECTION_SHIFT)
	94	#define SECTION_MASK (~(SECTION_SIZE-1))
	95
ecf35a23 JL	96	/*
	97	* Contiguous page definitions.
	98	*/
66b3923a DW	99	#ifdef CONFIG_ARM64_64K_PAGES
	100	#define CONT_PTE_SHIFT 5
	101	#define CONT_PMD_SHIFT 5
	102	#elif defined(CONFIG_ARM64_16K_PAGES)
	103	#define CONT_PTE_SHIFT 7
	104	#define CONT_PMD_SHIFT 5
	105	#else
	106	#define CONT_PTE_SHIFT 4
	107	#define CONT_PMD_SHIFT 4
	108	#endif
	109
	110	#define CONT_PTES (1 << CONT_PTE_SHIFT)
	111	#define CONT_PTE_SIZE (CONT_PTES * PAGE_SIZE)
	112	#define CONT_PTE_MASK (~(CONT_PTE_SIZE - 1))
	113	#define CONT_PMDS (1 << CONT_PMD_SHIFT)
	114	#define CONT_PMD_SIZE (CONT_PMDS * PMD_SIZE)
	115	#define CONT_PMD_MASK (~(CONT_PMD_SIZE - 1))
ecf35a23 JL	116	/* the the numerical offset of the PTE within a range of CONT_PTES */
	117	#define CONT_RANGE_OFFSET(addr) (((addr)>>PAGE_SHIFT)&(CONT_PTES-1))
	118
4f04d8f0 CM	119	/*
	120	* Hardware page table definitions.
	121	*
084bd298 SC	122	* Level 1 descriptor (PUD).
084bd298 SC	123	*/
c79b954b	124	#define PUD_TYPE_TABLE (_AT(pudval_t, 3) << 0)
29d9bef1 PA	125	#define PUD_TABLE_BIT (_AT(pudval_t, 1) << 1)
	126	#define PUD_TYPE_MASK (_AT(pudval_t, 3) << 0)
	127	#define PUD_TYPE_SECT (_AT(pudval_t, 1) << 0)
084bd298 SC	128
084bd298 SC	129	/*
4f04d8f0 CM	130	* Level 2 descriptor (PMD).
	131	*/
	132	#define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0)
	133	#define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0)
	134	#define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0)
	135	#define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0)
084bd298	136	#define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1)
4f04d8f0 CM	137
	138	/*
	139	* Section
	140	*/
af074848	141	#define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0)
af074848 SC	142	#define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */
af074848 SC	143	#define PMD_SECT_RDONLY (_AT(pmdval_t, 1) << 7) /* AP[2] */
4f04d8f0 CM	144	#define PMD_SECT_S (_AT(pmdval_t, 3) << 8)
	145	#define PMD_SECT_AF (_AT(pmdval_t, 1) << 10)
	146	#define PMD_SECT_NG (_AT(pmdval_t, 1) << 11)
ecf35a23	147	#define PMD_SECT_CONT (_AT(pmdval_t, 1) << 52)
8e620b04 CM	148	#define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53)
8e620b04 CM	149	#define PMD_SECT_UXN (_AT(pmdval_t, 1) << 54)
4f04d8f0 CM	150
	151	/*
	152	* AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
	153	*/
	154	#define PMD_ATTRINDX(t) (_AT(pmdval_t, (t)) << 2)
	155	#define PMD_ATTRINDX_MASK (_AT(pmdval_t, 7) << 2)
	156
	157	/*
	158	* Level 3 descriptor (PTE).
	159	*/
	160	#define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0)
	161	#define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0)
	162	#define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0)
084bd298	163	#define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1)
4f04d8f0 CM	164	#define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */
	165	#define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */
	166	#define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */
	167	#define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */
	168	#define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */
2f4b829c	169	#define PTE_DBM (_AT(pteval_t, 1) << 51) /* Dirty Bit Management */
ecf35a23	170	#define PTE_CONT (_AT(pteval_t, 1) << 52) /* Contiguous range */
8e620b04 CM	171	#define PTE_PXN (_AT(pteval_t, 1) << 53) /* Privileged XN */
8e620b04 CM	172	#define PTE_UXN (_AT(pteval_t, 1) << 54) /* User XN */
1166f3fe	173	#define PTE_HYP_XN (_AT(pteval_t, 1) << 54) /* HYP XN */
4f04d8f0	174
e6d588a8	175	#define PTE_ADDR_LOW (((_AT(pteval_t, 1) << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT)
75387b92	176	#ifdef CONFIG_ARM64_PA_BITS_52
e6d588a8	177	#define PTE_ADDR_HIGH (_AT(pteval_t, 0xf) << 12)
75387b92 KM	178	#define PTE_ADDR_MASK (PTE_ADDR_LOW \| PTE_ADDR_HIGH)
	179	#else
	180	#define PTE_ADDR_MASK PTE_ADDR_LOW
e6d588a8 KM	181	#endif
e6d588a8 KM	182
4f04d8f0 CM	183	/*
	184	* AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
	185	*/
	186	#define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2)
	187	#define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2)
	188
36311607 MZ	189	/*
	190	* 2nd stage PTE definitions
	191	*/
	192	#define PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[2:1] */
	193	#define PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */
fefb876b	194	#define PTE_S2_XN (_AT(pteval_t, 2) << 53) /* XN[1:0] */
36311607	195
8199ed0e	196	#define PMD_S2_RDONLY (_AT(pmdval_t, 1) << 6) /* HAP[2:1] */
ad361f09	197	#define PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */
fefb876b	198	#define PMD_S2_XN (_AT(pmdval_t, 2) << 53) /* XN[1:0] */
ad361f09	199
36311607 MZ	200	/*
	201	* Memory Attribute override for Stage-2 (MemAttr[3:0])
	202	*/
	203	#define PTE_S2_MEMATTR(t) (_AT(pteval_t, (t)) << 2)
	204	#define PTE_S2_MEMATTR_MASK (_AT(pteval_t, 0xf) << 2)
	205
	206	/*
	207	* EL2/HYP PTE/PMD definitions
	208	*/
	209	#define PMD_HYP PMD_SECT_USER
	210	#define PTE_HYP PTE_USER
	211
4f04d8f0	212	/*
87366d8c	213	* Highest possible physical address supported.
4f04d8f0	214	*/
982aa7c5	215	#define PHYS_MASK_SHIFT (CONFIG_ARM64_PA_BITS)
4f04d8f0 CM	216	#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)
4f04d8f0 CM	217
5ffdfaed VM	218	#define TTBR_CNP_BIT (UL(1) << 0)
5ffdfaed VM	219
4f04d8f0 CM	220	/*
	221	* TCR flags.
	222	*/
dd006da2 AB	223	#define TCR_T0SZ_OFFSET 0
	224	#define TCR_T1SZ_OFFSET 16
	225	#define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_T0SZ_OFFSET)
	226	#define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_T1SZ_OFFSET)
	227	#define TCR_TxSZ(x) (TCR_T0SZ(x) \| TCR_T1SZ(x))
	228	#define TCR_TxSZ_WIDTH 6
adf75899	229	#define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)
a563f759	230
793d5d92 MZ	231	#define TCR_EPD0_SHIFT 7
793d5d92 MZ	232	#define TCR_EPD0_MASK (UL(1) << TCR_EPD0_SHIFT)
a563f759 SP	233	#define TCR_IRGN0_SHIFT 8
	234	#define TCR_IRGN0_MASK (UL(3) << TCR_IRGN0_SHIFT)
	235	#define TCR_IRGN0_NC (UL(0) << TCR_IRGN0_SHIFT)
	236	#define TCR_IRGN0_WBWA (UL(1) << TCR_IRGN0_SHIFT)
	237	#define TCR_IRGN0_WT (UL(2) << TCR_IRGN0_SHIFT)
	238	#define TCR_IRGN0_WBnWA (UL(3) << TCR_IRGN0_SHIFT)
	239
793d5d92 MZ	240	#define TCR_EPD1_SHIFT 23
793d5d92 MZ	241	#define TCR_EPD1_MASK (UL(1) << TCR_EPD1_SHIFT)
a563f759 SP	242	#define TCR_IRGN1_SHIFT 24
	243	#define TCR_IRGN1_MASK (UL(3) << TCR_IRGN1_SHIFT)
	244	#define TCR_IRGN1_NC (UL(0) << TCR_IRGN1_SHIFT)
	245	#define TCR_IRGN1_WBWA (UL(1) << TCR_IRGN1_SHIFT)
	246	#define TCR_IRGN1_WT (UL(2) << TCR_IRGN1_SHIFT)
	247	#define TCR_IRGN1_WBnWA (UL(3) << TCR_IRGN1_SHIFT)
	248
	249	#define TCR_IRGN_NC (TCR_IRGN0_NC \| TCR_IRGN1_NC)
	250	#define TCR_IRGN_WBWA (TCR_IRGN0_WBWA \| TCR_IRGN1_WBWA)
	251	#define TCR_IRGN_WT (TCR_IRGN0_WT \| TCR_IRGN1_WT)
	252	#define TCR_IRGN_WBnWA (TCR_IRGN0_WBnWA \| TCR_IRGN1_WBnWA)
	253	#define TCR_IRGN_MASK (TCR_IRGN0_MASK \| TCR_IRGN1_MASK)
	254
	255
	256	#define TCR_ORGN0_SHIFT 10
	257	#define TCR_ORGN0_MASK (UL(3) << TCR_ORGN0_SHIFT)
	258	#define TCR_ORGN0_NC (UL(0) << TCR_ORGN0_SHIFT)
	259	#define TCR_ORGN0_WBWA (UL(1) << TCR_ORGN0_SHIFT)
	260	#define TCR_ORGN0_WT (UL(2) << TCR_ORGN0_SHIFT)
	261	#define TCR_ORGN0_WBnWA (UL(3) << TCR_ORGN0_SHIFT)
	262
	263	#define TCR_ORGN1_SHIFT 26
	264	#define TCR_ORGN1_MASK (UL(3) << TCR_ORGN1_SHIFT)
	265	#define TCR_ORGN1_NC (UL(0) << TCR_ORGN1_SHIFT)
	266	#define TCR_ORGN1_WBWA (UL(1) << TCR_ORGN1_SHIFT)
	267	#define TCR_ORGN1_WT (UL(2) << TCR_ORGN1_SHIFT)
	268	#define TCR_ORGN1_WBnWA (UL(3) << TCR_ORGN1_SHIFT)
	269
	270	#define TCR_ORGN_NC (TCR_ORGN0_NC \| TCR_ORGN1_NC)
	271	#define TCR_ORGN_WBWA (TCR_ORGN0_WBWA \| TCR_ORGN1_WBWA)
	272	#define TCR_ORGN_WT (TCR_ORGN0_WT \| TCR_ORGN1_WT)
	273	#define TCR_ORGN_WBnWA (TCR_ORGN0_WBnWA \| TCR_ORGN1_WBnWA)
	274	#define TCR_ORGN_MASK (TCR_ORGN0_MASK \| TCR_ORGN1_MASK)
	275
	276	#define TCR_SH0_SHIFT 12
	277	#define TCR_SH0_MASK (UL(3) << TCR_SH0_SHIFT)
	278	#define TCR_SH0_INNER (UL(3) << TCR_SH0_SHIFT)
	279
	280	#define TCR_SH1_SHIFT 28
	281	#define TCR_SH1_MASK (UL(3) << TCR_SH1_SHIFT)
	282	#define TCR_SH1_INNER (UL(3) << TCR_SH1_SHIFT)
	283	#define TCR_SHARED (TCR_SH0_INNER \| TCR_SH1_INNER)
	284
	285	#define TCR_TG0_SHIFT 14
	286	#define TCR_TG0_MASK (UL(3) << TCR_TG0_SHIFT)
	287	#define TCR_TG0_4K (UL(0) << TCR_TG0_SHIFT)
	288	#define TCR_TG0_64K (UL(1) << TCR_TG0_SHIFT)
	289	#define TCR_TG0_16K (UL(2) << TCR_TG0_SHIFT)
	290
	291	#define TCR_TG1_SHIFT 30
	292	#define TCR_TG1_MASK (UL(3) << TCR_TG1_SHIFT)
	293	#define TCR_TG1_16K (UL(1) << TCR_TG1_SHIFT)
	294	#define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT)
	295	#define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT)
	296
787fd1d0 KM	297	#define TCR_IPS_SHIFT 32
787fd1d0 KM	298	#define TCR_IPS_MASK (UL(7) << TCR_IPS_SHIFT)
7655abb9	299	#define TCR_A1 (UL(1) << 22)
4f04d8f0	300	#define TCR_ASID16 (UL(1) << 36)
d50240a5	301	#define TCR_TBI0 (UL(1) << 37)
2f4b829c CM	302	#define TCR_HA (UL(1) << 39)
2f4b829c CM	303	#define TCR_HD (UL(1) << 40)
e03e61c3	304	#define TCR_NFD1 (UL(1) << 54)
4f04d8f0	305
529c4b05 KM	306	/*
	307	* TTBR.
	308	*/
	309	#ifdef CONFIG_ARM64_PA_BITS_52
	310	/*
	311	* This should be GENMASK_ULL(47, 2).
	312	* TTBR_ELx[1] is RES0 in this configuration.
	313	*/
	314	#define TTBR_BADDR_MASK_52 (((UL(1) << 46) - 1) << 2)
	315	#endif
	316
68d23da4	317	#ifdef CONFIG_ARM64_USER_VA_BITS_52
e842dfb5 SC	318	/* Must be at least 64-byte aligned to prevent corruption of the TTBR */
	319	#define TTBR1_BADDR_4852_OFFSET (((UL(1) << (52 - PGDIR_SHIFT)) - \
	320	(UL(1) << (48 - PGDIR_SHIFT))) * 8)
	321	#endif
	322
4f04d8f0	323	#endif