[mirror_ubuntu-focal-kernel.git] / arch / arm64 / include / asm / pgtable-hwdef.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2012 ARM Ltd.
 */
#ifndef __ASM_PGTABLE_HWDEF_H
#define __ASM_PGTABLE_HWDEF_H

#include <asm/memory.h>

/*
 * Number of page-table levels required to address 'va_bits' wide
 * address, without section mapping. We resolve the top (va_bits - PAGE_SHIFT)
 * bits with (PAGE_SHIFT - 3) bits at each page table level. Hence:
 *
 *  levels = DIV_ROUND_UP((va_bits - PAGE_SHIFT), (PAGE_SHIFT - 3))
 *
 * where DIV_ROUND_UP(n, d) => (((n) + (d) - 1) / (d))
 *
 * We cannot include linux/kernel.h which defines DIV_ROUND_UP here
 * due to build issues. So we open code DIV_ROUND_UP here:
 *
 *	((((va_bits) - PAGE_SHIFT) + (PAGE_SHIFT - 3) - 1) / (PAGE_SHIFT - 3))
 *
 * which gets simplified as :
 */
#define ARM64_HW_PGTABLE_LEVELS(va_bits) (((va_bits) - 4) / (PAGE_SHIFT - 3))

/*
 * Size mapped by an entry at level n ( 0 <= n <= 3)
 * We map (PAGE_SHIFT - 3) at all translation levels and PAGE_SHIFT bits
 * in the final page. The maximum number of translation levels supported by
 * the architecture is 4. Hence, starting at at level n, we have further
 * ((4 - n) - 1) levels of translation excluding the offset within the page.
 * So, the total number of bits mapped by an entry at level n is :
 *
 *  ((4 - n) - 1) * (PAGE_SHIFT - 3) + PAGE_SHIFT
 *
 * Rearranging it a bit we get :
 *   (4 - n) * (PAGE_SHIFT - 3) + 3
 */
#define ARM64_HW_PGTABLE_LEVEL_SHIFT(n)	((PAGE_SHIFT - 3) * (4 - (n)) + 3)

#define PTRS_PER_PTE		(1 << (PAGE_SHIFT - 3))

/*
 * PMD_SHIFT determines the size a level 2 page table entry can map.
 */
#if CONFIG_PGTABLE_LEVELS > 2
#define PMD_SHIFT		ARM64_HW_PGTABLE_LEVEL_SHIFT(2)
#define PMD_SIZE		(_AC(1, UL) << PMD_SHIFT)
#define PMD_MASK		(~(PMD_SIZE-1))
#define PTRS_PER_PMD		PTRS_PER_PTE
#endif

/*
 * PUD_SHIFT determines the size a level 1 page table entry can map.
 */
#if CONFIG_PGTABLE_LEVELS > 3
#define PUD_SHIFT		ARM64_HW_PGTABLE_LEVEL_SHIFT(1)
#define PUD_SIZE		(_AC(1, UL) << PUD_SHIFT)
#define PUD_MASK		(~(PUD_SIZE-1))
#define PTRS_PER_PUD		PTRS_PER_PTE
#endif

/*
 * PGDIR_SHIFT determines the size a top-level page table entry can map
 * (depending on the configuration, this level can be 0, 1 or 2).
 */
#define PGDIR_SHIFT		ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - CONFIG_PGTABLE_LEVELS)
#define PGDIR_SIZE		(_AC(1, UL) << PGDIR_SHIFT)
#define PGDIR_MASK		(~(PGDIR_SIZE-1))
#define PTRS_PER_PGD		(1 << (MAX_USER_VA_BITS - PGDIR_SHIFT))

/*
 * Section address mask and size definitions.
 */
#define SECTION_SHIFT		PMD_SHIFT
#define SECTION_SIZE		(_AC(1, UL) << SECTION_SHIFT)
#define SECTION_MASK		(~(SECTION_SIZE-1))

/*
 * Contiguous page definitions.
 */
#ifdef CONFIG_ARM64_64K_PAGES
#define CONT_PTE_SHIFT		5
#define CONT_PMD_SHIFT		5
#elif defined(CONFIG_ARM64_16K_PAGES)
#define CONT_PTE_SHIFT		7
#define CONT_PMD_SHIFT		5
#else
#define CONT_PTE_SHIFT		4
#define CONT_PMD_SHIFT		4
#endif

#define CONT_PTES		(1 << CONT_PTE_SHIFT)
#define CONT_PTE_SIZE		(CONT_PTES * PAGE_SIZE)
#define CONT_PTE_MASK		(~(CONT_PTE_SIZE - 1))
#define CONT_PMDS		(1 << CONT_PMD_SHIFT)
#define CONT_PMD_SIZE		(CONT_PMDS * PMD_SIZE)
#define CONT_PMD_MASK		(~(CONT_PMD_SIZE - 1))
/* the the numerical offset of the PTE within a range of CONT_PTES */
#define CONT_RANGE_OFFSET(addr) (((addr)>>PAGE_SHIFT)&(CONT_PTES-1))

/*
 * Hardware page table definitions.
 *
 * Level 1 descriptor (PUD).
 */
#define PUD_TYPE_TABLE		(_AT(pudval_t, 3) << 0)
#define PUD_TABLE_BIT		(_AT(pudval_t, 1) << 1)
#define PUD_TYPE_MASK		(_AT(pudval_t, 3) << 0)
#define PUD_TYPE_SECT		(_AT(pudval_t, 1) << 0)

/*
 * Level 2 descriptor (PMD).
 */
#define PMD_TYPE_MASK		(_AT(pmdval_t, 3) << 0)
#define PMD_TYPE_FAULT		(_AT(pmdval_t, 0) << 0)
#define PMD_TYPE_TABLE		(_AT(pmdval_t, 3) << 0)
#define PMD_TYPE_SECT		(_AT(pmdval_t, 1) << 0)
#define PMD_TABLE_BIT		(_AT(pmdval_t, 1) << 1)

/*
 * Section
 */
#define PMD_SECT_VALID		(_AT(pmdval_t, 1) << 0)
#define PMD_SECT_USER		(_AT(pmdval_t, 1) << 6)		/* AP[1] */
#define PMD_SECT_RDONLY		(_AT(pmdval_t, 1) << 7)		/* AP[2] */
#define PMD_SECT_S		(_AT(pmdval_t, 3) << 8)
#define PMD_SECT_AF		(_AT(pmdval_t, 1) << 10)
#define PMD_SECT_NG		(_AT(pmdval_t, 1) << 11)
#define PMD_SECT_CONT		(_AT(pmdval_t, 1) << 52)
#define PMD_SECT_PXN		(_AT(pmdval_t, 1) << 53)
#define PMD_SECT_UXN		(_AT(pmdval_t, 1) << 54)

/*
 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
 */
#define PMD_ATTRINDX(t)		(_AT(pmdval_t, (t)) << 2)
#define PMD_ATTRINDX_MASK	(_AT(pmdval_t, 7) << 2)

/*
 * Level 3 descriptor (PTE).
 */
#define PTE_TYPE_MASK		(_AT(pteval_t, 3) << 0)
#define PTE_TYPE_FAULT		(_AT(pteval_t, 0) << 0)
#define PTE_TYPE_PAGE		(_AT(pteval_t, 3) << 0)
#define PTE_TABLE_BIT		(_AT(pteval_t, 1) << 1)
#define PTE_USER		(_AT(pteval_t, 1) << 6)		/* AP[1] */
#define PTE_RDONLY		(_AT(pteval_t, 1) << 7)		/* AP[2] */
#define PTE_SHARED		(_AT(pteval_t, 3) << 8)		/* SH[1:0], inner shareable */
#define PTE_AF			(_AT(pteval_t, 1) << 10)	/* Access Flag */
#define PTE_NG			(_AT(pteval_t, 1) << 11)	/* nG */
#define PTE_DBM			(_AT(pteval_t, 1) << 51)	/* Dirty Bit Management */
#define PTE_CONT		(_AT(pteval_t, 1) << 52)	/* Contiguous range */
#define PTE_PXN			(_AT(pteval_t, 1) << 53)	/* Privileged XN */
#define PTE_UXN			(_AT(pteval_t, 1) << 54)	/* User XN */
#define PTE_HYP_XN		(_AT(pteval_t, 1) << 54)	/* HYP XN */

#define PTE_ADDR_LOW		(((_AT(pteval_t, 1) << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT)
#ifdef CONFIG_ARM64_PA_BITS_52
#define PTE_ADDR_HIGH		(_AT(pteval_t, 0xf) << 12)
#define PTE_ADDR_MASK		(PTE_ADDR_LOW | PTE_ADDR_HIGH)
#else
#define PTE_ADDR_MASK		PTE_ADDR_LOW
#endif

/*
 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
 */
#define PTE_ATTRINDX(t)		(_AT(pteval_t, (t)) << 2)
#define PTE_ATTRINDX_MASK	(_AT(pteval_t, 7) << 2)

/*
 * 2nd stage PTE definitions
 */
#define PTE_S2_RDONLY		(_AT(pteval_t, 1) << 6)   /* HAP[2:1] */
#define PTE_S2_RDWR		(_AT(pteval_t, 3) << 6)   /* HAP[2:1] */
#define PTE_S2_XN		(_AT(pteval_t, 2) << 53)  /* XN[1:0] */

#define PMD_S2_RDONLY		(_AT(pmdval_t, 1) << 6)   /* HAP[2:1] */
#define PMD_S2_RDWR		(_AT(pmdval_t, 3) << 6)   /* HAP[2:1] */
#define PMD_S2_XN		(_AT(pmdval_t, 2) << 53)  /* XN[1:0] */

#define PUD_S2_RDONLY		(_AT(pudval_t, 1) << 6)   /* HAP[2:1] */
#define PUD_S2_RDWR		(_AT(pudval_t, 3) << 6)   /* HAP[2:1] */
#define PUD_S2_XN		(_AT(pudval_t, 2) << 53)  /* XN[1:0] */

/*
 * Memory Attribute override for Stage-2 (MemAttr[3:0])
 */
#define PTE_S2_MEMATTR(t)	(_AT(pteval_t, (t)) << 2)
#define PTE_S2_MEMATTR_MASK	(_AT(pteval_t, 0xf) << 2)

/*
 * EL2/HYP PTE/PMD definitions
 */
#define PMD_HYP			PMD_SECT_USER
#define PTE_HYP			PTE_USER

/*
 * Highest possible physical address supported.
 */
#define PHYS_MASK_SHIFT		(CONFIG_ARM64_PA_BITS)
#define PHYS_MASK		((UL(1) << PHYS_MASK_SHIFT) - 1)

#define TTBR_CNP_BIT		(UL(1) << 0)

/*
 * TCR flags.
 */
#define TCR_T0SZ_OFFSET		0
#define TCR_T1SZ_OFFSET		16
#define TCR_T0SZ(x)		((UL(64) - (x)) << TCR_T0SZ_OFFSET)
#define TCR_T1SZ(x)		((UL(64) - (x)) << TCR_T1SZ_OFFSET)
#define TCR_TxSZ(x)		(TCR_T0SZ(x) | TCR_T1SZ(x))
#define TCR_TxSZ_WIDTH		6
#define TCR_T0SZ_MASK		(((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)

#define TCR_EPD0_SHIFT		7
#define TCR_EPD0_MASK		(UL(1) << TCR_EPD0_SHIFT)
#define TCR_IRGN0_SHIFT		8
#define TCR_IRGN0_MASK		(UL(3) << TCR_IRGN0_SHIFT)
#define TCR_IRGN0_NC		(UL(0) << TCR_IRGN0_SHIFT)
#define TCR_IRGN0_WBWA		(UL(1) << TCR_IRGN0_SHIFT)
#define TCR_IRGN0_WT		(UL(2) << TCR_IRGN0_SHIFT)
#define TCR_IRGN0_WBnWA		(UL(3) << TCR_IRGN0_SHIFT)

#define TCR_EPD1_SHIFT		23
#define TCR_EPD1_MASK		(UL(1) << TCR_EPD1_SHIFT)
#define TCR_IRGN1_SHIFT		24
#define TCR_IRGN1_MASK		(UL(3) << TCR_IRGN1_SHIFT)
#define TCR_IRGN1_NC		(UL(0) << TCR_IRGN1_SHIFT)
#define TCR_IRGN1_WBWA		(UL(1) << TCR_IRGN1_SHIFT)
#define TCR_IRGN1_WT		(UL(2) << TCR_IRGN1_SHIFT)
#define TCR_IRGN1_WBnWA		(UL(3) << TCR_IRGN1_SHIFT)

#define TCR_IRGN_NC		(TCR_IRGN0_NC | TCR_IRGN1_NC)
#define TCR_IRGN_WBWA		(TCR_IRGN0_WBWA | TCR_IRGN1_WBWA)
#define TCR_IRGN_WT		(TCR_IRGN0_WT | TCR_IRGN1_WT)
#define TCR_IRGN_WBnWA		(TCR_IRGN0_WBnWA | TCR_IRGN1_WBnWA)
#define TCR_IRGN_MASK		(TCR_IRGN0_MASK | TCR_IRGN1_MASK)


#define TCR_ORGN0_SHIFT		10
#define TCR_ORGN0_MASK		(UL(3) << TCR_ORGN0_SHIFT)
#define TCR_ORGN0_NC		(UL(0) << TCR_ORGN0_SHIFT)
#define TCR_ORGN0_WBWA		(UL(1) << TCR_ORGN0_SHIFT)
#define TCR_ORGN0_WT		(UL(2) << TCR_ORGN0_SHIFT)
#define TCR_ORGN0_WBnWA		(UL(3) << TCR_ORGN0_SHIFT)

#define TCR_ORGN1_SHIFT		26
#define TCR_ORGN1_MASK		(UL(3) << TCR_ORGN1_SHIFT)
#define TCR_ORGN1_NC		(UL(0) << TCR_ORGN1_SHIFT)
#define TCR_ORGN1_WBWA		(UL(1) << TCR_ORGN1_SHIFT)
#define TCR_ORGN1_WT		(UL(2) << TCR_ORGN1_SHIFT)
#define TCR_ORGN1_WBnWA		(UL(3) << TCR_ORGN1_SHIFT)

#define TCR_ORGN_NC		(TCR_ORGN0_NC | TCR_ORGN1_NC)
#define TCR_ORGN_WBWA		(TCR_ORGN0_WBWA | TCR_ORGN1_WBWA)
#define TCR_ORGN_WT		(TCR_ORGN0_WT | TCR_ORGN1_WT)
#define TCR_ORGN_WBnWA		(TCR_ORGN0_WBnWA | TCR_ORGN1_WBnWA)
#define TCR_ORGN_MASK		(TCR_ORGN0_MASK | TCR_ORGN1_MASK)

#define TCR_SH0_SHIFT		12
#define TCR_SH0_MASK		(UL(3) << TCR_SH0_SHIFT)
#define TCR_SH0_INNER		(UL(3) << TCR_SH0_SHIFT)

#define TCR_SH1_SHIFT		28
#define TCR_SH1_MASK		(UL(3) << TCR_SH1_SHIFT)
#define TCR_SH1_INNER		(UL(3) << TCR_SH1_SHIFT)
#define TCR_SHARED		(TCR_SH0_INNER | TCR_SH1_INNER)

#define TCR_TG0_SHIFT		14
#define TCR_TG0_MASK		(UL(3) << TCR_TG0_SHIFT)
#define TCR_TG0_4K		(UL(0) << TCR_TG0_SHIFT)
#define TCR_TG0_64K		(UL(1) << TCR_TG0_SHIFT)
#define TCR_TG0_16K		(UL(2) << TCR_TG0_SHIFT)

#define TCR_TG1_SHIFT		30
#define TCR_TG1_MASK		(UL(3) << TCR_TG1_SHIFT)
#define TCR_TG1_16K		(UL(1) << TCR_TG1_SHIFT)
#define TCR_TG1_4K		(UL(2) << TCR_TG1_SHIFT)
#define TCR_TG1_64K		(UL(3) << TCR_TG1_SHIFT)

#define TCR_IPS_SHIFT		32
#define TCR_IPS_MASK		(UL(7) << TCR_IPS_SHIFT)
#define TCR_A1			(UL(1) << 22)
#define TCR_ASID16		(UL(1) << 36)
#define TCR_TBI0		(UL(1) << 37)
#define TCR_TBI1		(UL(1) << 38)
#define TCR_HA			(UL(1) << 39)
#define TCR_HD			(UL(1) << 40)
#define TCR_NFD0		(UL(1) << 53)
#define TCR_NFD1		(UL(1) << 54)

/*
 * TTBR.
 */
#ifdef CONFIG_ARM64_PA_BITS_52
/*
 * This should be GENMASK_ULL(47, 2).
 * TTBR_ELx[1] is RES0 in this configuration.
 */
#define TTBR_BADDR_MASK_52	(((UL(1) << 46) - 1) << 2)
#endif

#ifdef CONFIG_ARM64_USER_VA_BITS_52
/* Must be at least 64-byte aligned to prevent corruption of the TTBR */
#define TTBR1_BADDR_4852_OFFSET	(((UL(1) << (52 - PGDIR_SHIFT)) - \
				 (UL(1) << (48 - PGDIR_SHIFT))) * 8)
#endif

#endif
Commit	Line	Data
caab277b	1	/* SPDX-License-Identifier: GPL-2.0-only */
4f04d8f0 CM	2	/*
4f04d8f0 CM	3	* Copyright (C) 2012 ARM Ltd.
4f04d8f0 CM	4	*/
	5	#ifndef __ASM_PGTABLE_HWDEF_H
	6	#define __ASM_PGTABLE_HWDEF_H
	7
529c4b05 KM	8	#include <asm/memory.h>
529c4b05 KM	9
686e7838 SP	10	/*
	11	* Number of page-table levels required to address 'va_bits' wide
	12	* address, without section mapping. We resolve the top (va_bits - PAGE_SHIFT)
	13	* bits with (PAGE_SHIFT - 3) bits at each page table level. Hence:
	14	*
	15	* levels = DIV_ROUND_UP((va_bits - PAGE_SHIFT), (PAGE_SHIFT - 3))
	16	*
	17	* where DIV_ROUND_UP(n, d) => (((n) + (d) - 1) / (d))
	18	*
	19	* We cannot include linux/kernel.h which defines DIV_ROUND_UP here
	20	* due to build issues. So we open code DIV_ROUND_UP here:
	21	*
	22	* ((((va_bits) - PAGE_SHIFT) + (PAGE_SHIFT - 3) - 1) / (PAGE_SHIFT - 3))
	23	*
	24	* which gets simplified as :
	25	*/
	26	#define ARM64_HW_PGTABLE_LEVELS(va_bits) (((va_bits) - 4) / (PAGE_SHIFT - 3))
	27
	28	/*
	29	* Size mapped by an entry at level n ( 0 <= n <= 3)
	30	* We map (PAGE_SHIFT - 3) at all translation levels and PAGE_SHIFT bits
	31	* in the final page. The maximum number of translation levels supported by
	32	* the architecture is 4. Hence, starting at at level n, we have further
	33	* ((4 - n) - 1) levels of translation excluding the offset within the page.
	34	* So, the total number of bits mapped by an entry at level n is :
	35	*
	36	* ((4 - n) - 1) * (PAGE_SHIFT - 3) + PAGE_SHIFT
	37	*
	38	* Rearranging it a bit we get :
	39	* (4 - n) * (PAGE_SHIFT - 3) + 3
	40	*/
	41	#define ARM64_HW_PGTABLE_LEVEL_SHIFT(n) ((PAGE_SHIFT - 3) * (4 - (n)) + 3)
	42
6b4fee24 CM	43	#define PTRS_PER_PTE (1 << (PAGE_SHIFT - 3))
	44
	45	/*
	46	* PMD_SHIFT determines the size a level 2 page table entry can map.
	47	*/
9f25e6ad	48	#if CONFIG_PGTABLE_LEVELS > 2
686e7838	49	#define PMD_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(2)
6b4fee24 CM	50	#define PMD_SIZE (_AC(1, UL) << PMD_SHIFT)
	51	#define PMD_MASK (~(PMD_SIZE-1))
	52	#define PTRS_PER_PMD PTRS_PER_PTE
	53	#endif
	54
	55	/*
	56	* PUD_SHIFT determines the size a level 1 page table entry can map.
	57	*/
9f25e6ad	58	#if CONFIG_PGTABLE_LEVELS > 3
686e7838	59	#define PUD_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(1)
6b4fee24 CM	60	#define PUD_SIZE (_AC(1, UL) << PUD_SHIFT)
	61	#define PUD_MASK (~(PUD_SIZE-1))
	62	#define PTRS_PER_PUD PTRS_PER_PTE
4f04d8f0 CM	63	#endif
4f04d8f0 CM	64
6b4fee24 CM	65	/*
	66	* PGDIR_SHIFT determines the size a top-level page table entry can map
	67	* (depending on the configuration, this level can be 0, 1 or 2).
	68	*/
686e7838	69	#define PGDIR_SHIFT ARM64_HW_PGTABLE_LEVEL_SHIFT(4 - CONFIG_PGTABLE_LEVELS)
6b4fee24 CM	70	#define PGDIR_SIZE (_AC(1, UL) << PGDIR_SHIFT)
6b4fee24 CM	71	#define PGDIR_MASK (~(PGDIR_SIZE-1))
9b31cf49	72	#define PTRS_PER_PGD (1 << (MAX_USER_VA_BITS - PGDIR_SHIFT))
6b4fee24 CM	73
	74	/*
	75	* Section address mask and size definitions.
	76	*/
	77	#define SECTION_SHIFT PMD_SHIFT
	78	#define SECTION_SIZE (_AC(1, UL) << SECTION_SHIFT)
	79	#define SECTION_MASK (~(SECTION_SIZE-1))
	80
ecf35a23 JL	81	/*
	82	* Contiguous page definitions.
	83	*/
66b3923a DW	84	#ifdef CONFIG_ARM64_64K_PAGES
	85	#define CONT_PTE_SHIFT 5
	86	#define CONT_PMD_SHIFT 5
	87	#elif defined(CONFIG_ARM64_16K_PAGES)
	88	#define CONT_PTE_SHIFT 7
	89	#define CONT_PMD_SHIFT 5
	90	#else
	91	#define CONT_PTE_SHIFT 4
	92	#define CONT_PMD_SHIFT 4
	93	#endif
	94
	95	#define CONT_PTES (1 << CONT_PTE_SHIFT)
	96	#define CONT_PTE_SIZE (CONT_PTES * PAGE_SIZE)
	97	#define CONT_PTE_MASK (~(CONT_PTE_SIZE - 1))
	98	#define CONT_PMDS (1 << CONT_PMD_SHIFT)
	99	#define CONT_PMD_SIZE (CONT_PMDS * PMD_SIZE)
	100	#define CONT_PMD_MASK (~(CONT_PMD_SIZE - 1))
ecf35a23 JL	101	/* the the numerical offset of the PTE within a range of CONT_PTES */
	102	#define CONT_RANGE_OFFSET(addr) (((addr)>>PAGE_SHIFT)&(CONT_PTES-1))
	103
4f04d8f0 CM	104	/*
	105	* Hardware page table definitions.
	106	*
084bd298 SC	107	* Level 1 descriptor (PUD).
084bd298 SC	108	*/
c79b954b	109	#define PUD_TYPE_TABLE (_AT(pudval_t, 3) << 0)
29d9bef1 PA	110	#define PUD_TABLE_BIT (_AT(pudval_t, 1) << 1)
	111	#define PUD_TYPE_MASK (_AT(pudval_t, 3) << 0)
	112	#define PUD_TYPE_SECT (_AT(pudval_t, 1) << 0)
084bd298 SC	113
084bd298 SC	114	/*
4f04d8f0 CM	115	* Level 2 descriptor (PMD).
	116	*/
	117	#define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0)
	118	#define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0)
	119	#define PMD_TYPE_TABLE (_AT(pmdval_t, 3) << 0)
	120	#define PMD_TYPE_SECT (_AT(pmdval_t, 1) << 0)
084bd298	121	#define PMD_TABLE_BIT (_AT(pmdval_t, 1) << 1)
4f04d8f0 CM	122
	123	/*
	124	* Section
	125	*/
af074848	126	#define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0)
af074848 SC	127	#define PMD_SECT_USER (_AT(pmdval_t, 1) << 6) /* AP[1] */
af074848 SC	128	#define PMD_SECT_RDONLY (_AT(pmdval_t, 1) << 7) /* AP[2] */
4f04d8f0 CM	129	#define PMD_SECT_S (_AT(pmdval_t, 3) << 8)
	130	#define PMD_SECT_AF (_AT(pmdval_t, 1) << 10)
	131	#define PMD_SECT_NG (_AT(pmdval_t, 1) << 11)
ecf35a23	132	#define PMD_SECT_CONT (_AT(pmdval_t, 1) << 52)
8e620b04 CM	133	#define PMD_SECT_PXN (_AT(pmdval_t, 1) << 53)
8e620b04 CM	134	#define PMD_SECT_UXN (_AT(pmdval_t, 1) << 54)
4f04d8f0 CM	135
	136	/*
	137	* AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
	138	*/
	139	#define PMD_ATTRINDX(t) (_AT(pmdval_t, (t)) << 2)
	140	#define PMD_ATTRINDX_MASK (_AT(pmdval_t, 7) << 2)
	141
	142	/*
	143	* Level 3 descriptor (PTE).
	144	*/
	145	#define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0)
	146	#define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0)
	147	#define PTE_TYPE_PAGE (_AT(pteval_t, 3) << 0)
084bd298	148	#define PTE_TABLE_BIT (_AT(pteval_t, 1) << 1)
4f04d8f0 CM	149	#define PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */
	150	#define PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */
	151	#define PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */
	152	#define PTE_AF (_AT(pteval_t, 1) << 10) /* Access Flag */
	153	#define PTE_NG (_AT(pteval_t, 1) << 11) /* nG */
2f4b829c	154	#define PTE_DBM (_AT(pteval_t, 1) << 51) /* Dirty Bit Management */
ecf35a23	155	#define PTE_CONT (_AT(pteval_t, 1) << 52) /* Contiguous range */
8e620b04 CM	156	#define PTE_PXN (_AT(pteval_t, 1) << 53) /* Privileged XN */
8e620b04 CM	157	#define PTE_UXN (_AT(pteval_t, 1) << 54) /* User XN */
1166f3fe	158	#define PTE_HYP_XN (_AT(pteval_t, 1) << 54) /* HYP XN */
4f04d8f0	159
e6d588a8	160	#define PTE_ADDR_LOW (((_AT(pteval_t, 1) << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT)
75387b92	161	#ifdef CONFIG_ARM64_PA_BITS_52
e6d588a8	162	#define PTE_ADDR_HIGH (_AT(pteval_t, 0xf) << 12)
75387b92 KM	163	#define PTE_ADDR_MASK (PTE_ADDR_LOW \| PTE_ADDR_HIGH)
	164	#else
	165	#define PTE_ADDR_MASK PTE_ADDR_LOW
e6d588a8 KM	166	#endif
e6d588a8 KM	167
4f04d8f0 CM	168	/*
	169	* AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
	170	*/
	171	#define PTE_ATTRINDX(t) (_AT(pteval_t, (t)) << 2)
	172	#define PTE_ATTRINDX_MASK (_AT(pteval_t, 7) << 2)
	173
36311607 MZ	174	/*
	175	* 2nd stage PTE definitions
	176	*/
	177	#define PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[2:1] */
	178	#define PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */
fefb876b	179	#define PTE_S2_XN (_AT(pteval_t, 2) << 53) /* XN[1:0] */
36311607	180
8199ed0e	181	#define PMD_S2_RDONLY (_AT(pmdval_t, 1) << 6) /* HAP[2:1] */
ad361f09	182	#define PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */
fefb876b	183	#define PMD_S2_XN (_AT(pmdval_t, 2) << 53) /* XN[1:0] */
ad361f09	184
b8e0ba7c PA	185	#define PUD_S2_RDONLY (_AT(pudval_t, 1) << 6) /* HAP[2:1] */
b8e0ba7c PA	186	#define PUD_S2_RDWR (_AT(pudval_t, 3) << 6) /* HAP[2:1] */
86d1c55e PA	187	#define PUD_S2_XN (_AT(pudval_t, 2) << 53) /* XN[1:0] */
86d1c55e PA	188
36311607 MZ	189	/*
	190	* Memory Attribute override for Stage-2 (MemAttr[3:0])
	191	*/
	192	#define PTE_S2_MEMATTR(t) (_AT(pteval_t, (t)) << 2)
	193	#define PTE_S2_MEMATTR_MASK (_AT(pteval_t, 0xf) << 2)
	194
	195	/*
	196	* EL2/HYP PTE/PMD definitions
	197	*/
	198	#define PMD_HYP PMD_SECT_USER
	199	#define PTE_HYP PTE_USER
	200
4f04d8f0	201	/*
87366d8c	202	* Highest possible physical address supported.
4f04d8f0	203	*/
982aa7c5	204	#define PHYS_MASK_SHIFT (CONFIG_ARM64_PA_BITS)
4f04d8f0 CM	205	#define PHYS_MASK ((UL(1) << PHYS_MASK_SHIFT) - 1)
4f04d8f0 CM	206
5ffdfaed VM	207	#define TTBR_CNP_BIT (UL(1) << 0)
5ffdfaed VM	208
4f04d8f0 CM	209	/*
	210	* TCR flags.
	211	*/
dd006da2 AB	212	#define TCR_T0SZ_OFFSET 0
	213	#define TCR_T1SZ_OFFSET 16
	214	#define TCR_T0SZ(x) ((UL(64) - (x)) << TCR_T0SZ_OFFSET)
	215	#define TCR_T1SZ(x) ((UL(64) - (x)) << TCR_T1SZ_OFFSET)
	216	#define TCR_TxSZ(x) (TCR_T0SZ(x) \| TCR_T1SZ(x))
	217	#define TCR_TxSZ_WIDTH 6
adf75899	218	#define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)
a563f759	219
793d5d92 MZ	220	#define TCR_EPD0_SHIFT 7
793d5d92 MZ	221	#define TCR_EPD0_MASK (UL(1) << TCR_EPD0_SHIFT)
a563f759 SP	222	#define TCR_IRGN0_SHIFT 8
	223	#define TCR_IRGN0_MASK (UL(3) << TCR_IRGN0_SHIFT)
	224	#define TCR_IRGN0_NC (UL(0) << TCR_IRGN0_SHIFT)
	225	#define TCR_IRGN0_WBWA (UL(1) << TCR_IRGN0_SHIFT)
	226	#define TCR_IRGN0_WT (UL(2) << TCR_IRGN0_SHIFT)
	227	#define TCR_IRGN0_WBnWA (UL(3) << TCR_IRGN0_SHIFT)
	228
793d5d92 MZ	229	#define TCR_EPD1_SHIFT 23
793d5d92 MZ	230	#define TCR_EPD1_MASK (UL(1) << TCR_EPD1_SHIFT)
a563f759 SP	231	#define TCR_IRGN1_SHIFT 24
	232	#define TCR_IRGN1_MASK (UL(3) << TCR_IRGN1_SHIFT)
	233	#define TCR_IRGN1_NC (UL(0) << TCR_IRGN1_SHIFT)
	234	#define TCR_IRGN1_WBWA (UL(1) << TCR_IRGN1_SHIFT)
	235	#define TCR_IRGN1_WT (UL(2) << TCR_IRGN1_SHIFT)
	236	#define TCR_IRGN1_WBnWA (UL(3) << TCR_IRGN1_SHIFT)
	237
	238	#define TCR_IRGN_NC (TCR_IRGN0_NC \| TCR_IRGN1_NC)
	239	#define TCR_IRGN_WBWA (TCR_IRGN0_WBWA \| TCR_IRGN1_WBWA)
	240	#define TCR_IRGN_WT (TCR_IRGN0_WT \| TCR_IRGN1_WT)
	241	#define TCR_IRGN_WBnWA (TCR_IRGN0_WBnWA \| TCR_IRGN1_WBnWA)
	242	#define TCR_IRGN_MASK (TCR_IRGN0_MASK \| TCR_IRGN1_MASK)
	243
	244
	245	#define TCR_ORGN0_SHIFT 10
	246	#define TCR_ORGN0_MASK (UL(3) << TCR_ORGN0_SHIFT)
	247	#define TCR_ORGN0_NC (UL(0) << TCR_ORGN0_SHIFT)
	248	#define TCR_ORGN0_WBWA (UL(1) << TCR_ORGN0_SHIFT)
	249	#define TCR_ORGN0_WT (UL(2) << TCR_ORGN0_SHIFT)
	250	#define TCR_ORGN0_WBnWA (UL(3) << TCR_ORGN0_SHIFT)
	251
	252	#define TCR_ORGN1_SHIFT 26
	253	#define TCR_ORGN1_MASK (UL(3) << TCR_ORGN1_SHIFT)
	254	#define TCR_ORGN1_NC (UL(0) << TCR_ORGN1_SHIFT)
	255	#define TCR_ORGN1_WBWA (UL(1) << TCR_ORGN1_SHIFT)
	256	#define TCR_ORGN1_WT (UL(2) << TCR_ORGN1_SHIFT)
	257	#define TCR_ORGN1_WBnWA (UL(3) << TCR_ORGN1_SHIFT)
	258
	259	#define TCR_ORGN_NC (TCR_ORGN0_NC \| TCR_ORGN1_NC)
	260	#define TCR_ORGN_WBWA (TCR_ORGN0_WBWA \| TCR_ORGN1_WBWA)
	261	#define TCR_ORGN_WT (TCR_ORGN0_WT \| TCR_ORGN1_WT)
	262	#define TCR_ORGN_WBnWA (TCR_ORGN0_WBnWA \| TCR_ORGN1_WBnWA)
	263	#define TCR_ORGN_MASK (TCR_ORGN0_MASK \| TCR_ORGN1_MASK)
	264
	265	#define TCR_SH0_SHIFT 12
	266	#define TCR_SH0_MASK (UL(3) << TCR_SH0_SHIFT)
	267	#define TCR_SH0_INNER (UL(3) << TCR_SH0_SHIFT)
	268
	269	#define TCR_SH1_SHIFT 28
	270	#define TCR_SH1_MASK (UL(3) << TCR_SH1_SHIFT)
	271	#define TCR_SH1_INNER (UL(3) << TCR_SH1_SHIFT)
	272	#define TCR_SHARED (TCR_SH0_INNER \| TCR_SH1_INNER)
	273
	274	#define TCR_TG0_SHIFT 14
	275	#define TCR_TG0_MASK (UL(3) << TCR_TG0_SHIFT)
	276	#define TCR_TG0_4K (UL(0) << TCR_TG0_SHIFT)
	277	#define TCR_TG0_64K (UL(1) << TCR_TG0_SHIFT)
	278	#define TCR_TG0_16K (UL(2) << TCR_TG0_SHIFT)
	279
	280	#define TCR_TG1_SHIFT 30
	281	#define TCR_TG1_MASK (UL(3) << TCR_TG1_SHIFT)
	282	#define TCR_TG1_16K (UL(1) << TCR_TG1_SHIFT)
	283	#define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT)
	284	#define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT)
	285
787fd1d0 KM	286	#define TCR_IPS_SHIFT 32
787fd1d0 KM	287	#define TCR_IPS_MASK (UL(7) << TCR_IPS_SHIFT)
7655abb9	288	#define TCR_A1 (UL(1) << 22)
4f04d8f0	289	#define TCR_ASID16 (UL(1) << 36)
d50240a5	290	#define TCR_TBI0 (UL(1) << 37)
21696c16	291	#define TCR_TBI1 (UL(1) << 38)
2f4b829c CM	292	#define TCR_HA (UL(1) << 39)
2f4b829c CM	293	#define TCR_HD (UL(1) << 40)
3e32131a	294	#define TCR_NFD0 (UL(1) << 53)
e03e61c3	295	#define TCR_NFD1 (UL(1) << 54)
4f04d8f0	296
529c4b05 KM	297	/*
	298	* TTBR.
	299	*/
	300	#ifdef CONFIG_ARM64_PA_BITS_52
	301	/*
	302	* This should be GENMASK_ULL(47, 2).
	303	* TTBR_ELx[1] is RES0 in this configuration.
	304	*/
	305	#define TTBR_BADDR_MASK_52 (((UL(1) << 46) - 1) << 2)
	306	#endif
	307
68d23da4	308	#ifdef CONFIG_ARM64_USER_VA_BITS_52
e842dfb5 SC	309	/* Must be at least 64-byte aligned to prevent corruption of the TTBR */
	310	#define TTBR1_BADDR_4852_OFFSET (((UL(1) << (52 - PGDIR_SHIFT)) - \
	311	(UL(1) << (48 - PGDIR_SHIFT))) * 8)
	312	#endif
	313
4f04d8f0	314	#endif