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4f04d8f0 CM |
1 | /* |
2 | * Copyright (C) 2012 ARM Ltd. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | #ifndef __ASM_PGTABLE_H | |
17 | #define __ASM_PGTABLE_H | |
18 | ||
2f4b829c | 19 | #include <asm/bug.h> |
4f04d8f0 CM |
20 | #include <asm/proc-fns.h> |
21 | ||
22 | #include <asm/memory.h> | |
23 | #include <asm/pgtable-hwdef.h> | |
3eca86e7 | 24 | #include <asm/pgtable-prot.h> |
4f04d8f0 CM |
25 | |
26 | /* | |
3e1907d5 | 27 | * VMALLOC range. |
08375198 | 28 | * |
f9040773 | 29 | * VMALLOC_START: beginning of the kernel vmalloc space |
3e1907d5 AB |
30 | * VMALLOC_END: extends to the available space below vmmemmap, PCI I/O space |
31 | * and fixed mappings | |
4f04d8f0 | 32 | */ |
f9040773 | 33 | #define VMALLOC_START (MODULES_END) |
08375198 | 34 | #define VMALLOC_END (PAGE_OFFSET - PUD_SIZE - VMEMMAP_SIZE - SZ_64K) |
4f04d8f0 | 35 | |
3bab79ed | 36 | #define vmemmap ((struct page *)VMEMMAP_START - (memstart_addr >> PAGE_SHIFT)) |
4f04d8f0 | 37 | |
d016bf7e | 38 | #define FIRST_USER_ADDRESS 0UL |
4f04d8f0 CM |
39 | |
40 | #ifndef __ASSEMBLY__ | |
2f4b829c | 41 | |
3bbf7157 | 42 | #include <asm/cmpxchg.h> |
961faac1 | 43 | #include <asm/fixmap.h> |
2f4b829c CM |
44 | #include <linux/mmdebug.h> |
45 | ||
4f04d8f0 CM |
46 | extern void __pte_error(const char *file, int line, unsigned long val); |
47 | extern void __pmd_error(const char *file, int line, unsigned long val); | |
c79b954b | 48 | extern void __pud_error(const char *file, int line, unsigned long val); |
4f04d8f0 CM |
49 | extern void __pgd_error(const char *file, int line, unsigned long val); |
50 | ||
4f04d8f0 CM |
51 | /* |
52 | * ZERO_PAGE is a global shared page that is always zero: used | |
53 | * for zero-mapped memory areas etc.. | |
54 | */ | |
5227cfa7 | 55 | extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; |
2077be67 | 56 | #define ZERO_PAGE(vaddr) phys_to_page(__pa_symbol(empty_zero_page)) |
4f04d8f0 | 57 | |
7078db46 CM |
58 | #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte)) |
59 | ||
4f04d8f0 CM |
60 | #define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT) |
61 | ||
62 | #define pfn_pte(pfn,prot) (__pte(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) | |
63 | ||
64 | #define pte_none(pte) (!pte_val(pte)) | |
65 | #define pte_clear(mm,addr,ptep) set_pte(ptep, __pte(0)) | |
66 | #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) | |
7078db46 | 67 | |
4f04d8f0 CM |
68 | /* |
69 | * The following only work if pte_present(). Undefined behaviour otherwise. | |
70 | */ | |
84fe6826 | 71 | #define pte_present(pte) (!!(pte_val(pte) & (PTE_VALID | PTE_PROT_NONE))) |
84fe6826 SC |
72 | #define pte_young(pte) (!!(pte_val(pte) & PTE_AF)) |
73 | #define pte_special(pte) (!!(pte_val(pte) & PTE_SPECIAL)) | |
74 | #define pte_write(pte) (!!(pte_val(pte) & PTE_WRITE)) | |
ec663d96 | 75 | #define pte_user_exec(pte) (!(pte_val(pte) & PTE_UXN)) |
93ef666a | 76 | #define pte_cont(pte) (!!(pte_val(pte) & PTE_CONT)) |
4f04d8f0 | 77 | |
d27cfa1f AB |
78 | #define pte_cont_addr_end(addr, end) \ |
79 | ({ unsigned long __boundary = ((addr) + CONT_PTE_SIZE) & CONT_PTE_MASK; \ | |
80 | (__boundary - 1 < (end) - 1) ? __boundary : (end); \ | |
81 | }) | |
82 | ||
83 | #define pmd_cont_addr_end(addr, end) \ | |
84 | ({ unsigned long __boundary = ((addr) + CONT_PMD_SIZE) & CONT_PMD_MASK; \ | |
85 | (__boundary - 1 < (end) - 1) ? __boundary : (end); \ | |
86 | }) | |
87 | ||
2f4b829c | 88 | #ifdef CONFIG_ARM64_HW_AFDBM |
b847415c | 89 | #define pte_hw_dirty(pte) (pte_write(pte) && !(pte_val(pte) & PTE_RDONLY)) |
2f4b829c CM |
90 | #else |
91 | #define pte_hw_dirty(pte) (0) | |
92 | #endif | |
93 | #define pte_sw_dirty(pte) (!!(pte_val(pte) & PTE_DIRTY)) | |
94 | #define pte_dirty(pte) (pte_sw_dirty(pte) || pte_hw_dirty(pte)) | |
95 | ||
766ffb69 | 96 | #define pte_valid(pte) (!!(pte_val(pte) & PTE_VALID)) |
ec663d96 CM |
97 | /* |
98 | * Execute-only user mappings do not have the PTE_USER bit set. All valid | |
99 | * kernel mappings have the PTE_UXN bit set. | |
100 | */ | |
101 | #define pte_valid_not_user(pte) \ | |
102 | ((pte_val(pte) & (PTE_VALID | PTE_USER | PTE_UXN)) == (PTE_VALID | PTE_UXN)) | |
76c714be WD |
103 | #define pte_valid_young(pte) \ |
104 | ((pte_val(pte) & (PTE_VALID | PTE_AF)) == (PTE_VALID | PTE_AF)) | |
105 | ||
106 | /* | |
107 | * Could the pte be present in the TLB? We must check mm_tlb_flush_pending | |
108 | * so that we don't erroneously return false for pages that have been | |
109 | * remapped as PROT_NONE but are yet to be flushed from the TLB. | |
110 | */ | |
111 | #define pte_accessible(mm, pte) \ | |
112 | (mm_tlb_flush_pending(mm) ? pte_present(pte) : pte_valid_young(pte)) | |
4f04d8f0 | 113 | |
b6d4f280 | 114 | static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot) |
44b6dfc5 | 115 | { |
b6d4f280 | 116 | pte_val(pte) &= ~pgprot_val(prot); |
44b6dfc5 SC |
117 | return pte; |
118 | } | |
119 | ||
b6d4f280 | 120 | static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot) |
44b6dfc5 | 121 | { |
b6d4f280 | 122 | pte_val(pte) |= pgprot_val(prot); |
44b6dfc5 SC |
123 | return pte; |
124 | } | |
125 | ||
b6d4f280 LA |
126 | static inline pte_t pte_wrprotect(pte_t pte) |
127 | { | |
128 | return clear_pte_bit(pte, __pgprot(PTE_WRITE)); | |
129 | } | |
130 | ||
131 | static inline pte_t pte_mkwrite(pte_t pte) | |
132 | { | |
133 | return set_pte_bit(pte, __pgprot(PTE_WRITE)); | |
134 | } | |
135 | ||
44b6dfc5 SC |
136 | static inline pte_t pte_mkclean(pte_t pte) |
137 | { | |
b6d4f280 | 138 | return clear_pte_bit(pte, __pgprot(PTE_DIRTY)); |
44b6dfc5 SC |
139 | } |
140 | ||
141 | static inline pte_t pte_mkdirty(pte_t pte) | |
142 | { | |
b6d4f280 | 143 | return set_pte_bit(pte, __pgprot(PTE_DIRTY)); |
44b6dfc5 SC |
144 | } |
145 | ||
146 | static inline pte_t pte_mkold(pte_t pte) | |
147 | { | |
b6d4f280 | 148 | return clear_pte_bit(pte, __pgprot(PTE_AF)); |
44b6dfc5 SC |
149 | } |
150 | ||
151 | static inline pte_t pte_mkyoung(pte_t pte) | |
152 | { | |
b6d4f280 | 153 | return set_pte_bit(pte, __pgprot(PTE_AF)); |
44b6dfc5 SC |
154 | } |
155 | ||
156 | static inline pte_t pte_mkspecial(pte_t pte) | |
157 | { | |
b6d4f280 | 158 | return set_pte_bit(pte, __pgprot(PTE_SPECIAL)); |
44b6dfc5 | 159 | } |
4f04d8f0 | 160 | |
93ef666a JL |
161 | static inline pte_t pte_mkcont(pte_t pte) |
162 | { | |
66b3923a DW |
163 | pte = set_pte_bit(pte, __pgprot(PTE_CONT)); |
164 | return set_pte_bit(pte, __pgprot(PTE_TYPE_PAGE)); | |
93ef666a JL |
165 | } |
166 | ||
167 | static inline pte_t pte_mknoncont(pte_t pte) | |
168 | { | |
169 | return clear_pte_bit(pte, __pgprot(PTE_CONT)); | |
170 | } | |
171 | ||
5ebe3a44 JM |
172 | static inline pte_t pte_clear_rdonly(pte_t pte) |
173 | { | |
174 | return clear_pte_bit(pte, __pgprot(PTE_RDONLY)); | |
175 | } | |
176 | ||
3bbf7157 CM |
177 | static inline pte_t pte_set_rdonly(pte_t pte) |
178 | { | |
179 | return set_pte_bit(pte, __pgprot(PTE_RDONLY)); | |
180 | } | |
181 | ||
5ebe3a44 JM |
182 | static inline pte_t pte_mkpresent(pte_t pte) |
183 | { | |
184 | return set_pte_bit(pte, __pgprot(PTE_VALID)); | |
185 | } | |
186 | ||
66b3923a DW |
187 | static inline pmd_t pmd_mkcont(pmd_t pmd) |
188 | { | |
189 | return __pmd(pmd_val(pmd) | PMD_SECT_CONT); | |
190 | } | |
191 | ||
4f04d8f0 CM |
192 | static inline void set_pte(pte_t *ptep, pte_t pte) |
193 | { | |
194 | *ptep = pte; | |
7f0b1bf0 CM |
195 | |
196 | /* | |
197 | * Only if the new pte is valid and kernel, otherwise TLB maintenance | |
198 | * or update_mmu_cache() have the necessary barriers. | |
199 | */ | |
ec663d96 | 200 | if (pte_valid_not_user(pte)) { |
7f0b1bf0 CM |
201 | dsb(ishst); |
202 | isb(); | |
203 | } | |
4f04d8f0 CM |
204 | } |
205 | ||
2f4b829c CM |
206 | struct mm_struct; |
207 | struct vm_area_struct; | |
208 | ||
4f04d8f0 CM |
209 | extern void __sync_icache_dcache(pte_t pteval, unsigned long addr); |
210 | ||
2f4b829c CM |
211 | /* |
212 | * PTE bits configuration in the presence of hardware Dirty Bit Management | |
213 | * (PTE_WRITE == PTE_DBM): | |
214 | * | |
215 | * Dirty Writable | PTE_RDONLY PTE_WRITE PTE_DIRTY (sw) | |
216 | * 0 0 | 1 0 0 | |
217 | * 0 1 | 1 1 0 | |
218 | * 1 0 | 1 0 1 | |
219 | * 1 1 | 0 1 x | |
220 | * | |
221 | * When hardware DBM is not present, the sofware PTE_DIRTY bit is updated via | |
222 | * the page fault mechanism. Checking the dirty status of a pte becomes: | |
223 | * | |
b847415c | 224 | * PTE_DIRTY || (PTE_WRITE && !PTE_RDONLY) |
2f4b829c | 225 | */ |
4f04d8f0 CM |
226 | static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, |
227 | pte_t *ptep, pte_t pte) | |
228 | { | |
fdc69e7d | 229 | if (pte_present(pte)) { |
2f4b829c | 230 | if (pte_sw_dirty(pte) && pte_write(pte)) |
c2c93e5b SC |
231 | pte_val(pte) &= ~PTE_RDONLY; |
232 | else | |
233 | pte_val(pte) |= PTE_RDONLY; | |
ec663d96 | 234 | if (pte_user_exec(pte) && !pte_special(pte)) |
ac15bd63 | 235 | __sync_icache_dcache(pte, addr); |
02522463 WD |
236 | } |
237 | ||
2f4b829c CM |
238 | /* |
239 | * If the existing pte is valid, check for potential race with | |
240 | * hardware updates of the pte (ptep_set_access_flags safely changes | |
241 | * valid ptes without going through an invalid entry). | |
242 | */ | |
82d34008 CM |
243 | if (IS_ENABLED(CONFIG_ARM64_HW_AFDBM) && |
244 | pte_valid(*ptep) && pte_valid(pte)) { | |
245 | VM_WARN_ONCE(!pte_young(pte), | |
246 | "%s: racy access flag clearing: 0x%016llx -> 0x%016llx", | |
247 | __func__, pte_val(*ptep), pte_val(pte)); | |
248 | VM_WARN_ONCE(pte_write(*ptep) && !pte_dirty(pte), | |
249 | "%s: racy dirty state clearing: 0x%016llx -> 0x%016llx", | |
250 | __func__, pte_val(*ptep), pte_val(pte)); | |
2f4b829c CM |
251 | } |
252 | ||
4f04d8f0 CM |
253 | set_pte(ptep, pte); |
254 | } | |
255 | ||
747a70e6 SC |
256 | #define __HAVE_ARCH_PTE_SAME |
257 | static inline int pte_same(pte_t pte_a, pte_t pte_b) | |
258 | { | |
259 | pteval_t lhs, rhs; | |
260 | ||
261 | lhs = pte_val(pte_a); | |
262 | rhs = pte_val(pte_b); | |
263 | ||
264 | if (pte_present(pte_a)) | |
265 | lhs &= ~PTE_RDONLY; | |
266 | ||
267 | if (pte_present(pte_b)) | |
268 | rhs &= ~PTE_RDONLY; | |
269 | ||
270 | return (lhs == rhs); | |
271 | } | |
272 | ||
4f04d8f0 CM |
273 | /* |
274 | * Huge pte definitions. | |
275 | */ | |
084bd298 SC |
276 | #define pte_huge(pte) (!(pte_val(pte) & PTE_TABLE_BIT)) |
277 | #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT)) | |
278 | ||
279 | /* | |
280 | * Hugetlb definitions. | |
281 | */ | |
66b3923a | 282 | #define HUGE_MAX_HSTATE 4 |
084bd298 SC |
283 | #define HPAGE_SHIFT PMD_SHIFT |
284 | #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT) | |
285 | #define HPAGE_MASK (~(HPAGE_SIZE - 1)) | |
286 | #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT) | |
4f04d8f0 | 287 | |
4f04d8f0 CM |
288 | #define __HAVE_ARCH_PTE_SPECIAL |
289 | ||
29e56940 SC |
290 | static inline pte_t pud_pte(pud_t pud) |
291 | { | |
292 | return __pte(pud_val(pud)); | |
293 | } | |
294 | ||
295 | static inline pmd_t pud_pmd(pud_t pud) | |
296 | { | |
297 | return __pmd(pud_val(pud)); | |
298 | } | |
299 | ||
9c7e535f SC |
300 | static inline pte_t pmd_pte(pmd_t pmd) |
301 | { | |
302 | return __pte(pmd_val(pmd)); | |
303 | } | |
af074848 | 304 | |
9c7e535f SC |
305 | static inline pmd_t pte_pmd(pte_t pte) |
306 | { | |
307 | return __pmd(pte_val(pte)); | |
308 | } | |
af074848 | 309 | |
8ce837ce AB |
310 | static inline pgprot_t mk_sect_prot(pgprot_t prot) |
311 | { | |
312 | return __pgprot(pgprot_val(prot) & ~PTE_TABLE_BIT); | |
313 | } | |
314 | ||
56166230 GK |
315 | #ifdef CONFIG_NUMA_BALANCING |
316 | /* | |
317 | * See the comment in include/asm-generic/pgtable.h | |
318 | */ | |
319 | static inline int pte_protnone(pte_t pte) | |
320 | { | |
321 | return (pte_val(pte) & (PTE_VALID | PTE_PROT_NONE)) == PTE_PROT_NONE; | |
322 | } | |
323 | ||
324 | static inline int pmd_protnone(pmd_t pmd) | |
325 | { | |
326 | return pte_protnone(pmd_pte(pmd)); | |
327 | } | |
328 | #endif | |
329 | ||
af074848 SC |
330 | /* |
331 | * THP definitions. | |
332 | */ | |
af074848 SC |
333 | |
334 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
335 | #define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT)) | |
29e56940 | 336 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ |
af074848 | 337 | |
5bb1cc0f | 338 | #define pmd_present(pmd) pte_present(pmd_pte(pmd)) |
c164e038 | 339 | #define pmd_dirty(pmd) pte_dirty(pmd_pte(pmd)) |
9c7e535f SC |
340 | #define pmd_young(pmd) pte_young(pmd_pte(pmd)) |
341 | #define pmd_wrprotect(pmd) pte_pmd(pte_wrprotect(pmd_pte(pmd))) | |
9c7e535f SC |
342 | #define pmd_mkold(pmd) pte_pmd(pte_mkold(pmd_pte(pmd))) |
343 | #define pmd_mkwrite(pmd) pte_pmd(pte_mkwrite(pmd_pte(pmd))) | |
ab4db1f2 | 344 | #define pmd_mkclean(pmd) pte_pmd(pte_mkclean(pmd_pte(pmd))) |
9c7e535f SC |
345 | #define pmd_mkdirty(pmd) pte_pmd(pte_mkdirty(pmd_pte(pmd))) |
346 | #define pmd_mkyoung(pmd) pte_pmd(pte_mkyoung(pmd_pte(pmd))) | |
5bb1cc0f | 347 | #define pmd_mknotpresent(pmd) (__pmd(pmd_val(pmd) & ~PMD_SECT_VALID)) |
af074848 | 348 | |
0dbd3b18 SP |
349 | #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd)) |
350 | ||
9c7e535f SC |
351 | #define __HAVE_ARCH_PMD_WRITE |
352 | #define pmd_write(pmd) pte_write(pmd_pte(pmd)) | |
af074848 SC |
353 | |
354 | #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT)) | |
355 | ||
356 | #define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT) | |
357 | #define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot))) | |
358 | #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot) | |
359 | ||
29e56940 | 360 | #define pud_write(pud) pte_write(pud_pte(pud)) |
206a2a73 | 361 | #define pud_pfn(pud) (((pud_val(pud) & PUD_MASK) & PHYS_MASK) >> PAGE_SHIFT) |
af074848 | 362 | |
ceb21835 | 363 | #define set_pmd_at(mm, addr, pmdp, pmd) set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)) |
af074848 | 364 | |
a501e324 CM |
365 | #define __pgprot_modify(prot,mask,bits) \ |
366 | __pgprot((pgprot_val(prot) & ~(mask)) | (bits)) | |
367 | ||
4f04d8f0 CM |
368 | /* |
369 | * Mark the prot value as uncacheable and unbufferable. | |
370 | */ | |
371 | #define pgprot_noncached(prot) \ | |
de2db743 | 372 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN) |
4f04d8f0 | 373 | #define pgprot_writecombine(prot) \ |
de2db743 | 374 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN) |
d1e6dc91 LD |
375 | #define pgprot_device(prot) \ |
376 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN) | |
4f04d8f0 CM |
377 | #define __HAVE_PHYS_MEM_ACCESS_PROT |
378 | struct file; | |
379 | extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, | |
380 | unsigned long size, pgprot_t vma_prot); | |
381 | ||
382 | #define pmd_none(pmd) (!pmd_val(pmd)) | |
4f04d8f0 | 383 | |
ab4db1f2 | 384 | #define pmd_bad(pmd) (!(pmd_val(pmd) & PMD_TABLE_BIT)) |
4f04d8f0 | 385 | |
36311607 MZ |
386 | #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ |
387 | PMD_TYPE_TABLE) | |
388 | #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \ | |
389 | PMD_TYPE_SECT) | |
390 | ||
cac4b8cd | 391 | #if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3 |
206a2a73 | 392 | #define pud_sect(pud) (0) |
523d6e9f | 393 | #define pud_table(pud) (1) |
206a2a73 SC |
394 | #else |
395 | #define pud_sect(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ | |
396 | PUD_TYPE_SECT) | |
523d6e9f | 397 | #define pud_table(pud) ((pud_val(pud) & PUD_TYPE_MASK) == \ |
398 | PUD_TYPE_TABLE) | |
206a2a73 | 399 | #endif |
36311607 | 400 | |
4f04d8f0 CM |
401 | static inline void set_pmd(pmd_t *pmdp, pmd_t pmd) |
402 | { | |
403 | *pmdp = pmd; | |
98f7685e | 404 | dsb(ishst); |
7f0b1bf0 | 405 | isb(); |
4f04d8f0 CM |
406 | } |
407 | ||
408 | static inline void pmd_clear(pmd_t *pmdp) | |
409 | { | |
410 | set_pmd(pmdp, __pmd(0)); | |
411 | } | |
412 | ||
dca56dca | 413 | static inline phys_addr_t pmd_page_paddr(pmd_t pmd) |
4f04d8f0 | 414 | { |
dca56dca | 415 | return pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK; |
4f04d8f0 CM |
416 | } |
417 | ||
053520f7 MR |
418 | /* Find an entry in the third-level page table. */ |
419 | #define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) | |
420 | ||
dca56dca MR |
421 | #define pte_offset_phys(dir,addr) (pmd_page_paddr(*(dir)) + pte_index(addr) * sizeof(pte_t)) |
422 | #define pte_offset_kernel(dir,addr) ((pte_t *)__va(pte_offset_phys((dir), (addr)))) | |
053520f7 MR |
423 | |
424 | #define pte_offset_map(dir,addr) pte_offset_kernel((dir), (addr)) | |
425 | #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr)) | |
426 | #define pte_unmap(pte) do { } while (0) | |
427 | #define pte_unmap_nested(pte) do { } while (0) | |
428 | ||
961faac1 MR |
429 | #define pte_set_fixmap(addr) ((pte_t *)set_fixmap_offset(FIX_PTE, addr)) |
430 | #define pte_set_fixmap_offset(pmd, addr) pte_set_fixmap(pte_offset_phys(pmd, addr)) | |
431 | #define pte_clear_fixmap() clear_fixmap(FIX_PTE) | |
432 | ||
4f04d8f0 CM |
433 | #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK)) |
434 | ||
6533945a AB |
435 | /* use ONLY for statically allocated translation tables */ |
436 | #define pte_offset_kimg(dir,addr) ((pte_t *)__phys_to_kimg(pte_offset_phys((dir), (addr)))) | |
437 | ||
4f04d8f0 CM |
438 | /* |
439 | * Conversion functions: convert a page and protection to a page entry, | |
440 | * and a page entry and page directory to the page they refer to. | |
441 | */ | |
442 | #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot) | |
443 | ||
9f25e6ad | 444 | #if CONFIG_PGTABLE_LEVELS > 2 |
4f04d8f0 | 445 | |
7078db46 CM |
446 | #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd)) |
447 | ||
4f04d8f0 | 448 | #define pud_none(pud) (!pud_val(pud)) |
ab4db1f2 | 449 | #define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT)) |
f02ab08a | 450 | #define pud_present(pud) pte_present(pud_pte(pud)) |
4f04d8f0 CM |
451 | |
452 | static inline void set_pud(pud_t *pudp, pud_t pud) | |
453 | { | |
454 | *pudp = pud; | |
98f7685e | 455 | dsb(ishst); |
7f0b1bf0 | 456 | isb(); |
4f04d8f0 CM |
457 | } |
458 | ||
459 | static inline void pud_clear(pud_t *pudp) | |
460 | { | |
461 | set_pud(pudp, __pud(0)); | |
462 | } | |
463 | ||
dca56dca | 464 | static inline phys_addr_t pud_page_paddr(pud_t pud) |
4f04d8f0 | 465 | { |
dca56dca | 466 | return pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK; |
4f04d8f0 CM |
467 | } |
468 | ||
7078db46 CM |
469 | /* Find an entry in the second-level page table. */ |
470 | #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)) | |
471 | ||
dca56dca MR |
472 | #define pmd_offset_phys(dir, addr) (pud_page_paddr(*(dir)) + pmd_index(addr) * sizeof(pmd_t)) |
473 | #define pmd_offset(dir, addr) ((pmd_t *)__va(pmd_offset_phys((dir), (addr)))) | |
7078db46 | 474 | |
961faac1 MR |
475 | #define pmd_set_fixmap(addr) ((pmd_t *)set_fixmap_offset(FIX_PMD, addr)) |
476 | #define pmd_set_fixmap_offset(pud, addr) pmd_set_fixmap(pmd_offset_phys(pud, addr)) | |
477 | #define pmd_clear_fixmap() clear_fixmap(FIX_PMD) | |
7078db46 | 478 | |
5d96e0cb | 479 | #define pud_page(pud) pfn_to_page(__phys_to_pfn(pud_val(pud) & PHYS_MASK)) |
29e56940 | 480 | |
6533945a AB |
481 | /* use ONLY for statically allocated translation tables */ |
482 | #define pmd_offset_kimg(dir,addr) ((pmd_t *)__phys_to_kimg(pmd_offset_phys((dir), (addr)))) | |
483 | ||
dca56dca MR |
484 | #else |
485 | ||
486 | #define pud_page_paddr(pud) ({ BUILD_BUG(); 0; }) | |
487 | ||
961faac1 MR |
488 | /* Match pmd_offset folding in <asm/generic/pgtable-nopmd.h> */ |
489 | #define pmd_set_fixmap(addr) NULL | |
490 | #define pmd_set_fixmap_offset(pudp, addr) ((pmd_t *)pudp) | |
491 | #define pmd_clear_fixmap() | |
492 | ||
6533945a AB |
493 | #define pmd_offset_kimg(dir,addr) ((pmd_t *)dir) |
494 | ||
9f25e6ad | 495 | #endif /* CONFIG_PGTABLE_LEVELS > 2 */ |
4f04d8f0 | 496 | |
9f25e6ad | 497 | #if CONFIG_PGTABLE_LEVELS > 3 |
c79b954b | 498 | |
7078db46 CM |
499 | #define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud)) |
500 | ||
c79b954b JL |
501 | #define pgd_none(pgd) (!pgd_val(pgd)) |
502 | #define pgd_bad(pgd) (!(pgd_val(pgd) & 2)) | |
503 | #define pgd_present(pgd) (pgd_val(pgd)) | |
504 | ||
505 | static inline void set_pgd(pgd_t *pgdp, pgd_t pgd) | |
506 | { | |
507 | *pgdp = pgd; | |
508 | dsb(ishst); | |
509 | } | |
510 | ||
511 | static inline void pgd_clear(pgd_t *pgdp) | |
512 | { | |
513 | set_pgd(pgdp, __pgd(0)); | |
514 | } | |
515 | ||
dca56dca | 516 | static inline phys_addr_t pgd_page_paddr(pgd_t pgd) |
c79b954b | 517 | { |
dca56dca | 518 | return pgd_val(pgd) & PHYS_MASK & (s32)PAGE_MASK; |
c79b954b JL |
519 | } |
520 | ||
7078db46 CM |
521 | /* Find an entry in the frst-level page table. */ |
522 | #define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) | |
523 | ||
dca56dca MR |
524 | #define pud_offset_phys(dir, addr) (pgd_page_paddr(*(dir)) + pud_index(addr) * sizeof(pud_t)) |
525 | #define pud_offset(dir, addr) ((pud_t *)__va(pud_offset_phys((dir), (addr)))) | |
7078db46 | 526 | |
961faac1 MR |
527 | #define pud_set_fixmap(addr) ((pud_t *)set_fixmap_offset(FIX_PUD, addr)) |
528 | #define pud_set_fixmap_offset(pgd, addr) pud_set_fixmap(pud_offset_phys(pgd, addr)) | |
529 | #define pud_clear_fixmap() clear_fixmap(FIX_PUD) | |
7078db46 | 530 | |
5d96e0cb JL |
531 | #define pgd_page(pgd) pfn_to_page(__phys_to_pfn(pgd_val(pgd) & PHYS_MASK)) |
532 | ||
6533945a AB |
533 | /* use ONLY for statically allocated translation tables */ |
534 | #define pud_offset_kimg(dir,addr) ((pud_t *)__phys_to_kimg(pud_offset_phys((dir), (addr)))) | |
535 | ||
dca56dca MR |
536 | #else |
537 | ||
538 | #define pgd_page_paddr(pgd) ({ BUILD_BUG(); 0;}) | |
539 | ||
961faac1 MR |
540 | /* Match pud_offset folding in <asm/generic/pgtable-nopud.h> */ |
541 | #define pud_set_fixmap(addr) NULL | |
542 | #define pud_set_fixmap_offset(pgdp, addr) ((pud_t *)pgdp) | |
543 | #define pud_clear_fixmap() | |
544 | ||
6533945a AB |
545 | #define pud_offset_kimg(dir,addr) ((pud_t *)dir) |
546 | ||
9f25e6ad | 547 | #endif /* CONFIG_PGTABLE_LEVELS > 3 */ |
c79b954b | 548 | |
7078db46 CM |
549 | #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd)) |
550 | ||
4f04d8f0 CM |
551 | /* to find an entry in a page-table-directory */ |
552 | #define pgd_index(addr) (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) | |
553 | ||
dca56dca MR |
554 | #define pgd_offset_raw(pgd, addr) ((pgd) + pgd_index(addr)) |
555 | ||
556 | #define pgd_offset(mm, addr) (pgd_offset_raw((mm)->pgd, (addr))) | |
4f04d8f0 CM |
557 | |
558 | /* to find an entry in a kernel page-table-directory */ | |
559 | #define pgd_offset_k(addr) pgd_offset(&init_mm, addr) | |
560 | ||
961faac1 MR |
561 | #define pgd_set_fixmap(addr) ((pgd_t *)set_fixmap_offset(FIX_PGD, addr)) |
562 | #define pgd_clear_fixmap() clear_fixmap(FIX_PGD) | |
563 | ||
4f04d8f0 CM |
564 | static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) |
565 | { | |
a6fadf7e | 566 | const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | |
1a541b4e | 567 | PTE_PROT_NONE | PTE_VALID | PTE_WRITE; |
2f4b829c CM |
568 | /* preserve the hardware dirty information */ |
569 | if (pte_hw_dirty(pte)) | |
62d96c71 | 570 | pte = pte_mkdirty(pte); |
4f04d8f0 CM |
571 | pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); |
572 | return pte; | |
573 | } | |
574 | ||
9c7e535f SC |
575 | static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) |
576 | { | |
577 | return pte_pmd(pte_modify(pmd_pte(pmd), newprot)); | |
578 | } | |
579 | ||
2f4b829c | 580 | #ifdef CONFIG_ARM64_HW_AFDBM |
66dbd6e6 CM |
581 | #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS |
582 | extern int ptep_set_access_flags(struct vm_area_struct *vma, | |
583 | unsigned long address, pte_t *ptep, | |
584 | pte_t entry, int dirty); | |
585 | ||
282aa705 CM |
586 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
587 | #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS | |
588 | static inline int pmdp_set_access_flags(struct vm_area_struct *vma, | |
589 | unsigned long address, pmd_t *pmdp, | |
590 | pmd_t entry, int dirty) | |
591 | { | |
592 | return ptep_set_access_flags(vma, address, (pte_t *)pmdp, pmd_pte(entry), dirty); | |
593 | } | |
594 | #endif | |
595 | ||
2f4b829c CM |
596 | /* |
597 | * Atomic pte/pmd modifications. | |
598 | */ | |
599 | #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG | |
06485053 | 600 | static inline int __ptep_test_and_clear_young(pte_t *ptep) |
2f4b829c | 601 | { |
3bbf7157 | 602 | pte_t old_pte, pte; |
2f4b829c | 603 | |
3bbf7157 CM |
604 | pte = READ_ONCE(*ptep); |
605 | do { | |
606 | old_pte = pte; | |
607 | pte = pte_mkold(pte); | |
608 | pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), | |
609 | pte_val(old_pte), pte_val(pte)); | |
610 | } while (pte_val(pte) != pte_val(old_pte)); | |
2f4b829c | 611 | |
3bbf7157 | 612 | return pte_young(pte); |
2f4b829c CM |
613 | } |
614 | ||
06485053 CM |
615 | static inline int ptep_test_and_clear_young(struct vm_area_struct *vma, |
616 | unsigned long address, | |
617 | pte_t *ptep) | |
618 | { | |
619 | return __ptep_test_and_clear_young(ptep); | |
620 | } | |
621 | ||
2f4b829c CM |
622 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
623 | #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG | |
624 | static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma, | |
625 | unsigned long address, | |
626 | pmd_t *pmdp) | |
627 | { | |
628 | return ptep_test_and_clear_young(vma, address, (pte_t *)pmdp); | |
629 | } | |
630 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
631 | ||
632 | #define __HAVE_ARCH_PTEP_GET_AND_CLEAR | |
633 | static inline pte_t ptep_get_and_clear(struct mm_struct *mm, | |
634 | unsigned long address, pte_t *ptep) | |
635 | { | |
3bbf7157 | 636 | return __pte(xchg_relaxed(&pte_val(*ptep), 0)); |
2f4b829c CM |
637 | } |
638 | ||
639 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
911f56ee CM |
640 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR |
641 | static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, | |
642 | unsigned long address, pmd_t *pmdp) | |
2f4b829c CM |
643 | { |
644 | return pte_pmd(ptep_get_and_clear(mm, address, (pte_t *)pmdp)); | |
645 | } | |
646 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
647 | ||
648 | /* | |
649 | * ptep_set_wrprotect - mark read-only while trasferring potential hardware | |
650 | * dirty status (PTE_DBM && !PTE_RDONLY) to the software PTE_DIRTY bit. | |
651 | */ | |
652 | #define __HAVE_ARCH_PTEP_SET_WRPROTECT | |
653 | static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep) | |
654 | { | |
3bbf7157 CM |
655 | pte_t old_pte, pte; |
656 | ||
657 | pte = READ_ONCE(*ptep); | |
658 | do { | |
659 | old_pte = pte; | |
660 | /* | |
661 | * If hardware-dirty (PTE_WRITE/DBM bit set and PTE_RDONLY | |
662 | * clear), set the PTE_DIRTY and PTE_RDONLY bits. | |
663 | */ | |
664 | if (pte_hw_dirty(pte)) { | |
665 | pte = pte_mkdirty(pte); | |
666 | pte = pte_set_rdonly(pte); | |
667 | } | |
668 | pte = pte_wrprotect(pte); | |
669 | pte_val(pte) = cmpxchg_relaxed(&pte_val(*ptep), | |
670 | pte_val(old_pte), pte_val(pte)); | |
671 | } while (pte_val(pte) != pte_val(old_pte)); | |
2f4b829c CM |
672 | } |
673 | ||
674 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
675 | #define __HAVE_ARCH_PMDP_SET_WRPROTECT | |
676 | static inline void pmdp_set_wrprotect(struct mm_struct *mm, | |
677 | unsigned long address, pmd_t *pmdp) | |
678 | { | |
679 | ptep_set_wrprotect(mm, address, (pte_t *)pmdp); | |
680 | } | |
681 | #endif | |
682 | #endif /* CONFIG_ARM64_HW_AFDBM */ | |
683 | ||
4f04d8f0 CM |
684 | extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; |
685 | extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; | |
686 | ||
4f04d8f0 CM |
687 | /* |
688 | * Encode and decode a swap entry: | |
3676f9ef | 689 | * bits 0-1: present (must be zero) |
9b3e661e KS |
690 | * bits 2-7: swap type |
691 | * bits 8-57: swap offset | |
fdc69e7d | 692 | * bit 58: PTE_PROT_NONE (must be zero) |
4f04d8f0 | 693 | */ |
9b3e661e | 694 | #define __SWP_TYPE_SHIFT 2 |
4f04d8f0 | 695 | #define __SWP_TYPE_BITS 6 |
9b3e661e | 696 | #define __SWP_OFFSET_BITS 50 |
4f04d8f0 CM |
697 | #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) |
698 | #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) | |
3676f9ef | 699 | #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) |
4f04d8f0 CM |
700 | |
701 | #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) | |
3676f9ef | 702 | #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) |
4f04d8f0 CM |
703 | #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) |
704 | ||
705 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | |
706 | #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val }) | |
707 | ||
708 | /* | |
709 | * Ensure that there are not more swap files than can be encoded in the kernel | |
aad9061b | 710 | * PTEs. |
4f04d8f0 CM |
711 | */ |
712 | #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS) | |
713 | ||
4f04d8f0 CM |
714 | extern int kern_addr_valid(unsigned long addr); |
715 | ||
716 | #include <asm-generic/pgtable.h> | |
717 | ||
39b5be9b WD |
718 | void pgd_cache_init(void); |
719 | #define pgtable_cache_init pgd_cache_init | |
4f04d8f0 | 720 | |
cba3574f WD |
721 | /* |
722 | * On AArch64, the cache coherency is handled via the set_pte_at() function. | |
723 | */ | |
724 | static inline void update_mmu_cache(struct vm_area_struct *vma, | |
725 | unsigned long addr, pte_t *ptep) | |
726 | { | |
727 | /* | |
120798d2 WD |
728 | * We don't do anything here, so there's a very small chance of |
729 | * us retaking a user fault which we just fixed up. The alternative | |
730 | * is doing a dsb(ishst), but that penalises the fastpath. | |
cba3574f | 731 | */ |
cba3574f WD |
732 | } |
733 | ||
734 | #define update_mmu_cache_pmd(vma, address, pmd) do { } while (0) | |
735 | ||
7db743c6 CM |
736 | #define kc_vaddr_to_offset(v) ((v) & ~VA_START) |
737 | #define kc_offset_to_vaddr(o) ((o) | VA_START) | |
738 | ||
4f04d8f0 CM |
739 | #endif /* !__ASSEMBLY__ */ |
740 | ||
741 | #endif /* __ASM_PGTABLE_H */ |